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1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef MLX5_IB_H
34 #define MLX5_IB_H
35 
36 #include <linux/kernel.h>
37 #include <linux/sched.h>
38 #include <rdma/ib_verbs.h>
39 #include <rdma/ib_smi.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/cq.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/srq.h>
44 #include <linux/types.h>
45 
46 #define mlx5_ib_dbg(dev, format, arg...)				\
47 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__,	\
48 	 __LINE__, current->pid, ##arg)
49 
50 #define mlx5_ib_err(dev, format, arg...)				\
51 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__,	\
52 	__LINE__, current->pid, ##arg)
53 
54 #define mlx5_ib_warn(dev, format, arg...)				\
55 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__,	\
56 	__LINE__, current->pid, ##arg)
57 
58 enum {
59 	MLX5_IB_MMAP_CMD_SHIFT	= 8,
60 	MLX5_IB_MMAP_CMD_MASK	= 0xff,
61 };
62 
63 enum mlx5_ib_mmap_cmd {
64 	MLX5_IB_MMAP_REGULAR_PAGE		= 0,
65 	MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES	= 1, /* always last */
66 };
67 
68 enum {
69 	MLX5_RES_SCAT_DATA32_CQE	= 0x1,
70 	MLX5_RES_SCAT_DATA64_CQE	= 0x2,
71 	MLX5_REQ_SCAT_DATA32_CQE	= 0x11,
72 	MLX5_REQ_SCAT_DATA64_CQE	= 0x22,
73 };
74 
75 enum mlx5_ib_latency_class {
76 	MLX5_IB_LATENCY_CLASS_LOW,
77 	MLX5_IB_LATENCY_CLASS_MEDIUM,
78 	MLX5_IB_LATENCY_CLASS_HIGH,
79 	MLX5_IB_LATENCY_CLASS_FAST_PATH
80 };
81 
82 enum mlx5_ib_mad_ifc_flags {
83 	MLX5_MAD_IFC_IGNORE_MKEY	= 1,
84 	MLX5_MAD_IFC_IGNORE_BKEY	= 2,
85 	MLX5_MAD_IFC_NET_VIEW		= 4,
86 };
87 
88 struct mlx5_ib_ucontext {
89 	struct ib_ucontext	ibucontext;
90 	struct list_head	db_page_list;
91 
92 	/* protect doorbell record alloc/free
93 	 */
94 	struct mutex		db_page_mutex;
95 	struct mlx5_uuar_info	uuari;
96 };
97 
to_mucontext(struct ib_ucontext * ibucontext)98 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
99 {
100 	return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
101 }
102 
103 struct mlx5_ib_pd {
104 	struct ib_pd		ibpd;
105 	u32			pdn;
106 };
107 
108 /* Use macros here so that don't have to duplicate
109  * enum ib_send_flags and enum ib_qp_type for low-level driver
110  */
111 
112 #define MLX5_IB_SEND_UMR_UNREG	IB_SEND_RESERVED_START
113 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 1)
114 #define MLX5_IB_SEND_UMR_UPDATE_MTT (IB_SEND_RESERVED_START << 2)
115 #define MLX5_IB_QPT_REG_UMR	IB_QPT_RESERVED1
116 #define MLX5_IB_WR_UMR		IB_WR_RESERVED1
117 
118 struct wr_list {
119 	u16	opcode;
120 	u16	next;
121 };
122 
123 struct mlx5_ib_wq {
124 	u64		       *wrid;
125 	u32		       *wr_data;
126 	struct wr_list	       *w_list;
127 	unsigned	       *wqe_head;
128 	u16		        unsig_count;
129 
130 	/* serialize post to the work queue
131 	 */
132 	spinlock_t		lock;
133 	int			wqe_cnt;
134 	int			max_post;
135 	int			max_gs;
136 	int			offset;
137 	int			wqe_shift;
138 	unsigned		head;
139 	unsigned		tail;
140 	u16			cur_post;
141 	u16			last_poll;
142 	void		       *qend;
143 };
144 
145 enum {
146 	MLX5_QP_USER,
147 	MLX5_QP_KERNEL,
148 	MLX5_QP_EMPTY
149 };
150 
151 /*
152  * Connect-IB can trigger up to four concurrent pagefaults
153  * per-QP.
154  */
155 enum mlx5_ib_pagefault_context {
156 	MLX5_IB_PAGEFAULT_RESPONDER_READ,
157 	MLX5_IB_PAGEFAULT_REQUESTOR_READ,
158 	MLX5_IB_PAGEFAULT_RESPONDER_WRITE,
159 	MLX5_IB_PAGEFAULT_REQUESTOR_WRITE,
160 	MLX5_IB_PAGEFAULT_CONTEXTS
161 };
162 
163 static inline enum mlx5_ib_pagefault_context
mlx5_ib_get_pagefault_context(struct mlx5_pagefault * pagefault)164 	mlx5_ib_get_pagefault_context(struct mlx5_pagefault *pagefault)
165 {
166 	return pagefault->flags & (MLX5_PFAULT_REQUESTOR | MLX5_PFAULT_WRITE);
167 }
168 
169 struct mlx5_ib_pfault {
170 	struct work_struct	work;
171 	struct mlx5_pagefault	mpfault;
172 };
173 
174 struct mlx5_ib_qp {
175 	struct ib_qp		ibqp;
176 	struct mlx5_core_qp	mqp;
177 	struct mlx5_buf		buf;
178 
179 	struct mlx5_db		db;
180 	struct mlx5_ib_wq	rq;
181 
182 	u32			doorbell_qpn;
183 	u8			sq_signal_bits;
184 	u8			fm_cache;
185 	int			sq_max_wqes_per_wr;
186 	int			sq_spare_wqes;
187 	struct mlx5_ib_wq	sq;
188 
189 	struct ib_umem	       *umem;
190 	int			buf_size;
191 
192 	/* serialize qp state modifications
193 	 */
194 	struct mutex		mutex;
195 	u16			xrcdn;
196 	u32			flags;
197 	u8			port;
198 	u8			alt_port;
199 	u8			atomic_rd_en;
200 	u8			resp_depth;
201 	u8			state;
202 	int			mlx_type;
203 	int			wq_sig;
204 	int			scat_cqe;
205 	int			max_inline_data;
206 	struct mlx5_bf	       *bf;
207 	int			has_rq;
208 
209 	/* only for user space QPs. For kernel
210 	 * we have it from the bf object
211 	 */
212 	int			uuarn;
213 
214 	int			create_type;
215 
216 	/* Store signature errors */
217 	bool			signature_en;
218 
219 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
220 	/*
221 	 * A flag that is true for QP's that are in a state that doesn't
222 	 * allow page faults, and shouldn't schedule any more faults.
223 	 */
224 	int                     disable_page_faults;
225 	/*
226 	 * The disable_page_faults_lock protects a QP's disable_page_faults
227 	 * field, allowing for a thread to atomically check whether the QP
228 	 * allows page faults, and if so schedule a page fault.
229 	 */
230 	spinlock_t              disable_page_faults_lock;
231 	struct mlx5_ib_pfault	pagefaults[MLX5_IB_PAGEFAULT_CONTEXTS];
232 #endif
233 };
234 
235 struct mlx5_ib_cq_buf {
236 	struct mlx5_buf		buf;
237 	struct ib_umem		*umem;
238 	int			cqe_size;
239 	int			nent;
240 };
241 
242 enum mlx5_ib_qp_flags {
243 	MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK     = 1 << 0,
244 	MLX5_IB_QP_SIGNATURE_HANDLING           = 1 << 1,
245 };
246 
247 struct mlx5_umr_wr {
248 	struct ib_send_wr		wr;
249 	union {
250 		u64			virt_addr;
251 		u64			offset;
252 	} target;
253 	struct ib_pd		       *pd;
254 	unsigned int			page_shift;
255 	unsigned int			npages;
256 	u32				length;
257 	int				access_flags;
258 	u32				mkey;
259 };
260 
umr_wr(struct ib_send_wr * wr)261 static inline struct mlx5_umr_wr *umr_wr(struct ib_send_wr *wr)
262 {
263 	return container_of(wr, struct mlx5_umr_wr, wr);
264 }
265 
266 struct mlx5_shared_mr_info {
267 	int mr_id;
268 	struct ib_umem		*umem;
269 };
270 
271 struct mlx5_ib_cq {
272 	struct ib_cq		ibcq;
273 	struct mlx5_core_cq	mcq;
274 	struct mlx5_ib_cq_buf	buf;
275 	struct mlx5_db		db;
276 
277 	/* serialize access to the CQ
278 	 */
279 	spinlock_t		lock;
280 
281 	/* protect resize cq
282 	 */
283 	struct mutex		resize_mutex;
284 	struct mlx5_ib_cq_buf  *resize_buf;
285 	struct ib_umem	       *resize_umem;
286 	int			cqe_size;
287 };
288 
289 struct mlx5_ib_srq {
290 	struct ib_srq		ibsrq;
291 	struct mlx5_core_srq	msrq;
292 	struct mlx5_buf		buf;
293 	struct mlx5_db		db;
294 	u64		       *wrid;
295 	/* protect SRQ hanlding
296 	 */
297 	spinlock_t		lock;
298 	int			head;
299 	int			tail;
300 	u16			wqe_ctr;
301 	struct ib_umem	       *umem;
302 	/* serialize arming a SRQ
303 	 */
304 	struct mutex		mutex;
305 	int			wq_sig;
306 };
307 
308 struct mlx5_ib_xrcd {
309 	struct ib_xrcd		ibxrcd;
310 	u32			xrcdn;
311 };
312 
313 enum mlx5_ib_mtt_access_flags {
314 	MLX5_IB_MTT_READ  = (1 << 0),
315 	MLX5_IB_MTT_WRITE = (1 << 1),
316 };
317 
318 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
319 
320 struct mlx5_ib_mr {
321 	struct ib_mr		ibmr;
322 	void			*descs;
323 	dma_addr_t		desc_map;
324 	int			ndescs;
325 	int			max_descs;
326 	int			desc_size;
327 	struct mlx5_core_mr	mmr;
328 	struct ib_umem	       *umem;
329 	struct mlx5_shared_mr_info	*smr_info;
330 	struct list_head	list;
331 	int			order;
332 	int			umred;
333 	int			npages;
334 	struct mlx5_ib_dev     *dev;
335 	struct mlx5_create_mkey_mbox_out out;
336 	struct mlx5_core_sig_ctx    *sig;
337 	int			live;
338 	void			*descs_alloc;
339 };
340 
341 struct mlx5_ib_umr_context {
342 	enum ib_wc_status	status;
343 	struct completion	done;
344 };
345 
mlx5_ib_init_umr_context(struct mlx5_ib_umr_context * context)346 static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context)
347 {
348 	context->status = -1;
349 	init_completion(&context->done);
350 }
351 
352 struct umr_common {
353 	struct ib_pd	*pd;
354 	struct ib_cq	*cq;
355 	struct ib_qp	*qp;
356 	/* control access to UMR QP
357 	 */
358 	struct semaphore	sem;
359 };
360 
361 enum {
362 	MLX5_FMR_INVALID,
363 	MLX5_FMR_VALID,
364 	MLX5_FMR_BUSY,
365 };
366 
367 struct mlx5_cache_ent {
368 	struct list_head	head;
369 	/* sync access to the cahce entry
370 	 */
371 	spinlock_t		lock;
372 
373 
374 	struct dentry	       *dir;
375 	char                    name[4];
376 	u32                     order;
377 	u32			size;
378 	u32                     cur;
379 	u32                     miss;
380 	u32			limit;
381 
382 	struct dentry          *fsize;
383 	struct dentry          *fcur;
384 	struct dentry          *fmiss;
385 	struct dentry          *flimit;
386 
387 	struct mlx5_ib_dev     *dev;
388 	struct work_struct	work;
389 	struct delayed_work	dwork;
390 	int			pending;
391 };
392 
393 struct mlx5_mr_cache {
394 	struct workqueue_struct *wq;
395 	struct mlx5_cache_ent	ent[MAX_MR_CACHE_ENTRIES];
396 	int			stopped;
397 	struct dentry		*root;
398 	unsigned long		last_add;
399 };
400 
401 struct mlx5_ib_resources {
402 	struct ib_cq	*c0;
403 	struct ib_xrcd	*x0;
404 	struct ib_xrcd	*x1;
405 	struct ib_pd	*p0;
406 	struct ib_srq	*s0;
407 	struct ib_srq	*s1;
408 };
409 
410 struct mlx5_ib_dev {
411 	struct ib_device		ib_dev;
412 	struct mlx5_core_dev		*mdev;
413 	MLX5_DECLARE_DOORBELL_LOCK(uar_lock);
414 	int				num_ports;
415 	/* serialize update of capability mask
416 	 */
417 	struct mutex			cap_mask_mutex;
418 	bool				ib_active;
419 	struct umr_common		umrc;
420 	/* sync used page count stats
421 	 */
422 	struct mlx5_ib_resources	devr;
423 	struct mlx5_mr_cache		cache;
424 	struct timer_list		delay_timer;
425 	int				fill_delay;
426 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
427 	struct ib_odp_caps	odp_caps;
428 	/*
429 	 * Sleepable RCU that prevents destruction of MRs while they are still
430 	 * being used by a page fault handler.
431 	 */
432 	struct srcu_struct      mr_srcu;
433 #endif
434 };
435 
to_mibcq(struct mlx5_core_cq * mcq)436 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
437 {
438 	return container_of(mcq, struct mlx5_ib_cq, mcq);
439 }
440 
to_mxrcd(struct ib_xrcd * ibxrcd)441 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
442 {
443 	return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
444 }
445 
to_mdev(struct ib_device * ibdev)446 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
447 {
448 	return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
449 }
450 
to_mcq(struct ib_cq * ibcq)451 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
452 {
453 	return container_of(ibcq, struct mlx5_ib_cq, ibcq);
454 }
455 
to_mibqp(struct mlx5_core_qp * mqp)456 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
457 {
458 	return container_of(mqp, struct mlx5_ib_qp, mqp);
459 }
460 
to_mibmr(struct mlx5_core_mr * mmr)461 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mr *mmr)
462 {
463 	return container_of(mmr, struct mlx5_ib_mr, mmr);
464 }
465 
to_mpd(struct ib_pd * ibpd)466 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
467 {
468 	return container_of(ibpd, struct mlx5_ib_pd, ibpd);
469 }
470 
to_msrq(struct ib_srq * ibsrq)471 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
472 {
473 	return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
474 }
475 
to_mqp(struct ib_qp * ibqp)476 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
477 {
478 	return container_of(ibqp, struct mlx5_ib_qp, ibqp);
479 }
480 
to_mibsrq(struct mlx5_core_srq * msrq)481 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
482 {
483 	return container_of(msrq, struct mlx5_ib_srq, msrq);
484 }
485 
to_mmr(struct ib_mr * ibmr)486 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
487 {
488 	return container_of(ibmr, struct mlx5_ib_mr, ibmr);
489 }
490 
491 struct mlx5_ib_ah {
492 	struct ib_ah		ibah;
493 	struct mlx5_av		av;
494 };
495 
to_mah(struct ib_ah * ibah)496 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah)
497 {
498 	return container_of(ibah, struct mlx5_ib_ah, ibah);
499 }
500 
501 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
502 			struct mlx5_db *db);
503 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
504 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
505 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
506 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
507 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey,
508 		 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
509 		 const void *in_mad, void *response_mad);
510 struct ib_ah *create_ib_ah(struct ib_ah_attr *ah_attr,
511 			   struct mlx5_ib_ah *ah);
512 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr);
513 int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr);
514 int mlx5_ib_destroy_ah(struct ib_ah *ah);
515 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd,
516 				  struct ib_srq_init_attr *init_attr,
517 				  struct ib_udata *udata);
518 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
519 		       enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
520 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
521 int mlx5_ib_destroy_srq(struct ib_srq *srq);
522 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
523 			  struct ib_recv_wr **bad_wr);
524 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
525 				struct ib_qp_init_attr *init_attr,
526 				struct ib_udata *udata);
527 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
528 		      int attr_mask, struct ib_udata *udata);
529 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
530 		     struct ib_qp_init_attr *qp_init_attr);
531 int mlx5_ib_destroy_qp(struct ib_qp *qp);
532 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
533 		      struct ib_send_wr **bad_wr);
534 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
535 		      struct ib_recv_wr **bad_wr);
536 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n);
537 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
538 			  void *buffer, u32 length);
539 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
540 				const struct ib_cq_init_attr *attr,
541 				struct ib_ucontext *context,
542 				struct ib_udata *udata);
543 int mlx5_ib_destroy_cq(struct ib_cq *cq);
544 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
545 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
546 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
547 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
548 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
549 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
550 				  u64 virt_addr, int access_flags,
551 				  struct ib_udata *udata);
552 int mlx5_ib_update_mtt(struct mlx5_ib_mr *mr, u64 start_page_index,
553 		       int npages, int zap);
554 int mlx5_ib_dereg_mr(struct ib_mr *ibmr);
555 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd,
556 			       enum ib_mr_type mr_type,
557 			       u32 max_num_sg);
558 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr,
559 		      struct scatterlist *sg,
560 		      int sg_nents);
561 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
562 			const struct ib_wc *in_wc, const struct ib_grh *in_grh,
563 			const struct ib_mad_hdr *in, size_t in_mad_size,
564 			struct ib_mad_hdr *out, size_t *out_mad_size,
565 			u16 *out_mad_pkey_index);
566 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
567 					  struct ib_ucontext *context,
568 					  struct ib_udata *udata);
569 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd);
570 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
571 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
572 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev,
573 					  struct ib_smp *out_mad);
574 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
575 					 __be64 *sys_image_guid);
576 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
577 				 u16 *max_pkeys);
578 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
579 				 u32 *vendor_id);
580 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
581 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
582 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index,
583 			    u16 *pkey);
584 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index,
585 			    union ib_gid *gid);
586 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port,
587 			    struct ib_port_attr *props);
588 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
589 		       struct ib_port_attr *props);
590 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
591 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
592 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift,
593 			int *ncont, int *order);
594 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
595 			    int page_shift, size_t offset, size_t num_pages,
596 			    __be64 *pas, int access_flags);
597 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
598 			  int page_shift, __be64 *pas, int access_flags);
599 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
600 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq);
601 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
602 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
603 int mlx5_mr_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift);
604 void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context);
605 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
606 			    struct ib_mr_status *mr_status);
607 
608 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
609 extern struct workqueue_struct *mlx5_ib_page_fault_wq;
610 
611 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev);
612 void mlx5_ib_mr_pfault_handler(struct mlx5_ib_qp *qp,
613 			       struct mlx5_ib_pfault *pfault);
614 void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp);
615 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
616 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev);
617 int __init mlx5_ib_odp_init(void);
618 void mlx5_ib_odp_cleanup(void);
619 void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp);
620 void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp);
621 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start,
622 			      unsigned long end);
623 
624 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev * dev)625 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
626 {
627 	return;
628 }
629 
mlx5_ib_odp_create_qp(struct mlx5_ib_qp * qp)630 static inline void mlx5_ib_odp_create_qp(struct mlx5_ib_qp *qp)		{}
mlx5_ib_odp_init_one(struct mlx5_ib_dev * ibdev)631 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
mlx5_ib_odp_remove_one(struct mlx5_ib_dev * ibdev)632 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev *ibdev)	{}
mlx5_ib_odp_init(void)633 static inline int mlx5_ib_odp_init(void) { return 0; }
mlx5_ib_odp_cleanup(void)634 static inline void mlx5_ib_odp_cleanup(void)				{}
mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp * qp)635 static inline void mlx5_ib_qp_disable_pagefaults(struct mlx5_ib_qp *qp) {}
mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp * qp)636 static inline void mlx5_ib_qp_enable_pagefaults(struct mlx5_ib_qp *qp)  {}
637 
638 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
639 
init_query_mad(struct ib_smp * mad)640 static inline void init_query_mad(struct ib_smp *mad)
641 {
642 	mad->base_version  = 1;
643 	mad->mgmt_class    = IB_MGMT_CLASS_SUBN_LID_ROUTED;
644 	mad->class_version = 1;
645 	mad->method	   = IB_MGMT_METHOD_GET;
646 }
647 
convert_access(int acc)648 static inline u8 convert_access(int acc)
649 {
650 	return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
651 	       (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
652 	       (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
653 	       (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
654 	       MLX5_PERM_LOCAL_READ;
655 }
656 
is_qp1(enum ib_qp_type qp_type)657 static inline int is_qp1(enum ib_qp_type qp_type)
658 {
659 	return qp_type == IB_QPT_GSI;
660 }
661 
662 #define MLX5_MAX_UMR_SHIFT 16
663 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
664 
665 #endif /* MLX5_IB_H */
666