1 /*
2 * Open Host Controller Interface (OHCI) driver for USB.
3 *
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
5 *
6 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
7 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
8 *
9 * [ Initialisation is based on Linus' ]
10 * [ uhci code and gregs ohci fragments ]
11 * [ (C) Copyright 1999 Linus Torvalds ]
12 * [ (C) Copyright 1999 Gregory P. Smith]
13 *
14 *
15 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
16 * interfaces (though some non-x86 Intel chips use it). It supports
17 * smarter hardware than UHCI. A download link for the spec available
18 * through the http://www.usb.org website.
19 *
20 * This file is licenced under the GPL.
21 */
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/pci.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/list.h>
35 #include <linux/usb.h>
36 #include <linux/usb/otg.h>
37 #include <linux/usb/hcd.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmapool.h>
40 #include <linux/workqueue.h>
41 #include <linux/debugfs.h>
42
43 #include <asm/io.h>
44 #include <asm/irq.h>
45 #include <asm/unaligned.h>
46 #include <asm/byteorder.h>
47
48
49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
51
52 /*-------------------------------------------------------------------------*/
53
54 /* For initializing controller (mask in an HCFS mode too) */
55 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
56 #define OHCI_INTR_INIT \
57 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
58 | OHCI_INTR_RD | OHCI_INTR_WDH)
59
60 #ifdef __hppa__
61 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
62 #define IR_DISABLE
63 #endif
64
65 #ifdef CONFIG_ARCH_OMAP
66 /* OMAP doesn't support IR (no SMM; not needed) */
67 #define IR_DISABLE
68 #endif
69
70 /*-------------------------------------------------------------------------*/
71
72 static const char hcd_name [] = "ohci_hcd";
73
74 #define STATECHANGE_DELAY msecs_to_jiffies(300)
75 #define IO_WATCHDOG_DELAY msecs_to_jiffies(275)
76
77 #include "ohci.h"
78 #include "pci-quirks.h"
79
80 static void ohci_dump(struct ohci_hcd *ohci);
81 static void ohci_stop(struct usb_hcd *hcd);
82 static void io_watchdog_func(unsigned long _ohci);
83
84 #include "ohci-hub.c"
85 #include "ohci-dbg.c"
86 #include "ohci-mem.c"
87 #include "ohci-q.c"
88
89
90 /*
91 * On architectures with edge-triggered interrupts we must never return
92 * IRQ_NONE.
93 */
94 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
95 #define IRQ_NOTMINE IRQ_HANDLED
96 #else
97 #define IRQ_NOTMINE IRQ_NONE
98 #endif
99
100
101 /* Some boards misreport power switching/overcurrent */
102 static bool distrust_firmware;
103 module_param (distrust_firmware, bool, 0);
104 MODULE_PARM_DESC (distrust_firmware,
105 "true to distrust firmware power/overcurrent setup");
106
107 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
108 static bool no_handshake = 0;
109 module_param (no_handshake, bool, 0);
110 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
111
112 /*-------------------------------------------------------------------------*/
113
number_of_tds(struct urb * urb)114 static int number_of_tds(struct urb *urb)
115 {
116 int len, i, num, this_sg_len;
117 struct scatterlist *sg;
118
119 len = urb->transfer_buffer_length;
120 i = urb->num_mapped_sgs;
121
122 if (len > 0 && i > 0) { /* Scatter-gather transfer */
123 num = 0;
124 sg = urb->sg;
125 for (;;) {
126 this_sg_len = min_t(int, sg_dma_len(sg), len);
127 num += DIV_ROUND_UP(this_sg_len, 4096);
128 len -= this_sg_len;
129 if (--i <= 0 || len <= 0)
130 break;
131 sg = sg_next(sg);
132 }
133
134 } else { /* Non-SG transfer */
135 /* one TD for every 4096 Bytes (could be up to 8K) */
136 num = DIV_ROUND_UP(len, 4096);
137 }
138 return num;
139 }
140
141 /*
142 * queue up an urb for anything except the root hub
143 */
ohci_urb_enqueue(struct usb_hcd * hcd,struct urb * urb,gfp_t mem_flags)144 static int ohci_urb_enqueue (
145 struct usb_hcd *hcd,
146 struct urb *urb,
147 gfp_t mem_flags
148 ) {
149 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
150 struct ed *ed;
151 urb_priv_t *urb_priv;
152 unsigned int pipe = urb->pipe;
153 int i, size = 0;
154 unsigned long flags;
155 int retval = 0;
156
157 /* every endpoint has a ed, locate and maybe (re)initialize it */
158 ed = ed_get(ohci, urb->ep, urb->dev, pipe, urb->interval);
159 if (! ed)
160 return -ENOMEM;
161
162 /* for the private part of the URB we need the number of TDs (size) */
163 switch (ed->type) {
164 case PIPE_CONTROL:
165 /* td_submit_urb() doesn't yet handle these */
166 if (urb->transfer_buffer_length > 4096)
167 return -EMSGSIZE;
168
169 /* 1 TD for setup, 1 for ACK, plus ... */
170 size = 2;
171 /* FALLTHROUGH */
172 // case PIPE_INTERRUPT:
173 // case PIPE_BULK:
174 default:
175 size += number_of_tds(urb);
176 /* maybe a zero-length packet to wrap it up */
177 if (size == 0)
178 size++;
179 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
180 && (urb->transfer_buffer_length
181 % usb_maxpacket (urb->dev, pipe,
182 usb_pipeout (pipe))) == 0)
183 size++;
184 break;
185 case PIPE_ISOCHRONOUS: /* number of packets from URB */
186 size = urb->number_of_packets;
187 break;
188 }
189
190 /* allocate the private part of the URB */
191 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
192 mem_flags);
193 if (!urb_priv)
194 return -ENOMEM;
195 INIT_LIST_HEAD (&urb_priv->pending);
196 urb_priv->length = size;
197 urb_priv->ed = ed;
198
199 /* allocate the TDs (deferring hash chain updates) */
200 for (i = 0; i < size; i++) {
201 urb_priv->td [i] = td_alloc (ohci, mem_flags);
202 if (!urb_priv->td [i]) {
203 urb_priv->length = i;
204 urb_free_priv (ohci, urb_priv);
205 return -ENOMEM;
206 }
207 }
208
209 spin_lock_irqsave (&ohci->lock, flags);
210
211 /* don't submit to a dead HC */
212 if (!HCD_HW_ACCESSIBLE(hcd)) {
213 retval = -ENODEV;
214 goto fail;
215 }
216 if (ohci->rh_state != OHCI_RH_RUNNING) {
217 retval = -ENODEV;
218 goto fail;
219 }
220 retval = usb_hcd_link_urb_to_ep(hcd, urb);
221 if (retval)
222 goto fail;
223
224 /* schedule the ed if needed */
225 if (ed->state == ED_IDLE) {
226 retval = ed_schedule (ohci, ed);
227 if (retval < 0) {
228 usb_hcd_unlink_urb_from_ep(hcd, urb);
229 goto fail;
230 }
231
232 /* Start up the I/O watchdog timer, if it's not running */
233 if (!timer_pending(&ohci->io_watchdog) &&
234 list_empty(&ohci->eds_in_use)) {
235 ohci->prev_frame_no = ohci_frame_no(ohci);
236 mod_timer(&ohci->io_watchdog,
237 jiffies + IO_WATCHDOG_DELAY);
238 }
239 list_add(&ed->in_use_list, &ohci->eds_in_use);
240
241 if (ed->type == PIPE_ISOCHRONOUS) {
242 u16 frame = ohci_frame_no(ohci);
243
244 /* delay a few frames before the first TD */
245 frame += max_t (u16, 8, ed->interval);
246 frame &= ~(ed->interval - 1);
247 frame |= ed->branch;
248 urb->start_frame = frame;
249 ed->last_iso = frame + ed->interval * (size - 1);
250 }
251 } else if (ed->type == PIPE_ISOCHRONOUS) {
252 u16 next = ohci_frame_no(ohci) + 1;
253 u16 frame = ed->last_iso + ed->interval;
254 u16 length = ed->interval * (size - 1);
255
256 /* Behind the scheduling threshold? */
257 if (unlikely(tick_before(frame, next))) {
258
259 /* URB_ISO_ASAP: Round up to the first available slot */
260 if (urb->transfer_flags & URB_ISO_ASAP) {
261 frame += (next - frame + ed->interval - 1) &
262 -ed->interval;
263
264 /*
265 * Not ASAP: Use the next slot in the stream,
266 * no matter what.
267 */
268 } else {
269 /*
270 * Some OHCI hardware doesn't handle late TDs
271 * correctly. After retiring them it proceeds
272 * to the next ED instead of the next TD.
273 * Therefore we have to omit the late TDs
274 * entirely.
275 */
276 urb_priv->td_cnt = DIV_ROUND_UP(
277 (u16) (next - frame),
278 ed->interval);
279 if (urb_priv->td_cnt >= urb_priv->length) {
280 ++urb_priv->td_cnt; /* Mark it */
281 ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
282 urb, frame, length,
283 next);
284 }
285 }
286 }
287 urb->start_frame = frame;
288 ed->last_iso = frame + length;
289 }
290
291 /* fill the TDs and link them to the ed; and
292 * enable that part of the schedule, if needed
293 * and update count of queued periodic urbs
294 */
295 urb->hcpriv = urb_priv;
296 td_submit_urb (ohci, urb);
297
298 fail:
299 if (retval)
300 urb_free_priv (ohci, urb_priv);
301 spin_unlock_irqrestore (&ohci->lock, flags);
302 return retval;
303 }
304
305 /*
306 * decouple the URB from the HC queues (TDs, urb_priv).
307 * reporting is always done
308 * asynchronously, and we might be dealing with an urb that's
309 * partially transferred, or an ED with other urbs being unlinked.
310 */
ohci_urb_dequeue(struct usb_hcd * hcd,struct urb * urb,int status)311 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
312 {
313 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
314 unsigned long flags;
315 int rc;
316 urb_priv_t *urb_priv;
317
318 spin_lock_irqsave (&ohci->lock, flags);
319 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
320 if (rc == 0) {
321
322 /* Unless an IRQ completed the unlink while it was being
323 * handed to us, flag it for unlink and giveback, and force
324 * some upcoming INTR_SF to call finish_unlinks()
325 */
326 urb_priv = urb->hcpriv;
327 if (urb_priv->ed->state == ED_OPER)
328 start_ed_unlink(ohci, urb_priv->ed);
329
330 if (ohci->rh_state != OHCI_RH_RUNNING) {
331 /* With HC dead, we can clean up right away */
332 ohci_work(ohci);
333 }
334 }
335 spin_unlock_irqrestore (&ohci->lock, flags);
336 return rc;
337 }
338
339 /*-------------------------------------------------------------------------*/
340
341 /* frees config/altsetting state for endpoints,
342 * including ED memory, dummy TD, and bulk/intr data toggle
343 */
344
345 static void
ohci_endpoint_disable(struct usb_hcd * hcd,struct usb_host_endpoint * ep)346 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
347 {
348 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
349 unsigned long flags;
350 struct ed *ed = ep->hcpriv;
351 unsigned limit = 1000;
352
353 /* ASSERT: any requests/urbs are being unlinked */
354 /* ASSERT: nobody can be submitting urbs for this any more */
355
356 if (!ed)
357 return;
358
359 rescan:
360 spin_lock_irqsave (&ohci->lock, flags);
361
362 if (ohci->rh_state != OHCI_RH_RUNNING) {
363 sanitize:
364 ed->state = ED_IDLE;
365 ohci_work(ohci);
366 }
367
368 switch (ed->state) {
369 case ED_UNLINK: /* wait for hw to finish? */
370 /* major IRQ delivery trouble loses INTR_SF too... */
371 if (limit-- == 0) {
372 ohci_warn(ohci, "ED unlink timeout\n");
373 goto sanitize;
374 }
375 spin_unlock_irqrestore (&ohci->lock, flags);
376 schedule_timeout_uninterruptible(1);
377 goto rescan;
378 case ED_IDLE: /* fully unlinked */
379 if (list_empty (&ed->td_list)) {
380 td_free (ohci, ed->dummy);
381 ed_free (ohci, ed);
382 break;
383 }
384 /* else FALL THROUGH */
385 default:
386 /* caller was supposed to have unlinked any requests;
387 * that's not our job. can't recover; must leak ed.
388 */
389 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
390 ed, ep->desc.bEndpointAddress, ed->state,
391 list_empty (&ed->td_list) ? "" : " (has tds)");
392 td_free (ohci, ed->dummy);
393 break;
394 }
395 ep->hcpriv = NULL;
396 spin_unlock_irqrestore (&ohci->lock, flags);
397 }
398
ohci_get_frame(struct usb_hcd * hcd)399 static int ohci_get_frame (struct usb_hcd *hcd)
400 {
401 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
402
403 return ohci_frame_no(ohci);
404 }
405
ohci_usb_reset(struct ohci_hcd * ohci)406 static void ohci_usb_reset (struct ohci_hcd *ohci)
407 {
408 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
409 ohci->hc_control &= OHCI_CTRL_RWC;
410 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
411 ohci->rh_state = OHCI_RH_HALTED;
412 }
413
414 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
415 * other cases where the next software may expect clean state from the
416 * "firmware". this is bus-neutral, unlike shutdown() methods.
417 */
_ohci_shutdown(struct usb_hcd * hcd)418 static void _ohci_shutdown(struct usb_hcd *hcd)
419 {
420 struct ohci_hcd *ohci;
421
422 ohci = hcd_to_ohci (hcd);
423 ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
424
425 /* Software reset, after which the controller goes into SUSPEND */
426 ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
427 ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */
428 udelay(10);
429
430 ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
431 ohci->rh_state = OHCI_RH_HALTED;
432 }
433
ohci_shutdown(struct usb_hcd * hcd)434 static void ohci_shutdown(struct usb_hcd *hcd)
435 {
436 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
437 unsigned long flags;
438
439 spin_lock_irqsave(&ohci->lock, flags);
440 _ohci_shutdown(hcd);
441 spin_unlock_irqrestore(&ohci->lock, flags);
442 }
443
444 /*-------------------------------------------------------------------------*
445 * HC functions
446 *-------------------------------------------------------------------------*/
447
448 /* init memory, and kick BIOS/SMM off */
449
ohci_init(struct ohci_hcd * ohci)450 static int ohci_init (struct ohci_hcd *ohci)
451 {
452 int ret;
453 struct usb_hcd *hcd = ohci_to_hcd(ohci);
454
455 /* Accept arbitrarily long scatter-gather lists */
456 if (!(hcd->driver->flags & HCD_LOCAL_MEM))
457 hcd->self.sg_tablesize = ~0;
458
459 if (distrust_firmware)
460 ohci->flags |= OHCI_QUIRK_HUB_POWER;
461
462 ohci->rh_state = OHCI_RH_HALTED;
463 ohci->regs = hcd->regs;
464
465 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
466 * was never needed for most non-PCI systems ... remove the code?
467 */
468
469 #ifndef IR_DISABLE
470 /* SMM owns the HC? not for long! */
471 if (!no_handshake && ohci_readl (ohci,
472 &ohci->regs->control) & OHCI_CTRL_IR) {
473 u32 temp;
474
475 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
476
477 /* this timeout is arbitrary. we make it long, so systems
478 * depending on usb keyboards may be usable even if the
479 * BIOS/SMM code seems pretty broken.
480 */
481 temp = 500; /* arbitrary: five seconds */
482
483 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
484 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
485 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
486 msleep (10);
487 if (--temp == 0) {
488 ohci_err (ohci, "USB HC takeover failed!"
489 " (BIOS/SMM bug)\n");
490 return -EBUSY;
491 }
492 }
493 ohci_usb_reset (ohci);
494 }
495 #endif
496
497 /* Disable HC interrupts */
498 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
499
500 /* flush the writes, and save key bits like RWC */
501 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
502 ohci->hc_control |= OHCI_CTRL_RWC;
503
504 /* Read the number of ports unless overridden */
505 if (ohci->num_ports == 0)
506 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
507
508 if (ohci->hcca)
509 return 0;
510
511 setup_timer(&ohci->io_watchdog, io_watchdog_func,
512 (unsigned long) ohci);
513 set_timer_slack(&ohci->io_watchdog, msecs_to_jiffies(20));
514
515 ohci->hcca = dma_alloc_coherent (hcd->self.controller,
516 sizeof(*ohci->hcca), &ohci->hcca_dma, GFP_KERNEL);
517 if (!ohci->hcca)
518 return -ENOMEM;
519
520 if ((ret = ohci_mem_init (ohci)) < 0)
521 ohci_stop (hcd);
522 else {
523 create_debug_files (ohci);
524 }
525
526 return ret;
527 }
528
529 /*-------------------------------------------------------------------------*/
530
531 /* Start an OHCI controller, set the BUS operational
532 * resets USB and controller
533 * enable interrupts
534 */
ohci_run(struct ohci_hcd * ohci)535 static int ohci_run (struct ohci_hcd *ohci)
536 {
537 u32 mask, val;
538 int first = ohci->fminterval == 0;
539 struct usb_hcd *hcd = ohci_to_hcd(ohci);
540
541 ohci->rh_state = OHCI_RH_HALTED;
542
543 /* boot firmware should have set this up (5.1.1.3.1) */
544 if (first) {
545
546 val = ohci_readl (ohci, &ohci->regs->fminterval);
547 ohci->fminterval = val & 0x3fff;
548 if (ohci->fminterval != FI)
549 ohci_dbg (ohci, "fminterval delta %d\n",
550 ohci->fminterval - FI);
551 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
552 /* also: power/overcurrent flags in roothub.a */
553 }
554
555 /* Reset USB nearly "by the book". RemoteWakeupConnected has
556 * to be checked in case boot firmware (BIOS/SMM/...) has set up
557 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
558 * If the bus glue detected wakeup capability then it should
559 * already be enabled; if so we'll just enable it again.
560 */
561 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
562 device_set_wakeup_capable(hcd->self.controller, 1);
563
564 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
565 case OHCI_USB_OPER:
566 val = 0;
567 break;
568 case OHCI_USB_SUSPEND:
569 case OHCI_USB_RESUME:
570 ohci->hc_control &= OHCI_CTRL_RWC;
571 ohci->hc_control |= OHCI_USB_RESUME;
572 val = 10 /* msec wait */;
573 break;
574 // case OHCI_USB_RESET:
575 default:
576 ohci->hc_control &= OHCI_CTRL_RWC;
577 ohci->hc_control |= OHCI_USB_RESET;
578 val = 50 /* msec wait */;
579 break;
580 }
581 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
582 // flush the writes
583 (void) ohci_readl (ohci, &ohci->regs->control);
584 msleep(val);
585
586 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
587
588 /* 2msec timelimit here means no irqs/preempt */
589 spin_lock_irq (&ohci->lock);
590
591 retry:
592 /* HC Reset requires max 10 us delay */
593 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
594 val = 30; /* ... allow extra time */
595 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
596 if (--val == 0) {
597 spin_unlock_irq (&ohci->lock);
598 ohci_err (ohci, "USB HC reset timed out!\n");
599 return -1;
600 }
601 udelay (1);
602 }
603
604 /* now we're in the SUSPEND state ... must go OPERATIONAL
605 * within 2msec else HC enters RESUME
606 *
607 * ... but some hardware won't init fmInterval "by the book"
608 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
609 * this if we write fmInterval after we're OPERATIONAL.
610 * Unclear about ALi, ServerWorks, and others ... this could
611 * easily be a longstanding bug in chip init on Linux.
612 */
613 if (ohci->flags & OHCI_QUIRK_INITRESET) {
614 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
615 // flush those writes
616 (void) ohci_readl (ohci, &ohci->regs->control);
617 }
618
619 /* Tell the controller where the control and bulk lists are
620 * The lists are empty now. */
621 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
622 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
623
624 /* a reset clears this */
625 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
626
627 periodic_reinit (ohci);
628
629 /* some OHCI implementations are finicky about how they init.
630 * bogus values here mean not even enumeration could work.
631 */
632 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
633 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
634 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
635 ohci->flags |= OHCI_QUIRK_INITRESET;
636 ohci_dbg (ohci, "enabling initreset quirk\n");
637 goto retry;
638 }
639 spin_unlock_irq (&ohci->lock);
640 ohci_err (ohci, "init err (%08x %04x)\n",
641 ohci_readl (ohci, &ohci->regs->fminterval),
642 ohci_readl (ohci, &ohci->regs->periodicstart));
643 return -EOVERFLOW;
644 }
645
646 /* use rhsc irqs after hub_wq is allocated */
647 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
648 hcd->uses_new_polling = 1;
649
650 /* start controller operations */
651 ohci->hc_control &= OHCI_CTRL_RWC;
652 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
653 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
654 ohci->rh_state = OHCI_RH_RUNNING;
655
656 /* wake on ConnectStatusChange, matching external hubs */
657 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
658
659 /* Choose the interrupts we care about now, others later on demand */
660 mask = OHCI_INTR_INIT;
661 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
662 ohci_writel (ohci, mask, &ohci->regs->intrenable);
663
664 /* handle root hub init quirks ... */
665 val = roothub_a (ohci);
666 /* Configure for per-port over-current protection by default */
667 val &= ~RH_A_NOCP;
668 val |= RH_A_OCPM;
669 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
670 /* NSC 87560 and maybe others.
671 * Ganged power switching, no over-current protection.
672 */
673 val |= RH_A_NOCP;
674 val &= ~(RH_A_POTPGT | RH_A_NPS | RH_A_PSM | RH_A_OCPM);
675 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
676 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
677 /* hub power always on; required for AMD-756 and some
678 * Mac platforms.
679 */
680 val |= RH_A_NPS;
681 }
682 ohci_writel(ohci, val, &ohci->regs->roothub.a);
683
684 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
685 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
686 &ohci->regs->roothub.b);
687 // flush those writes
688 (void) ohci_readl (ohci, &ohci->regs->control);
689
690 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
691 spin_unlock_irq (&ohci->lock);
692
693 // POTPGT delay is bits 24-31, in 2 ms units.
694 mdelay ((val >> 23) & 0x1fe);
695
696 ohci_dump(ohci);
697
698 return 0;
699 }
700
701 /* ohci_setup routine for generic controller initialization */
702
ohci_setup(struct usb_hcd * hcd)703 int ohci_setup(struct usb_hcd *hcd)
704 {
705 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
706
707 ohci_hcd_init(ohci);
708
709 return ohci_init(ohci);
710 }
711 EXPORT_SYMBOL_GPL(ohci_setup);
712
713 /* ohci_start routine for generic controller start of all OHCI bus glue */
ohci_start(struct usb_hcd * hcd)714 static int ohci_start(struct usb_hcd *hcd)
715 {
716 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
717 int ret;
718
719 ret = ohci_run(ohci);
720 if (ret < 0) {
721 ohci_err(ohci, "can't start\n");
722 ohci_stop(hcd);
723 }
724 return ret;
725 }
726
727 /*-------------------------------------------------------------------------*/
728
729 /*
730 * Some OHCI controllers are known to lose track of completed TDs. They
731 * don't add the TDs to the hardware done queue, which means we never see
732 * them as being completed.
733 *
734 * This watchdog routine checks for such problems. Without some way to
735 * tell when those TDs have completed, we would never take their EDs off
736 * the unlink list. As a result, URBs could never be dequeued and
737 * endpoints could never be released.
738 */
io_watchdog_func(unsigned long _ohci)739 static void io_watchdog_func(unsigned long _ohci)
740 {
741 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
742 bool takeback_all_pending = false;
743 u32 status;
744 u32 head;
745 struct ed *ed;
746 struct td *td, *td_start, *td_next;
747 unsigned frame_no;
748 unsigned long flags;
749
750 spin_lock_irqsave(&ohci->lock, flags);
751
752 /*
753 * One way to lose track of completed TDs is if the controller
754 * never writes back the done queue head. If it hasn't been
755 * written back since the last time this function ran and if it
756 * was non-empty at that time, something is badly wrong with the
757 * hardware.
758 */
759 status = ohci_readl(ohci, &ohci->regs->intrstatus);
760 if (!(status & OHCI_INTR_WDH) && ohci->wdh_cnt == ohci->prev_wdh_cnt) {
761 if (ohci->prev_donehead) {
762 ohci_err(ohci, "HcDoneHead not written back; disabled\n");
763 died:
764 usb_hc_died(ohci_to_hcd(ohci));
765 ohci_dump(ohci);
766 _ohci_shutdown(ohci_to_hcd(ohci));
767 goto done;
768 } else {
769 /* No write back because the done queue was empty */
770 takeback_all_pending = true;
771 }
772 }
773
774 /* Check every ED which might have pending TDs */
775 list_for_each_entry(ed, &ohci->eds_in_use, in_use_list) {
776 if (ed->pending_td) {
777 if (takeback_all_pending ||
778 OKAY_TO_TAKEBACK(ohci, ed)) {
779 unsigned tmp = hc32_to_cpu(ohci, ed->hwINFO);
780
781 ohci_dbg(ohci, "takeback pending TD for dev %d ep 0x%x\n",
782 0x007f & tmp,
783 (0x000f & (tmp >> 7)) +
784 ((tmp & ED_IN) >> 5));
785 add_to_done_list(ohci, ed->pending_td);
786 }
787 }
788
789 /* Starting from the latest pending TD, */
790 td = ed->pending_td;
791
792 /* or the last TD on the done list, */
793 if (!td) {
794 list_for_each_entry(td_next, &ed->td_list, td_list) {
795 if (!td_next->next_dl_td)
796 break;
797 td = td_next;
798 }
799 }
800
801 /* find the last TD processed by the controller. */
802 head = hc32_to_cpu(ohci, ACCESS_ONCE(ed->hwHeadP)) & TD_MASK;
803 td_start = td;
804 td_next = list_prepare_entry(td, &ed->td_list, td_list);
805 list_for_each_entry_continue(td_next, &ed->td_list, td_list) {
806 if (head == (u32) td_next->td_dma)
807 break;
808 td = td_next; /* head pointer has passed this TD */
809 }
810 if (td != td_start) {
811 /*
812 * In case a WDH cycle is in progress, we will wait
813 * for the next two cycles to complete before assuming
814 * this TD will never get on the done queue.
815 */
816 ed->takeback_wdh_cnt = ohci->wdh_cnt + 2;
817 ed->pending_td = td;
818 }
819 }
820
821 ohci_work(ohci);
822
823 if (ohci->rh_state == OHCI_RH_RUNNING) {
824
825 /*
826 * Sometimes a controller just stops working. We can tell
827 * by checking that the frame counter has advanced since
828 * the last time we ran.
829 *
830 * But be careful: Some controllers violate the spec by
831 * stopping their frame counter when no ports are active.
832 */
833 frame_no = ohci_frame_no(ohci);
834 if (frame_no == ohci->prev_frame_no) {
835 int active_cnt = 0;
836 int i;
837 unsigned tmp;
838
839 for (i = 0; i < ohci->num_ports; ++i) {
840 tmp = roothub_portstatus(ohci, i);
841 /* Enabled and not suspended? */
842 if ((tmp & RH_PS_PES) && !(tmp & RH_PS_PSS))
843 ++active_cnt;
844 }
845
846 if (active_cnt > 0) {
847 ohci_err(ohci, "frame counter not updating; disabled\n");
848 goto died;
849 }
850 }
851 if (!list_empty(&ohci->eds_in_use)) {
852 ohci->prev_frame_no = frame_no;
853 ohci->prev_wdh_cnt = ohci->wdh_cnt;
854 ohci->prev_donehead = ohci_readl(ohci,
855 &ohci->regs->donehead);
856 mod_timer(&ohci->io_watchdog,
857 jiffies + IO_WATCHDOG_DELAY);
858 }
859 }
860
861 done:
862 spin_unlock_irqrestore(&ohci->lock, flags);
863 }
864
865 /* an interrupt happens */
866
ohci_irq(struct usb_hcd * hcd)867 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
868 {
869 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
870 struct ohci_regs __iomem *regs = ohci->regs;
871 int ints;
872
873 /* Read interrupt status (and flush pending writes). We ignore the
874 * optimization of checking the LSB of hcca->done_head; it doesn't
875 * work on all systems (edge triggering for OHCI can be a factor).
876 */
877 ints = ohci_readl(ohci, ®s->intrstatus);
878
879 /* Check for an all 1's result which is a typical consequence
880 * of dead, unclocked, or unplugged (CardBus...) devices
881 */
882 if (ints == ~(u32)0) {
883 ohci->rh_state = OHCI_RH_HALTED;
884 ohci_dbg (ohci, "device removed!\n");
885 usb_hc_died(hcd);
886 return IRQ_HANDLED;
887 }
888
889 /* We only care about interrupts that are enabled */
890 ints &= ohci_readl(ohci, ®s->intrenable);
891
892 /* interrupt for some other device? */
893 if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
894 return IRQ_NOTMINE;
895
896 if (ints & OHCI_INTR_UE) {
897 // e.g. due to PCI Master/Target Abort
898 if (quirk_nec(ohci)) {
899 /* Workaround for a silicon bug in some NEC chips used
900 * in Apple's PowerBooks. Adapted from Darwin code.
901 */
902 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
903
904 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable);
905
906 schedule_work (&ohci->nec_work);
907 } else {
908 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
909 ohci->rh_state = OHCI_RH_HALTED;
910 usb_hc_died(hcd);
911 }
912
913 ohci_dump(ohci);
914 ohci_usb_reset (ohci);
915 }
916
917 if (ints & OHCI_INTR_RHSC) {
918 ohci_dbg(ohci, "rhsc\n");
919 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
920 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
921 ®s->intrstatus);
922
923 /* NOTE: Vendors didn't always make the same implementation
924 * choices for RHSC. Many followed the spec; RHSC triggers
925 * on an edge, like setting and maybe clearing a port status
926 * change bit. With others it's level-triggered, active
927 * until hub_wq clears all the port status change bits. We'll
928 * always disable it here and rely on polling until hub_wq
929 * re-enables it.
930 */
931 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable);
932 usb_hcd_poll_rh_status(hcd);
933 }
934
935 /* For connect and disconnect events, we expect the controller
936 * to turn on RHSC along with RD. But for remote wakeup events
937 * this might not happen.
938 */
939 else if (ints & OHCI_INTR_RD) {
940 ohci_dbg(ohci, "resume detect\n");
941 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus);
942 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
943 if (ohci->autostop) {
944 spin_lock (&ohci->lock);
945 ohci_rh_resume (ohci);
946 spin_unlock (&ohci->lock);
947 } else
948 usb_hcd_resume_root_hub(hcd);
949 }
950
951 spin_lock(&ohci->lock);
952 if (ints & OHCI_INTR_WDH)
953 update_done_list(ohci);
954
955 /* could track INTR_SO to reduce available PCI/... bandwidth */
956
957 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
958 * when there's still unlinking to be done (next frame).
959 */
960 ohci_work(ohci);
961 if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list
962 && ohci->rh_state == OHCI_RH_RUNNING)
963 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable);
964
965 if (ohci->rh_state == OHCI_RH_RUNNING) {
966 ohci_writel (ohci, ints, ®s->intrstatus);
967 if (ints & OHCI_INTR_WDH)
968 ++ohci->wdh_cnt;
969
970 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable);
971 // flush those writes
972 (void) ohci_readl (ohci, &ohci->regs->control);
973 }
974 spin_unlock(&ohci->lock);
975
976 return IRQ_HANDLED;
977 }
978
979 /*-------------------------------------------------------------------------*/
980
ohci_stop(struct usb_hcd * hcd)981 static void ohci_stop (struct usb_hcd *hcd)
982 {
983 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
984
985 ohci_dump(ohci);
986
987 if (quirk_nec(ohci))
988 flush_work(&ohci->nec_work);
989 del_timer_sync(&ohci->io_watchdog);
990
991 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
992 ohci_usb_reset(ohci);
993 free_irq(hcd->irq, hcd);
994 hcd->irq = 0;
995
996 if (quirk_amdiso(ohci))
997 usb_amd_dev_put();
998
999 remove_debug_files (ohci);
1000 ohci_mem_cleanup (ohci);
1001 if (ohci->hcca) {
1002 dma_free_coherent (hcd->self.controller,
1003 sizeof *ohci->hcca,
1004 ohci->hcca, ohci->hcca_dma);
1005 ohci->hcca = NULL;
1006 ohci->hcca_dma = 0;
1007 }
1008 }
1009
1010 /*-------------------------------------------------------------------------*/
1011
1012 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
1013
1014 /* must not be called from interrupt context */
ohci_restart(struct ohci_hcd * ohci)1015 int ohci_restart(struct ohci_hcd *ohci)
1016 {
1017 int temp;
1018 int i;
1019 struct urb_priv *priv;
1020
1021 ohci_init(ohci);
1022 spin_lock_irq(&ohci->lock);
1023 ohci->rh_state = OHCI_RH_HALTED;
1024
1025 /* Recycle any "live" eds/tds (and urbs). */
1026 if (!list_empty (&ohci->pending))
1027 ohci_dbg(ohci, "abort schedule...\n");
1028 list_for_each_entry (priv, &ohci->pending, pending) {
1029 struct urb *urb = priv->td[0]->urb;
1030 struct ed *ed = priv->ed;
1031
1032 switch (ed->state) {
1033 case ED_OPER:
1034 ed->state = ED_UNLINK;
1035 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
1036 ed_deschedule (ohci, ed);
1037
1038 ed->ed_next = ohci->ed_rm_list;
1039 ed->ed_prev = NULL;
1040 ohci->ed_rm_list = ed;
1041 /* FALLTHROUGH */
1042 case ED_UNLINK:
1043 break;
1044 default:
1045 ohci_dbg(ohci, "bogus ed %p state %d\n",
1046 ed, ed->state);
1047 }
1048
1049 if (!urb->unlinked)
1050 urb->unlinked = -ESHUTDOWN;
1051 }
1052 ohci_work(ohci);
1053 spin_unlock_irq(&ohci->lock);
1054
1055 /* paranoia, in case that didn't work: */
1056
1057 /* empty the interrupt branches */
1058 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
1059 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
1060
1061 /* no EDs to remove */
1062 ohci->ed_rm_list = NULL;
1063
1064 /* empty control and bulk lists */
1065 ohci->ed_controltail = NULL;
1066 ohci->ed_bulktail = NULL;
1067
1068 if ((temp = ohci_run (ohci)) < 0) {
1069 ohci_err (ohci, "can't restart, %d\n", temp);
1070 return temp;
1071 }
1072 ohci_dbg(ohci, "restart complete\n");
1073 return 0;
1074 }
1075 EXPORT_SYMBOL_GPL(ohci_restart);
1076
1077 #endif
1078
1079 #ifdef CONFIG_PM
1080
ohci_suspend(struct usb_hcd * hcd,bool do_wakeup)1081 int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1082 {
1083 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1084 unsigned long flags;
1085 int rc = 0;
1086
1087 /* Disable irq emission and mark HW unaccessible. Use
1088 * the spinlock to properly synchronize with possible pending
1089 * RH suspend or resume activity.
1090 */
1091 spin_lock_irqsave (&ohci->lock, flags);
1092 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1093 (void)ohci_readl(ohci, &ohci->regs->intrdisable);
1094
1095 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1096 spin_unlock_irqrestore (&ohci->lock, flags);
1097
1098 synchronize_irq(hcd->irq);
1099
1100 if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
1101 ohci_resume(hcd, false);
1102 rc = -EBUSY;
1103 }
1104 return rc;
1105 }
1106 EXPORT_SYMBOL_GPL(ohci_suspend);
1107
1108
ohci_resume(struct usb_hcd * hcd,bool hibernated)1109 int ohci_resume(struct usb_hcd *hcd, bool hibernated)
1110 {
1111 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
1112 int port;
1113 bool need_reinit = false;
1114
1115 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1116
1117 /* Make sure resume from hibernation re-enumerates everything */
1118 if (hibernated)
1119 ohci_usb_reset(ohci);
1120
1121 /* See if the controller is already running or has been reset */
1122 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
1123 if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
1124 need_reinit = true;
1125 } else {
1126 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
1127 case OHCI_USB_OPER:
1128 case OHCI_USB_RESET:
1129 need_reinit = true;
1130 }
1131 }
1132
1133 /* If needed, reinitialize and suspend the root hub */
1134 if (need_reinit) {
1135 spin_lock_irq(&ohci->lock);
1136 ohci_rh_resume(ohci);
1137 ohci_rh_suspend(ohci, 0);
1138 spin_unlock_irq(&ohci->lock);
1139 }
1140
1141 /* Normally just turn on port power and enable interrupts */
1142 else {
1143 ohci_dbg(ohci, "powerup ports\n");
1144 for (port = 0; port < ohci->num_ports; port++)
1145 ohci_writel(ohci, RH_PS_PPS,
1146 &ohci->regs->roothub.portstatus[port]);
1147
1148 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
1149 ohci_readl(ohci, &ohci->regs->intrenable);
1150 msleep(20);
1151 }
1152
1153 usb_hcd_resume_root_hub(hcd);
1154
1155 return 0;
1156 }
1157 EXPORT_SYMBOL_GPL(ohci_resume);
1158
1159 #endif
1160
1161 /*-------------------------------------------------------------------------*/
1162
1163 /*
1164 * Generic structure: This gets copied for platform drivers so that
1165 * individual entries can be overridden as needed.
1166 */
1167
1168 static const struct hc_driver ohci_hc_driver = {
1169 .description = hcd_name,
1170 .product_desc = "OHCI Host Controller",
1171 .hcd_priv_size = sizeof(struct ohci_hcd),
1172
1173 /*
1174 * generic hardware linkage
1175 */
1176 .irq = ohci_irq,
1177 .flags = HCD_MEMORY | HCD_USB11,
1178
1179 /*
1180 * basic lifecycle operations
1181 */
1182 .reset = ohci_setup,
1183 .start = ohci_start,
1184 .stop = ohci_stop,
1185 .shutdown = ohci_shutdown,
1186
1187 /*
1188 * managing i/o requests and associated device resources
1189 */
1190 .urb_enqueue = ohci_urb_enqueue,
1191 .urb_dequeue = ohci_urb_dequeue,
1192 .endpoint_disable = ohci_endpoint_disable,
1193
1194 /*
1195 * scheduling support
1196 */
1197 .get_frame_number = ohci_get_frame,
1198
1199 /*
1200 * root hub support
1201 */
1202 .hub_status_data = ohci_hub_status_data,
1203 .hub_control = ohci_hub_control,
1204 #ifdef CONFIG_PM
1205 .bus_suspend = ohci_bus_suspend,
1206 .bus_resume = ohci_bus_resume,
1207 #endif
1208 .start_port_reset = ohci_start_port_reset,
1209 };
1210
ohci_init_driver(struct hc_driver * drv,const struct ohci_driver_overrides * over)1211 void ohci_init_driver(struct hc_driver *drv,
1212 const struct ohci_driver_overrides *over)
1213 {
1214 /* Copy the generic table to drv and then apply the overrides */
1215 *drv = ohci_hc_driver;
1216
1217 if (over) {
1218 drv->product_desc = over->product_desc;
1219 drv->hcd_priv_size += over->extra_priv_size;
1220 if (over->reset)
1221 drv->reset = over->reset;
1222 }
1223 }
1224 EXPORT_SYMBOL_GPL(ohci_init_driver);
1225
1226 /*-------------------------------------------------------------------------*/
1227
1228 MODULE_AUTHOR (DRIVER_AUTHOR);
1229 MODULE_DESCRIPTION(DRIVER_DESC);
1230 MODULE_LICENSE ("GPL");
1231
1232 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1233 #include "ohci-sa1111.c"
1234 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1235 #endif
1236
1237 #ifdef CONFIG_USB_OHCI_HCD_DAVINCI
1238 #include "ohci-da8xx.c"
1239 #define DAVINCI_PLATFORM_DRIVER ohci_hcd_da8xx_driver
1240 #endif
1241
1242 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1243 #include "ohci-ppc-of.c"
1244 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1245 #endif
1246
1247 #ifdef CONFIG_PPC_PS3
1248 #include "ohci-ps3.c"
1249 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1250 #endif
1251
1252 #ifdef CONFIG_MFD_SM501
1253 #include "ohci-sm501.c"
1254 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1255 #endif
1256
1257 #ifdef CONFIG_MFD_TC6393XB
1258 #include "ohci-tmio.c"
1259 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1260 #endif
1261
1262 #ifdef CONFIG_MACH_JZ4740
1263 #include "ohci-jz4740.c"
1264 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1265 #endif
1266
1267 #ifdef CONFIG_TILE_USB
1268 #include "ohci-tilegx.c"
1269 #define PLATFORM_DRIVER ohci_hcd_tilegx_driver
1270 #endif
1271
ohci_hcd_mod_init(void)1272 static int __init ohci_hcd_mod_init(void)
1273 {
1274 int retval = 0;
1275
1276 if (usb_disabled())
1277 return -ENODEV;
1278
1279 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1280 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1281 sizeof (struct ed), sizeof (struct td));
1282 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1283
1284 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1285 if (!ohci_debug_root) {
1286 retval = -ENOENT;
1287 goto error_debug;
1288 }
1289
1290 #ifdef PS3_SYSTEM_BUS_DRIVER
1291 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1292 if (retval < 0)
1293 goto error_ps3;
1294 #endif
1295
1296 #ifdef PLATFORM_DRIVER
1297 retval = platform_driver_register(&PLATFORM_DRIVER);
1298 if (retval < 0)
1299 goto error_platform;
1300 #endif
1301
1302 #ifdef OF_PLATFORM_DRIVER
1303 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1304 if (retval < 0)
1305 goto error_of_platform;
1306 #endif
1307
1308 #ifdef SA1111_DRIVER
1309 retval = sa1111_driver_register(&SA1111_DRIVER);
1310 if (retval < 0)
1311 goto error_sa1111;
1312 #endif
1313
1314 #ifdef SM501_OHCI_DRIVER
1315 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1316 if (retval < 0)
1317 goto error_sm501;
1318 #endif
1319
1320 #ifdef TMIO_OHCI_DRIVER
1321 retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1322 if (retval < 0)
1323 goto error_tmio;
1324 #endif
1325
1326 #ifdef DAVINCI_PLATFORM_DRIVER
1327 retval = platform_driver_register(&DAVINCI_PLATFORM_DRIVER);
1328 if (retval < 0)
1329 goto error_davinci;
1330 #endif
1331
1332 return retval;
1333
1334 /* Error path */
1335 #ifdef DAVINCI_PLATFORM_DRIVER
1336 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1337 error_davinci:
1338 #endif
1339 #ifdef TMIO_OHCI_DRIVER
1340 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1341 error_tmio:
1342 #endif
1343 #ifdef SM501_OHCI_DRIVER
1344 platform_driver_unregister(&SM501_OHCI_DRIVER);
1345 error_sm501:
1346 #endif
1347 #ifdef SA1111_DRIVER
1348 sa1111_driver_unregister(&SA1111_DRIVER);
1349 error_sa1111:
1350 #endif
1351 #ifdef OF_PLATFORM_DRIVER
1352 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1353 error_of_platform:
1354 #endif
1355 #ifdef PLATFORM_DRIVER
1356 platform_driver_unregister(&PLATFORM_DRIVER);
1357 error_platform:
1358 #endif
1359 #ifdef PS3_SYSTEM_BUS_DRIVER
1360 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1361 error_ps3:
1362 #endif
1363 debugfs_remove(ohci_debug_root);
1364 ohci_debug_root = NULL;
1365 error_debug:
1366
1367 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1368 return retval;
1369 }
1370 module_init(ohci_hcd_mod_init);
1371
ohci_hcd_mod_exit(void)1372 static void __exit ohci_hcd_mod_exit(void)
1373 {
1374 #ifdef DAVINCI_PLATFORM_DRIVER
1375 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1376 #endif
1377 #ifdef TMIO_OHCI_DRIVER
1378 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1379 #endif
1380 #ifdef SM501_OHCI_DRIVER
1381 platform_driver_unregister(&SM501_OHCI_DRIVER);
1382 #endif
1383 #ifdef SA1111_DRIVER
1384 sa1111_driver_unregister(&SA1111_DRIVER);
1385 #endif
1386 #ifdef OF_PLATFORM_DRIVER
1387 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1388 #endif
1389 #ifdef PLATFORM_DRIVER
1390 platform_driver_unregister(&PLATFORM_DRIVER);
1391 #endif
1392 #ifdef PS3_SYSTEM_BUS_DRIVER
1393 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1394 #endif
1395 debugfs_remove(ohci_debug_root);
1396 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1397 }
1398 module_exit(ohci_hcd_mod_exit);
1399
1400