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1 /*
2  * OMAP3/4 - specific DPLL control functions
3  *
4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
5  * Copyright (C) 2009-2010 Nokia Corporation
6  *
7  * Written by Paul Walmsley
8  * Testing and integration fixes by Jouni Högander
9  *
10  * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
11  * Menon
12  *
13  * Parts of this code are based on code written by
14  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License version 2 as
18  * published by the Free Software Foundation.
19  */
20 
21 #include <linux/kernel.h>
22 #include <linux/device.h>
23 #include <linux/list.h>
24 #include <linux/errno.h>
25 #include <linux/delay.h>
26 #include <linux/clk.h>
27 #include <linux/io.h>
28 #include <linux/bitops.h>
29 #include <linux/clkdev.h>
30 #include <linux/clk/ti.h>
31 
32 #include "clock.h"
33 
34 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
35 #define DPLL_AUTOIDLE_DISABLE			0x0
36 #define DPLL_AUTOIDLE_LOW_POWER_STOP		0x1
37 
38 #define MAX_DPLL_WAIT_TRIES		1000000
39 
40 #define OMAP3XXX_EN_DPLL_LOCKED		0x7
41 
42 /* Forward declarations */
43 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
44 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
45 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
46 
47 /* Private functions */
48 
49 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
_omap3_dpll_write_clken(struct clk_hw_omap * clk,u8 clken_bits)50 static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
51 {
52 	const struct dpll_data *dd;
53 	u32 v;
54 
55 	dd = clk->dpll_data;
56 
57 	v = ti_clk_ll_ops->clk_readl(dd->control_reg);
58 	v &= ~dd->enable_mask;
59 	v |= clken_bits << __ffs(dd->enable_mask);
60 	ti_clk_ll_ops->clk_writel(v, dd->control_reg);
61 }
62 
63 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
_omap3_wait_dpll_status(struct clk_hw_omap * clk,u8 state)64 static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
65 {
66 	const struct dpll_data *dd;
67 	int i = 0;
68 	int ret = -EINVAL;
69 	const char *clk_name;
70 
71 	dd = clk->dpll_data;
72 	clk_name = clk_hw_get_name(&clk->hw);
73 
74 	state <<= __ffs(dd->idlest_mask);
75 
76 	while (((ti_clk_ll_ops->clk_readl(dd->idlest_reg) & dd->idlest_mask)
77 		!= state) && i < MAX_DPLL_WAIT_TRIES) {
78 		i++;
79 		udelay(1);
80 	}
81 
82 	if (i == MAX_DPLL_WAIT_TRIES) {
83 		pr_err("clock: %s failed transition to '%s'\n",
84 		       clk_name, (state) ? "locked" : "bypassed");
85 	} else {
86 		pr_debug("clock: %s transition to '%s' in %d loops\n",
87 			 clk_name, (state) ? "locked" : "bypassed", i);
88 
89 		ret = 0;
90 	}
91 
92 	return ret;
93 }
94 
95 /* From 3430 TRM ES2 4.7.6.2 */
_omap3_dpll_compute_freqsel(struct clk_hw_omap * clk,u8 n)96 static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
97 {
98 	unsigned long fint;
99 	u16 f = 0;
100 
101 	fint = clk_get_rate(clk->dpll_data->clk_ref) / n;
102 
103 	pr_debug("clock: fint is %lu\n", fint);
104 
105 	if (fint >= 750000 && fint <= 1000000)
106 		f = 0x3;
107 	else if (fint > 1000000 && fint <= 1250000)
108 		f = 0x4;
109 	else if (fint > 1250000 && fint <= 1500000)
110 		f = 0x5;
111 	else if (fint > 1500000 && fint <= 1750000)
112 		f = 0x6;
113 	else if (fint > 1750000 && fint <= 2100000)
114 		f = 0x7;
115 	else if (fint > 7500000 && fint <= 10000000)
116 		f = 0xB;
117 	else if (fint > 10000000 && fint <= 12500000)
118 		f = 0xC;
119 	else if (fint > 12500000 && fint <= 15000000)
120 		f = 0xD;
121 	else if (fint > 15000000 && fint <= 17500000)
122 		f = 0xE;
123 	else if (fint > 17500000 && fint <= 21000000)
124 		f = 0xF;
125 	else
126 		pr_debug("clock: unknown freqsel setting for %d\n", n);
127 
128 	return f;
129 }
130 
131 /*
132  * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
133  * @clk: pointer to a DPLL struct clk
134  *
135  * Instructs a non-CORE DPLL to lock.  Waits for the DPLL to report
136  * readiness before returning.  Will save and restore the DPLL's
137  * autoidle state across the enable, per the CDP code.  If the DPLL
138  * locked successfully, return 0; if the DPLL did not lock in the time
139  * allotted, or DPLL3 was passed in, return -EINVAL.
140  */
_omap3_noncore_dpll_lock(struct clk_hw_omap * clk)141 static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
142 {
143 	const struct dpll_data *dd;
144 	u8 ai;
145 	u8 state = 1;
146 	int r = 0;
147 
148 	pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw));
149 
150 	dd = clk->dpll_data;
151 	state <<= __ffs(dd->idlest_mask);
152 
153 	/* Check if already locked */
154 	if ((ti_clk_ll_ops->clk_readl(dd->idlest_reg) & dd->idlest_mask) ==
155 	    state)
156 		goto done;
157 
158 	ai = omap3_dpll_autoidle_read(clk);
159 
160 	if (ai)
161 		omap3_dpll_deny_idle(clk);
162 
163 	_omap3_dpll_write_clken(clk, DPLL_LOCKED);
164 
165 	r = _omap3_wait_dpll_status(clk, 1);
166 
167 	if (ai)
168 		omap3_dpll_allow_idle(clk);
169 
170 done:
171 	return r;
172 }
173 
174 /*
175  * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
176  * @clk: pointer to a DPLL struct clk
177  *
178  * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
179  * bypass mode, the DPLL's rate is set equal to its parent clock's
180  * rate.  Waits for the DPLL to report readiness before returning.
181  * Will save and restore the DPLL's autoidle state across the enable,
182  * per the CDP code.  If the DPLL entered bypass mode successfully,
183  * return 0; if the DPLL did not enter bypass in the time allotted, or
184  * DPLL3 was passed in, or the DPLL does not support low-power bypass,
185  * return -EINVAL.
186  */
_omap3_noncore_dpll_bypass(struct clk_hw_omap * clk)187 static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
188 {
189 	int r;
190 	u8 ai;
191 
192 	if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
193 		return -EINVAL;
194 
195 	pr_debug("clock: configuring DPLL %s for low-power bypass\n",
196 		 clk_hw_get_name(&clk->hw));
197 
198 	ai = omap3_dpll_autoidle_read(clk);
199 
200 	_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
201 
202 	r = _omap3_wait_dpll_status(clk, 0);
203 
204 	if (ai)
205 		omap3_dpll_allow_idle(clk);
206 
207 	return r;
208 }
209 
210 /*
211  * _omap3_noncore_dpll_stop - instruct a DPLL to stop
212  * @clk: pointer to a DPLL struct clk
213  *
214  * Instructs a non-CORE DPLL to enter low-power stop. Will save and
215  * restore the DPLL's autoidle state across the stop, per the CDP
216  * code.  If DPLL3 was passed in, or the DPLL does not support
217  * low-power stop, return -EINVAL; otherwise, return 0.
218  */
_omap3_noncore_dpll_stop(struct clk_hw_omap * clk)219 static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
220 {
221 	u8 ai;
222 
223 	if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
224 		return -EINVAL;
225 
226 	pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw));
227 
228 	ai = omap3_dpll_autoidle_read(clk);
229 
230 	_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
231 
232 	if (ai)
233 		omap3_dpll_allow_idle(clk);
234 
235 	return 0;
236 }
237 
238 /**
239  * _lookup_dco - Lookup DCO used by j-type DPLL
240  * @clk: pointer to a DPLL struct clk
241  * @dco: digital control oscillator selector
242  * @m: DPLL multiplier to set
243  * @n: DPLL divider to set
244  *
245  * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
246  *
247  * XXX This code is not needed for 3430/AM35xx; can it be optimized
248  * out in non-multi-OMAP builds for those chips?
249  */
_lookup_dco(struct clk_hw_omap * clk,u8 * dco,u16 m,u8 n)250 static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)
251 {
252 	unsigned long fint, clkinp; /* watch out for overflow */
253 
254 	clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
255 	fint = (clkinp / n) * m;
256 
257 	if (fint < 1000000000)
258 		*dco = 2;
259 	else
260 		*dco = 4;
261 }
262 
263 /**
264  * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
265  * @clk: pointer to a DPLL struct clk
266  * @sd_div: target sigma-delta divider
267  * @m: DPLL multiplier to set
268  * @n: DPLL divider to set
269  *
270  * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
271  *
272  * XXX This code is not needed for 3430/AM35xx; can it be optimized
273  * out in non-multi-OMAP builds for those chips?
274  */
_lookup_sddiv(struct clk_hw_omap * clk,u8 * sd_div,u16 m,u8 n)275 static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
276 {
277 	unsigned long clkinp, sd; /* watch out for overflow */
278 	int mod1, mod2;
279 
280 	clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw));
281 
282 	/*
283 	 * target sigma-delta to near 250MHz
284 	 * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
285 	 */
286 	clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
287 	mod1 = (clkinp * m) % (250 * n);
288 	sd = (clkinp * m) / (250 * n);
289 	mod2 = sd % 10;
290 	sd /= 10;
291 
292 	if (mod1 || mod2)
293 		sd++;
294 	*sd_div = sd;
295 }
296 
297 /*
298  * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
299  * @clk:	struct clk * of DPLL to set
300  * @freqsel:	FREQSEL value to set
301  *
302  * Program the DPLL with the last M, N values calculated, and wait for
303  * the DPLL to lock. Returns -EINVAL upon error, or 0 upon success.
304  */
omap3_noncore_dpll_program(struct clk_hw_omap * clk,u16 freqsel)305 static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
306 {
307 	struct dpll_data *dd = clk->dpll_data;
308 	u8 dco, sd_div;
309 	u32 v;
310 
311 	/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
312 	_omap3_noncore_dpll_bypass(clk);
313 
314 	/*
315 	 * Set jitter correction. Jitter correction applicable for OMAP343X
316 	 * only since freqsel field is no longer present on other devices.
317 	 */
318 	if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {
319 		v = ti_clk_ll_ops->clk_readl(dd->control_reg);
320 		v &= ~dd->freqsel_mask;
321 		v |= freqsel << __ffs(dd->freqsel_mask);
322 		ti_clk_ll_ops->clk_writel(v, dd->control_reg);
323 	}
324 
325 	/* Set DPLL multiplier, divider */
326 	v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg);
327 
328 	/* Handle Duty Cycle Correction */
329 	if (dd->dcc_mask) {
330 		if (dd->last_rounded_rate >= dd->dcc_rate)
331 			v |= dd->dcc_mask; /* Enable DCC */
332 		else
333 			v &= ~dd->dcc_mask; /* Disable DCC */
334 	}
335 
336 	v &= ~(dd->mult_mask | dd->div1_mask);
337 	v |= dd->last_rounded_m << __ffs(dd->mult_mask);
338 	v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
339 
340 	/* Configure dco and sd_div for dplls that have these fields */
341 	if (dd->dco_mask) {
342 		_lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);
343 		v &= ~(dd->dco_mask);
344 		v |= dco << __ffs(dd->dco_mask);
345 	}
346 	if (dd->sddiv_mask) {
347 		_lookup_sddiv(clk, &sd_div, dd->last_rounded_m,
348 			      dd->last_rounded_n);
349 		v &= ~(dd->sddiv_mask);
350 		v |= sd_div << __ffs(dd->sddiv_mask);
351 	}
352 
353 	ti_clk_ll_ops->clk_writel(v, dd->mult_div1_reg);
354 
355 	/* Set 4X multiplier and low-power mode */
356 	if (dd->m4xen_mask || dd->lpmode_mask) {
357 		v = ti_clk_ll_ops->clk_readl(dd->control_reg);
358 
359 		if (dd->m4xen_mask) {
360 			if (dd->last_rounded_m4xen)
361 				v |= dd->m4xen_mask;
362 			else
363 				v &= ~dd->m4xen_mask;
364 		}
365 
366 		if (dd->lpmode_mask) {
367 			if (dd->last_rounded_lpmode)
368 				v |= dd->lpmode_mask;
369 			else
370 				v &= ~dd->lpmode_mask;
371 		}
372 
373 		ti_clk_ll_ops->clk_writel(v, dd->control_reg);
374 	}
375 
376 	/* We let the clock framework set the other output dividers later */
377 
378 	/* REVISIT: Set ramp-up delay? */
379 
380 	_omap3_noncore_dpll_lock(clk);
381 
382 	return 0;
383 }
384 
385 /* Public functions */
386 
387 /**
388  * omap3_dpll_recalc - recalculate DPLL rate
389  * @clk: DPLL struct clk
390  *
391  * Recalculate and propagate the DPLL rate.
392  */
omap3_dpll_recalc(struct clk_hw * hw,unsigned long parent_rate)393 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
394 {
395 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
396 
397 	return omap2_get_dpll_rate(clk);
398 }
399 
400 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
401 
402 /**
403  * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
404  * @clk: pointer to a DPLL struct clk
405  *
406  * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
407  * The choice of modes depends on the DPLL's programmed rate: if it is
408  * the same as the DPLL's parent clock, it will enter bypass;
409  * otherwise, it will enter lock.  This code will wait for the DPLL to
410  * indicate readiness before returning, unless the DPLL takes too long
411  * to enter the target state.  Intended to be used as the struct clk's
412  * enable function.  If DPLL3 was passed in, or the DPLL does not
413  * support low-power stop, or if the DPLL took too long to enter
414  * bypass or lock, return -EINVAL; otherwise, return 0.
415  */
omap3_noncore_dpll_enable(struct clk_hw * hw)416 int omap3_noncore_dpll_enable(struct clk_hw *hw)
417 {
418 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
419 	int r;
420 	struct dpll_data *dd;
421 	struct clk_hw *parent;
422 
423 	dd = clk->dpll_data;
424 	if (!dd)
425 		return -EINVAL;
426 
427 	if (clk->clkdm) {
428 		r = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
429 		if (r) {
430 			WARN(1,
431 			     "%s: could not enable %s's clockdomain %s: %d\n",
432 			     __func__, clk_hw_get_name(hw),
433 			     clk->clkdm_name, r);
434 			return r;
435 		}
436 	}
437 
438 	parent = clk_hw_get_parent(hw);
439 
440 	if (clk_hw_get_rate(hw) ==
441 	    clk_hw_get_rate(__clk_get_hw(dd->clk_bypass))) {
442 		WARN_ON(parent != __clk_get_hw(dd->clk_bypass));
443 		r = _omap3_noncore_dpll_bypass(clk);
444 	} else {
445 		WARN_ON(parent != __clk_get_hw(dd->clk_ref));
446 		r = _omap3_noncore_dpll_lock(clk);
447 	}
448 
449 	return r;
450 }
451 
452 /**
453  * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
454  * @clk: pointer to a DPLL struct clk
455  *
456  * Instructs a non-CORE DPLL to enter low-power stop.  This function is
457  * intended for use in struct clkops.  No return value.
458  */
omap3_noncore_dpll_disable(struct clk_hw * hw)459 void omap3_noncore_dpll_disable(struct clk_hw *hw)
460 {
461 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
462 
463 	_omap3_noncore_dpll_stop(clk);
464 	if (clk->clkdm)
465 		ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
466 }
467 
468 /* Non-CORE DPLL rate set code */
469 
470 /**
471  * omap3_noncore_dpll_determine_rate - determine rate for a DPLL
472  * @hw: pointer to the clock to determine rate for
473  * @req: target rate request
474  *
475  * Determines which DPLL mode to use for reaching a desired target rate.
476  * Checks whether the DPLL shall be in bypass or locked mode, and if
477  * locked, calculates the M,N values for the DPLL via round-rate.
478  * Returns a 0 on success, negative error value in failure.
479  */
omap3_noncore_dpll_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)480 int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
481 				      struct clk_rate_request *req)
482 {
483 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
484 	struct dpll_data *dd;
485 
486 	if (!req->rate)
487 		return -EINVAL;
488 
489 	dd = clk->dpll_data;
490 	if (!dd)
491 		return -EINVAL;
492 
493 	if (clk_get_rate(dd->clk_bypass) == req->rate &&
494 	    (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
495 		req->best_parent_hw = __clk_get_hw(dd->clk_bypass);
496 	} else {
497 		req->rate = omap2_dpll_round_rate(hw, req->rate,
498 					  &req->best_parent_rate);
499 		req->best_parent_hw = __clk_get_hw(dd->clk_ref);
500 	}
501 
502 	req->best_parent_rate = req->rate;
503 
504 	return 0;
505 }
506 
507 /**
508  * omap3_noncore_dpll_set_parent - set parent for a DPLL clock
509  * @hw: pointer to the clock to set parent for
510  * @index: parent index to select
511  *
512  * Sets parent for a DPLL clock. This sets the DPLL into bypass or
513  * locked mode. Returns 0 with success, negative error value otherwise.
514  */
omap3_noncore_dpll_set_parent(struct clk_hw * hw,u8 index)515 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index)
516 {
517 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
518 	int ret;
519 
520 	if (!hw)
521 		return -EINVAL;
522 
523 	if (index)
524 		ret = _omap3_noncore_dpll_bypass(clk);
525 	else
526 		ret = _omap3_noncore_dpll_lock(clk);
527 
528 	return ret;
529 }
530 
531 /**
532  * omap3_noncore_dpll_set_rate - set rate for a DPLL clock
533  * @hw: pointer to the clock to set parent for
534  * @rate: target rate for the clock
535  * @parent_rate: rate of the parent clock
536  *
537  * Sets rate for a DPLL clock. First checks if the clock parent is
538  * reference clock (in bypass mode, the rate of the clock can't be
539  * changed) and proceeds with the rate change operation. Returns 0
540  * with success, negative error value otherwise.
541  */
omap3_noncore_dpll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)542 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
543 				unsigned long parent_rate)
544 {
545 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
546 	struct dpll_data *dd;
547 	u16 freqsel = 0;
548 	int ret;
549 
550 	if (!hw || !rate)
551 		return -EINVAL;
552 
553 	dd = clk->dpll_data;
554 	if (!dd)
555 		return -EINVAL;
556 
557 	if (clk_hw_get_parent(hw) != __clk_get_hw(dd->clk_ref))
558 		return -EINVAL;
559 
560 	if (dd->last_rounded_rate == 0)
561 		return -EINVAL;
562 
563 	/* Freqsel is available only on OMAP343X devices */
564 	if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {
565 		freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
566 		WARN_ON(!freqsel);
567 	}
568 
569 	pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__,
570 		 clk_hw_get_name(hw), rate);
571 
572 	ret = omap3_noncore_dpll_program(clk, freqsel);
573 
574 	return ret;
575 }
576 
577 /**
578  * omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock
579  * @hw: pointer to the clock to set rate and parent for
580  * @rate: target rate for the DPLL
581  * @parent_rate: clock rate of the DPLL parent
582  * @index: new parent index for the DPLL, 0 - reference, 1 - bypass
583  *
584  * Sets rate and parent for a DPLL clock. If new parent is the bypass
585  * clock, only selects the parent. Otherwise proceeds with a rate
586  * change, as this will effectively also change the parent as the
587  * DPLL is put into locked mode. Returns 0 with success, negative error
588  * value otherwise.
589  */
omap3_noncore_dpll_set_rate_and_parent(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate,u8 index)590 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
591 					   unsigned long rate,
592 					   unsigned long parent_rate,
593 					   u8 index)
594 {
595 	int ret;
596 
597 	if (!hw || !rate)
598 		return -EINVAL;
599 
600 	/*
601 	 * clk-ref at index[0], in which case we only need to set rate,
602 	 * the parent will be changed automatically with the lock sequence.
603 	 * With clk-bypass case we only need to change parent.
604 	 */
605 	if (index)
606 		ret = omap3_noncore_dpll_set_parent(hw, index);
607 	else
608 		ret = omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
609 
610 	return ret;
611 }
612 
613 /* DPLL autoidle read/set code */
614 
615 /**
616  * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
617  * @clk: struct clk * of the DPLL to read
618  *
619  * Return the DPLL's autoidle bits, shifted down to bit 0.  Returns
620  * -EINVAL if passed a null pointer or if the struct clk does not
621  * appear to refer to a DPLL.
622  */
omap3_dpll_autoidle_read(struct clk_hw_omap * clk)623 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
624 {
625 	const struct dpll_data *dd;
626 	u32 v;
627 
628 	if (!clk || !clk->dpll_data)
629 		return -EINVAL;
630 
631 	dd = clk->dpll_data;
632 
633 	if (!dd->autoidle_reg)
634 		return -EINVAL;
635 
636 	v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg);
637 	v &= dd->autoidle_mask;
638 	v >>= __ffs(dd->autoidle_mask);
639 
640 	return v;
641 }
642 
643 /**
644  * omap3_dpll_allow_idle - enable DPLL autoidle bits
645  * @clk: struct clk * of the DPLL to operate on
646  *
647  * Enable DPLL automatic idle control.  This automatic idle mode
648  * switching takes effect only when the DPLL is locked, at least on
649  * OMAP3430.  The DPLL will enter low-power stop when its downstream
650  * clocks are gated.  No return value.
651  */
omap3_dpll_allow_idle(struct clk_hw_omap * clk)652 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
653 {
654 	const struct dpll_data *dd;
655 	u32 v;
656 
657 	if (!clk || !clk->dpll_data)
658 		return;
659 
660 	dd = clk->dpll_data;
661 
662 	if (!dd->autoidle_reg)
663 		return;
664 
665 	/*
666 	 * REVISIT: CORE DPLL can optionally enter low-power bypass
667 	 * by writing 0x5 instead of 0x1.  Add some mechanism to
668 	 * optionally enter this mode.
669 	 */
670 	v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg);
671 	v &= ~dd->autoidle_mask;
672 	v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
673 	ti_clk_ll_ops->clk_writel(v, dd->autoidle_reg);
674 }
675 
676 /**
677  * omap3_dpll_deny_idle - prevent DPLL from automatically idling
678  * @clk: struct clk * of the DPLL to operate on
679  *
680  * Disable DPLL automatic idle control.  No return value.
681  */
omap3_dpll_deny_idle(struct clk_hw_omap * clk)682 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
683 {
684 	const struct dpll_data *dd;
685 	u32 v;
686 
687 	if (!clk || !clk->dpll_data)
688 		return;
689 
690 	dd = clk->dpll_data;
691 
692 	if (!dd->autoidle_reg)
693 		return;
694 
695 	v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg);
696 	v &= ~dd->autoidle_mask;
697 	v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
698 	ti_clk_ll_ops->clk_writel(v, dd->autoidle_reg);
699 }
700 
701 /* Clock control for DPLL outputs */
702 
703 /* Find the parent DPLL for the given clkoutx2 clock */
omap3_find_clkoutx2_dpll(struct clk_hw * hw)704 static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)
705 {
706 	struct clk_hw_omap *pclk = NULL;
707 
708 	/* Walk up the parents of clk, looking for a DPLL */
709 	do {
710 		do {
711 			hw = clk_hw_get_parent(hw);
712 		} while (hw && (clk_hw_get_flags(hw) & CLK_IS_BASIC));
713 		if (!hw)
714 			break;
715 		pclk = to_clk_hw_omap(hw);
716 	} while (pclk && !pclk->dpll_data);
717 
718 	/* clk does not have a DPLL as a parent?  error in the clock data */
719 	if (!pclk) {
720 		WARN_ON(1);
721 		return NULL;
722 	}
723 
724 	return pclk;
725 }
726 
727 /**
728  * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
729  * @clk: DPLL output struct clk
730  *
731  * Using parent clock DPLL data, look up DPLL state.  If locked, set our
732  * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
733  */
omap3_clkoutx2_recalc(struct clk_hw * hw,unsigned long parent_rate)734 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
735 				    unsigned long parent_rate)
736 {
737 	const struct dpll_data *dd;
738 	unsigned long rate;
739 	u32 v;
740 	struct clk_hw_omap *pclk = NULL;
741 
742 	if (!parent_rate)
743 		return 0;
744 
745 	pclk = omap3_find_clkoutx2_dpll(hw);
746 
747 	if (!pclk)
748 		return 0;
749 
750 	dd = pclk->dpll_data;
751 
752 	WARN_ON(!dd->enable_mask);
753 
754 	v = ti_clk_ll_ops->clk_readl(dd->control_reg) & dd->enable_mask;
755 	v >>= __ffs(dd->enable_mask);
756 	if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
757 		rate = parent_rate;
758 	else
759 		rate = parent_rate * 2;
760 	return rate;
761 }
762 
763 /* OMAP3/4 non-CORE DPLL clkops */
764 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
765 	.allow_idle	= omap3_dpll_allow_idle,
766 	.deny_idle	= omap3_dpll_deny_idle,
767 };
768 
769 /**
770  * omap3_dpll4_set_rate - set rate for omap3 per-dpll
771  * @hw: clock to change
772  * @rate: target rate for clock
773  * @parent_rate: rate of the parent clock
774  *
775  * Check if the current SoC supports the per-dpll reprogram operation
776  * or not, and then do the rate change if supported. Returns -EINVAL
777  * if not supported, 0 for success, and potential error codes from the
778  * clock rate change.
779  */
omap3_dpll4_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)780 int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
781 			 unsigned long parent_rate)
782 {
783 	/*
784 	 * According to the 12-5 CDP code from TI, "Limitation 2.5"
785 	 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
786 	 * on DPLL4.
787 	 */
788 	if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
789 		pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
790 		return -EINVAL;
791 	}
792 
793 	return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
794 }
795 
796 /**
797  * omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll
798  * @hw: clock to change
799  * @rate: target rate for clock
800  * @parent_rate: rate of the parent clock
801  * @index: parent index, 0 - reference clock, 1 - bypass clock
802  *
803  * Check if the current SoC support the per-dpll reprogram operation
804  * or not, and then do the rate + parent change if supported. Returns
805  * -EINVAL if not supported, 0 for success, and potential error codes
806  * from the clock rate change.
807  */
omap3_dpll4_set_rate_and_parent(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate,u8 index)808 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
809 				    unsigned long parent_rate, u8 index)
810 {
811 	if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
812 		pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
813 		return -EINVAL;
814 	}
815 
816 	return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,
817 						      index);
818 }
819 
820 /* Apply DM3730 errata sprz319 advisory 2.1. */
omap3_dpll5_apply_errata(struct clk_hw * hw,unsigned long parent_rate)821 static bool omap3_dpll5_apply_errata(struct clk_hw *hw,
822 				     unsigned long parent_rate)
823 {
824 	struct omap3_dpll5_settings {
825 		unsigned int rate, m, n;
826 	};
827 
828 	static const struct omap3_dpll5_settings precomputed[] = {
829 		/*
830 		 * From DM3730 errata advisory 2.1, table 35 and 36.
831 		 * The N value is increased by 1 compared to the tables as the
832 		 * errata lists register values while last_rounded_field is the
833 		 * real divider value.
834 		 */
835 		{ 12000000,  80,  0 + 1 },
836 		{ 13000000, 443,  5 + 1 },
837 		{ 19200000,  50,  0 + 1 },
838 		{ 26000000, 443, 11 + 1 },
839 		{ 38400000,  25,  0 + 1 }
840 	};
841 
842 	const struct omap3_dpll5_settings *d;
843 	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
844 	struct dpll_data *dd;
845 	unsigned int i;
846 
847 	for (i = 0; i < ARRAY_SIZE(precomputed); ++i) {
848 		if (parent_rate == precomputed[i].rate)
849 			break;
850 	}
851 
852 	if (i == ARRAY_SIZE(precomputed))
853 		return false;
854 
855 	d = &precomputed[i];
856 
857 	/* Update the M, N and rounded rate values and program the DPLL. */
858 	dd = clk->dpll_data;
859 	dd->last_rounded_m = d->m;
860 	dd->last_rounded_n = d->n;
861 	dd->last_rounded_rate = div_u64((u64)parent_rate * d->m, d->n);
862 	omap3_noncore_dpll_program(clk, 0);
863 
864 	return true;
865 }
866 
867 /**
868  * omap3_dpll5_set_rate - set rate for omap3 dpll5
869  * @hw: clock to change
870  * @rate: target rate for clock
871  * @parent_rate: rate of the parent clock
872  *
873  * Set rate for the DPLL5 clock. Apply the sprz319 advisory 2.1 on OMAP36xx if
874  * the DPLL is used for USB host (detected through the requested rate).
875  */
omap3_dpll5_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)876 int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
877 			 unsigned long parent_rate)
878 {
879 	if (rate == OMAP3_DPLL5_FREQ_FOR_USBHOST * 8) {
880 		if (omap3_dpll5_apply_errata(hw, parent_rate))
881 			return 0;
882 	}
883 
884 	return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
885 }
886