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1 /*
2  * OMAP2/3 System Control Module register access
3  *
4  * Copyright (C) 2007, 2012 Texas Instruments, Inc.
5  * Copyright (C) 2007 Nokia Corporation
6  *
7  * Written by Paul Walmsley
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13 #undef DEBUG
14 
15 #include <linux/kernel.h>
16 #include <linux/io.h>
17 #include <linux/of_address.h>
18 #include <linux/regmap.h>
19 #include <linux/mfd/syscon.h>
20 
21 #include "soc.h"
22 #include "iomap.h"
23 #include "common.h"
24 #include "cm-regbits-34xx.h"
25 #include "prm-regbits-34xx.h"
26 #include "prm3xxx.h"
27 #include "cm3xxx.h"
28 #include "sdrc.h"
29 #include "pm.h"
30 #include "control.h"
31 #include "clock.h"
32 
33 /* Used by omap3_ctrl_save_padconf() */
34 #define START_PADCONF_SAVE		0x2
35 #define PADCONF_SAVE_DONE		0x1
36 
37 static void __iomem *omap2_ctrl_base;
38 static s16 omap2_ctrl_offset;
39 static struct regmap *omap2_ctrl_syscon;
40 
41 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
42 struct omap3_scratchpad {
43 	u32 boot_config_ptr;
44 	u32 public_restore_ptr;
45 	u32 secure_ram_restore_ptr;
46 	u32 sdrc_module_semaphore;
47 	u32 prcm_block_offset;
48 	u32 sdrc_block_offset;
49 };
50 
51 struct omap3_scratchpad_prcm_block {
52 	u32 prm_contents[2];
53 	u32 cm_contents[11];
54 	u32 prcm_block_size;
55 };
56 
57 struct omap3_scratchpad_sdrc_block {
58 	u16 sysconfig;
59 	u16 cs_cfg;
60 	u16 sharing;
61 	u16 err_type;
62 	u32 dll_a_ctrl;
63 	u32 dll_b_ctrl;
64 	u32 power;
65 	u32 cs_0;
66 	u32 mcfg_0;
67 	u16 mr_0;
68 	u16 emr_1_0;
69 	u16 emr_2_0;
70 	u16 emr_3_0;
71 	u32 actim_ctrla_0;
72 	u32 actim_ctrlb_0;
73 	u32 rfr_ctrl_0;
74 	u32 cs_1;
75 	u32 mcfg_1;
76 	u16 mr_1;
77 	u16 emr_1_1;
78 	u16 emr_2_1;
79 	u16 emr_3_1;
80 	u32 actim_ctrla_1;
81 	u32 actim_ctrlb_1;
82 	u32 rfr_ctrl_1;
83 	u16 dcdl_1_ctrl;
84 	u16 dcdl_2_ctrl;
85 	u32 flags;
86 	u32 block_size;
87 };
88 
89 void *omap3_secure_ram_storage;
90 
91 /*
92  * This is used to store ARM registers in SDRAM before attempting
93  * an MPU OFF. The save and restore happens from the SRAM sleep code.
94  * The address is stored in scratchpad, so that it can be used
95  * during the restore path.
96  */
97 u32 omap3_arm_context[128];
98 
99 struct omap3_control_regs {
100 	u32 sysconfig;
101 	u32 devconf0;
102 	u32 mem_dftrw0;
103 	u32 mem_dftrw1;
104 	u32 msuspendmux_0;
105 	u32 msuspendmux_1;
106 	u32 msuspendmux_2;
107 	u32 msuspendmux_3;
108 	u32 msuspendmux_4;
109 	u32 msuspendmux_5;
110 	u32 sec_ctrl;
111 	u32 devconf1;
112 	u32 csirxfe;
113 	u32 iva2_bootaddr;
114 	u32 iva2_bootmod;
115 	u32 wkup_ctrl;
116 	u32 debobs_0;
117 	u32 debobs_1;
118 	u32 debobs_2;
119 	u32 debobs_3;
120 	u32 debobs_4;
121 	u32 debobs_5;
122 	u32 debobs_6;
123 	u32 debobs_7;
124 	u32 debobs_8;
125 	u32 prog_io0;
126 	u32 prog_io1;
127 	u32 dss_dpll_spreading;
128 	u32 core_dpll_spreading;
129 	u32 per_dpll_spreading;
130 	u32 usbhost_dpll_spreading;
131 	u32 pbias_lite;
132 	u32 temp_sensor;
133 	u32 sramldo4;
134 	u32 sramldo5;
135 	u32 csi;
136 	u32 padconf_sys_nirq;
137 };
138 
139 static struct omap3_control_regs control_context;
140 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
141 
omap2_set_globals_control(void __iomem * ctrl)142 void __init omap2_set_globals_control(void __iomem *ctrl)
143 {
144 	omap2_ctrl_base = ctrl;
145 }
146 
omap_ctrl_readb(u16 offset)147 u8 omap_ctrl_readb(u16 offset)
148 {
149 	u32 val;
150 	u8 byte_offset = offset & 0x3;
151 
152 	val = omap_ctrl_readl(offset);
153 
154 	return (val >> (byte_offset * 8)) & 0xff;
155 }
156 
omap_ctrl_readw(u16 offset)157 u16 omap_ctrl_readw(u16 offset)
158 {
159 	u32 val;
160 	u16 byte_offset = offset & 0x2;
161 
162 	val = omap_ctrl_readl(offset);
163 
164 	return (val >> (byte_offset * 8)) & 0xffff;
165 }
166 
omap_ctrl_readl(u16 offset)167 u32 omap_ctrl_readl(u16 offset)
168 {
169 	u32 val;
170 
171 	offset &= 0xfffc;
172 	if (!omap2_ctrl_syscon)
173 		val = readl_relaxed(omap2_ctrl_base + offset);
174 	else
175 		regmap_read(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
176 			    &val);
177 
178 	return val;
179 }
180 
omap_ctrl_writeb(u8 val,u16 offset)181 void omap_ctrl_writeb(u8 val, u16 offset)
182 {
183 	u32 tmp;
184 	u8 byte_offset = offset & 0x3;
185 
186 	tmp = omap_ctrl_readl(offset);
187 
188 	tmp &= 0xffffffff ^ (0xff << (byte_offset * 8));
189 	tmp |= val << (byte_offset * 8);
190 
191 	omap_ctrl_writel(tmp, offset);
192 }
193 
omap_ctrl_writew(u16 val,u16 offset)194 void omap_ctrl_writew(u16 val, u16 offset)
195 {
196 	u32 tmp;
197 	u8 byte_offset = offset & 0x2;
198 
199 	tmp = omap_ctrl_readl(offset);
200 
201 	tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8));
202 	tmp |= val << (byte_offset * 8);
203 
204 	omap_ctrl_writel(tmp, offset);
205 }
206 
omap_ctrl_writel(u32 val,u16 offset)207 void omap_ctrl_writel(u32 val, u16 offset)
208 {
209 	offset &= 0xfffc;
210 	if (!omap2_ctrl_syscon)
211 		writel_relaxed(val, omap2_ctrl_base + offset);
212 	else
213 		regmap_write(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
214 			     val);
215 }
216 
217 #ifdef CONFIG_ARCH_OMAP3
218 
219 /**
220  * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
221  * @bootmode: 8-bit value to pass to some boot code
222  *
223  * Set the bootmode in the scratchpad RAM.  This is used after the
224  * system restarts.  Not sure what actually uses this - it may be the
225  * bootloader, rather than the boot ROM - contrary to the preserved
226  * comment below.  No return value.
227  */
omap3_ctrl_write_boot_mode(u8 bootmode)228 void omap3_ctrl_write_boot_mode(u8 bootmode)
229 {
230 	u32 l;
231 
232 	l = ('B' << 24) | ('M' << 16) | bootmode;
233 
234 	/*
235 	 * Reserve the first word in scratchpad for communicating
236 	 * with the boot ROM. A pointer to a data structure
237 	 * describing the boot process can be stored there,
238 	 * cf. OMAP34xx TRM, Initialization / Software Booting
239 	 * Configuration.
240 	 *
241 	 * XXX This should use some omap_ctrl_writel()-type function
242 	 */
243 	writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
244 }
245 
246 #endif
247 
248 /**
249  * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
250  * @bootaddr: physical address of the boot loader
251  *
252  * Set boot address for the boot loader of a supported processor
253  * when a power ON sequence occurs.
254  */
omap_ctrl_write_dsp_boot_addr(u32 bootaddr)255 void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
256 {
257 	u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
258 		     cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
259 		     cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
260 		     soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
261 		     0;
262 
263 	if (!offset) {
264 		pr_err("%s: unsupported omap type\n", __func__);
265 		return;
266 	}
267 
268 	omap_ctrl_writel(bootaddr, offset);
269 }
270 
271 /**
272  * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
273  * @bootmode: 8-bit value to pass to some boot code
274  *
275  * Sets boot mode for the boot loader of a supported processor
276  * when a power ON sequence occurs.
277  */
omap_ctrl_write_dsp_boot_mode(u8 bootmode)278 void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
279 {
280 	u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
281 		     cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
282 		     0;
283 
284 	if (!offset) {
285 		pr_err("%s: unsupported omap type\n", __func__);
286 		return;
287 	}
288 
289 	omap_ctrl_writel(bootmode, offset);
290 }
291 
292 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
293 /*
294  * Clears the scratchpad contents in case of cold boot-
295  * called during bootup
296  */
omap3_clear_scratchpad_contents(void)297 void omap3_clear_scratchpad_contents(void)
298 {
299 	u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
300 	void __iomem *v_addr;
301 	u32 offset = 0;
302 
303 	v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
304 	if (omap3xxx_prm_clear_global_cold_reset()) {
305 		for ( ; offset <= max_offset; offset += 0x4)
306 			writel_relaxed(0x0, (v_addr + offset));
307 	}
308 }
309 
310 /* Populate the scratchpad structure with restore structure */
omap3_save_scratchpad_contents(void)311 void omap3_save_scratchpad_contents(void)
312 {
313 	void  __iomem *scratchpad_address;
314 	u32 arm_context_addr;
315 	struct omap3_scratchpad scratchpad_contents;
316 	struct omap3_scratchpad_prcm_block prcm_block_contents;
317 	struct omap3_scratchpad_sdrc_block sdrc_block_contents;
318 
319 	/*
320 	 * Populate the Scratchpad contents
321 	 *
322 	 * The "get_*restore_pointer" functions are used to provide a
323 	 * physical restore address where the ROM code jumps while waking
324 	 * up from MPU OFF/OSWR state.
325 	 * The restore pointer is stored into the scratchpad.
326 	 */
327 	scratchpad_contents.boot_config_ptr = 0x0;
328 	if (cpu_is_omap3630())
329 		scratchpad_contents.public_restore_ptr =
330 			virt_to_phys(omap3_restore_3630);
331 	else if (omap_rev() != OMAP3430_REV_ES3_0 &&
332 					omap_rev() != OMAP3430_REV_ES3_1 &&
333 					omap_rev() != OMAP3430_REV_ES3_1_2)
334 		scratchpad_contents.public_restore_ptr =
335 			virt_to_phys(omap3_restore);
336 	else
337 		scratchpad_contents.public_restore_ptr =
338 			virt_to_phys(omap3_restore_es3);
339 
340 	if (omap_type() == OMAP2_DEVICE_TYPE_GP)
341 		scratchpad_contents.secure_ram_restore_ptr = 0x0;
342 	else
343 		scratchpad_contents.secure_ram_restore_ptr =
344 			(u32) __pa(omap3_secure_ram_storage);
345 	scratchpad_contents.sdrc_module_semaphore = 0x0;
346 	scratchpad_contents.prcm_block_offset = 0x2C;
347 	scratchpad_contents.sdrc_block_offset = 0x64;
348 
349 	/* Populate the PRCM block contents */
350 	omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents);
351 	omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
352 
353 	prcm_block_contents.prcm_block_size = 0x0;
354 
355 	/* Populate the SDRC block contents */
356 	sdrc_block_contents.sysconfig =
357 			(sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
358 	sdrc_block_contents.cs_cfg =
359 			(sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
360 	sdrc_block_contents.sharing =
361 			(sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
362 	sdrc_block_contents.err_type =
363 			(sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
364 	sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
365 	sdrc_block_contents.dll_b_ctrl = 0x0;
366 	/*
367 	 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
368 	 * be programed to issue automatic self refresh on timeout
369 	 * of AUTO_CNT = 1 prior to any transition to OFF mode.
370 	 */
371 	if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
372 			&& (omap_rev() >= OMAP3430_REV_ES3_0))
373 		sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
374 				~(SDRC_POWER_AUTOCOUNT_MASK|
375 				SDRC_POWER_CLKCTRL_MASK)) |
376 				(1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
377 				SDRC_SELF_REFRESH_ON_AUTOCOUNT;
378 	else
379 		sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
380 
381 	sdrc_block_contents.cs_0 = 0x0;
382 	sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
383 	sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
384 	sdrc_block_contents.emr_1_0 = 0x0;
385 	sdrc_block_contents.emr_2_0 = 0x0;
386 	sdrc_block_contents.emr_3_0 = 0x0;
387 	sdrc_block_contents.actim_ctrla_0 =
388 			sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
389 	sdrc_block_contents.actim_ctrlb_0 =
390 			sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
391 	sdrc_block_contents.rfr_ctrl_0 =
392 			sdrc_read_reg(SDRC_RFR_CTRL_0);
393 	sdrc_block_contents.cs_1 = 0x0;
394 	sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
395 	sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
396 	sdrc_block_contents.emr_1_1 = 0x0;
397 	sdrc_block_contents.emr_2_1 = 0x0;
398 	sdrc_block_contents.emr_3_1 = 0x0;
399 	sdrc_block_contents.actim_ctrla_1 =
400 			sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
401 	sdrc_block_contents.actim_ctrlb_1 =
402 			sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
403 	sdrc_block_contents.rfr_ctrl_1 =
404 			sdrc_read_reg(SDRC_RFR_CTRL_1);
405 	sdrc_block_contents.dcdl_1_ctrl = 0x0;
406 	sdrc_block_contents.dcdl_2_ctrl = 0x0;
407 	sdrc_block_contents.flags = 0x0;
408 	sdrc_block_contents.block_size = 0x0;
409 
410 	arm_context_addr = virt_to_phys(omap3_arm_context);
411 
412 	/* Copy all the contents to the scratchpad location */
413 	scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
414 	memcpy_toio(scratchpad_address, &scratchpad_contents,
415 		 sizeof(scratchpad_contents));
416 	/* Scratchpad contents being 32 bits, a divide by 4 done here */
417 	memcpy_toio(scratchpad_address +
418 		scratchpad_contents.prcm_block_offset,
419 		&prcm_block_contents, sizeof(prcm_block_contents));
420 	memcpy_toio(scratchpad_address +
421 		scratchpad_contents.sdrc_block_offset,
422 		&sdrc_block_contents, sizeof(sdrc_block_contents));
423 	/*
424 	 * Copies the address of the location in SDRAM where ARM
425 	 * registers get saved during a MPU OFF transition.
426 	 */
427 	memcpy_toio(scratchpad_address +
428 		scratchpad_contents.sdrc_block_offset +
429 		sizeof(sdrc_block_contents), &arm_context_addr, 4);
430 }
431 
omap3_control_save_context(void)432 void omap3_control_save_context(void)
433 {
434 	control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
435 	control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
436 	control_context.mem_dftrw0 =
437 			omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
438 	control_context.mem_dftrw1 =
439 			omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
440 	control_context.msuspendmux_0 =
441 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
442 	control_context.msuspendmux_1 =
443 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
444 	control_context.msuspendmux_2 =
445 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
446 	control_context.msuspendmux_3 =
447 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
448 	control_context.msuspendmux_4 =
449 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
450 	control_context.msuspendmux_5 =
451 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
452 	control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
453 	control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
454 	control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
455 	control_context.iva2_bootaddr =
456 			omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
457 	control_context.iva2_bootmod =
458 			omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
459 	control_context.wkup_ctrl = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL);
460 	control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
461 	control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
462 	control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
463 	control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
464 	control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
465 	control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
466 	control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
467 	control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
468 	control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
469 	control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
470 	control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
471 	control_context.dss_dpll_spreading =
472 			omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
473 	control_context.core_dpll_spreading =
474 			omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
475 	control_context.per_dpll_spreading =
476 			omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
477 	control_context.usbhost_dpll_spreading =
478 		omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
479 	control_context.pbias_lite =
480 			omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
481 	control_context.temp_sensor =
482 			omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
483 	control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
484 	control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
485 	control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
486 	control_context.padconf_sys_nirq =
487 		omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
488 }
489 
omap3_control_restore_context(void)490 void omap3_control_restore_context(void)
491 {
492 	omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
493 	omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
494 	omap_ctrl_writel(control_context.mem_dftrw0,
495 					OMAP343X_CONTROL_MEM_DFTRW0);
496 	omap_ctrl_writel(control_context.mem_dftrw1,
497 					OMAP343X_CONTROL_MEM_DFTRW1);
498 	omap_ctrl_writel(control_context.msuspendmux_0,
499 					OMAP2_CONTROL_MSUSPENDMUX_0);
500 	omap_ctrl_writel(control_context.msuspendmux_1,
501 					OMAP2_CONTROL_MSUSPENDMUX_1);
502 	omap_ctrl_writel(control_context.msuspendmux_2,
503 					OMAP2_CONTROL_MSUSPENDMUX_2);
504 	omap_ctrl_writel(control_context.msuspendmux_3,
505 					OMAP2_CONTROL_MSUSPENDMUX_3);
506 	omap_ctrl_writel(control_context.msuspendmux_4,
507 					OMAP2_CONTROL_MSUSPENDMUX_4);
508 	omap_ctrl_writel(control_context.msuspendmux_5,
509 					OMAP2_CONTROL_MSUSPENDMUX_5);
510 	omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
511 	omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
512 	omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
513 	omap_ctrl_writel(control_context.iva2_bootaddr,
514 					OMAP343X_CONTROL_IVA2_BOOTADDR);
515 	omap_ctrl_writel(control_context.iva2_bootmod,
516 					OMAP343X_CONTROL_IVA2_BOOTMOD);
517 	omap_ctrl_writel(control_context.wkup_ctrl, OMAP34XX_CONTROL_WKUP_CTRL);
518 	omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
519 	omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
520 	omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
521 	omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
522 	omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
523 	omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
524 	omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
525 	omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
526 	omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
527 	omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
528 	omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
529 	omap_ctrl_writel(control_context.dss_dpll_spreading,
530 					OMAP343X_CONTROL_DSS_DPLL_SPREADING);
531 	omap_ctrl_writel(control_context.core_dpll_spreading,
532 					OMAP343X_CONTROL_CORE_DPLL_SPREADING);
533 	omap_ctrl_writel(control_context.per_dpll_spreading,
534 					OMAP343X_CONTROL_PER_DPLL_SPREADING);
535 	omap_ctrl_writel(control_context.usbhost_dpll_spreading,
536 				OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
537 	omap_ctrl_writel(control_context.pbias_lite,
538 					OMAP343X_CONTROL_PBIAS_LITE);
539 	omap_ctrl_writel(control_context.temp_sensor,
540 					OMAP343X_CONTROL_TEMP_SENSOR);
541 	omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
542 	omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
543 	omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
544 	omap_ctrl_writel(control_context.padconf_sys_nirq,
545 			 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
546 }
547 
omap3630_ctrl_disable_rta(void)548 void omap3630_ctrl_disable_rta(void)
549 {
550 	if (!cpu_is_omap3630())
551 		return;
552 	omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
553 }
554 
555 /**
556  * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
557  *
558  * Tell the SCM to start saving the padconf registers, then wait for
559  * the process to complete.  Returns 0 unconditionally, although it
560  * should also eventually be able to return -ETIMEDOUT, if the save
561  * does not complete.
562  *
563  * XXX This function is missing a timeout.  What should it be?
564  */
omap3_ctrl_save_padconf(void)565 int omap3_ctrl_save_padconf(void)
566 {
567 	u32 cpo;
568 
569 	/* Save the padconf registers */
570 	cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
571 	cpo |= START_PADCONF_SAVE;
572 	omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF);
573 
574 	/* wait for the save to complete */
575 	while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
576 		 & PADCONF_SAVE_DONE))
577 		udelay(1);
578 
579 	return 0;
580 }
581 
582 /**
583  * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle
584  *
585  * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
586  * force disable IVA2 so that it does not prevent any low-power states.
587  */
omap3_ctrl_set_iva_bootmode_idle(void)588 static void __init omap3_ctrl_set_iva_bootmode_idle(void)
589 {
590 	omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
591 			 OMAP343X_CONTROL_IVA2_BOOTMOD);
592 }
593 
594 /**
595  * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle
596  *
597  * Sets up the pads controlling the stacked modem in such way that the
598  * device can enter idle.
599  */
omap3_ctrl_setup_d2d_padconf(void)600 static void __init omap3_ctrl_setup_d2d_padconf(void)
601 {
602 	u16 mask, padconf;
603 
604 	/*
605 	 * In a stand alone OMAP3430 where there is not a stacked
606 	 * modem for the D2D Idle Ack and D2D MStandby must be pulled
607 	 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
608 	 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up.
609 	 */
610 	mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
611 	padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
612 	padconf |= mask;
613 	omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
614 
615 	padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
616 	padconf |= mask;
617 	omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
618 }
619 
620 /**
621  * omap3_ctrl_init - does static initializations for control module
622  *
623  * Initializes system control module. This sets up the sysconfig autoidle,
624  * and sets up modem and iva2 so that they can be idled properly.
625  */
omap3_ctrl_init(void)626 void __init omap3_ctrl_init(void)
627 {
628 	omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
629 
630 	omap3_ctrl_set_iva_bootmode_idle();
631 
632 	omap3_ctrl_setup_d2d_padconf();
633 }
634 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
635 
636 struct control_init_data {
637 	int index;
638 	s16 offset;
639 };
640 
641 static struct control_init_data ctrl_data = {
642 	.index = TI_CLKM_CTRL,
643 };
644 
645 static const struct control_init_data omap2_ctrl_data = {
646 	.index = TI_CLKM_CTRL,
647 	.offset = -OMAP2_CONTROL_GENERAL,
648 };
649 
650 static const struct of_device_id omap_scrm_dt_match_table[] = {
651 	{ .compatible = "ti,am3-scm", .data = &ctrl_data },
652 	{ .compatible = "ti,am4-scm", .data = &ctrl_data },
653 	{ .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data },
654 	{ .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data },
655 	{ .compatible = "ti,dm814-scm", .data = &ctrl_data },
656 	{ .compatible = "ti,dm816-scrm", .data = &ctrl_data },
657 	{ .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
658 	{ .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
659 	{ .compatible = "ti,dra7-scm-core", .data = &ctrl_data },
660 	{ }
661 };
662 
663 /**
664  * omap2_control_base_init - initialize iomappings for the control driver
665  *
666  * Detects and initializes the iomappings for the control driver, based
667  * on the DT data. Returns 0 in success, negative error value
668  * otherwise.
669  */
omap2_control_base_init(void)670 int __init omap2_control_base_init(void)
671 {
672 	struct device_node *np;
673 	const struct of_device_id *match;
674 	struct control_init_data *data;
675 
676 	for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
677 		data = (struct control_init_data *)match->data;
678 
679 		omap2_ctrl_base = of_iomap(np, 0);
680 		if (!omap2_ctrl_base)
681 			return -ENOMEM;
682 
683 		omap2_ctrl_offset = data->offset;
684 	}
685 
686 	return 0;
687 }
688 
689 /**
690  * omap_control_init - low level init for the control driver
691  *
692  * Initializes the low level clock infrastructure for control driver.
693  * Returns 0 in success, negative error value in failure.
694  */
omap_control_init(void)695 int __init omap_control_init(void)
696 {
697 	struct device_node *np, *scm_conf;
698 	const struct of_device_id *match;
699 	const struct omap_prcm_init_data *data;
700 	int ret;
701 	struct regmap *syscon;
702 
703 	for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
704 		data = match->data;
705 
706 		/*
707 		 * Check if we have scm_conf node, if yes, use this to
708 		 * access clock registers.
709 		 */
710 		scm_conf = of_get_child_by_name(np, "scm_conf");
711 
712 		if (scm_conf) {
713 			syscon = syscon_node_to_regmap(scm_conf);
714 
715 			if (IS_ERR(syscon))
716 				return PTR_ERR(syscon);
717 
718 			omap2_ctrl_syscon = syscon;
719 
720 			if (of_get_child_by_name(scm_conf, "clocks")) {
721 				ret = omap2_clk_provider_init(scm_conf,
722 							      data->index,
723 							      syscon, NULL);
724 				if (ret)
725 					return ret;
726 			}
727 
728 			iounmap(omap2_ctrl_base);
729 			omap2_ctrl_base = NULL;
730 		} else {
731 			/* No scm_conf found, direct access */
732 			ret = omap2_clk_provider_init(np, data->index, NULL,
733 						      omap2_ctrl_base);
734 			if (ret)
735 				return ret;
736 		}
737 	}
738 
739 	return 0;
740 }
741 
742 /**
743  * omap3_control_legacy_iomap_init - legacy iomap init for clock providers
744  *
745  * Legacy iomap init for clock provider. Needed only by legacy boot mode,
746  * where the base addresses are not parsed from DT, but still required
747  * by the clock driver to be setup properly.
748  */
omap3_control_legacy_iomap_init(void)749 void __init omap3_control_legacy_iomap_init(void)
750 {
751 	omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base);
752 }
753