1 /*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
12 *
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
24
25 #include <asm/tlb.h>
26 #include <asm/mach/map.h>
27
28 #include <linux/omap-dma.h>
29
30 #include "omap_hwmod.h"
31 #include "soc.h"
32 #include "iomap.h"
33 #include "voltage.h"
34 #include "powerdomain.h"
35 #include "clockdomain.h"
36 #include "common.h"
37 #include "clock.h"
38 #include "clock2xxx.h"
39 #include "clock3xxx.h"
40 #include "omap-pm.h"
41 #include "sdrc.h"
42 #include "control.h"
43 #include "serial.h"
44 #include "sram.h"
45 #include "cm2xxx.h"
46 #include "cm3xxx.h"
47 #include "cm33xx.h"
48 #include "cm44xx.h"
49 #include "prm.h"
50 #include "cm.h"
51 #include "prcm_mpu44xx.h"
52 #include "prminst44xx.h"
53 #include "prm2xxx.h"
54 #include "prm3xxx.h"
55 #include "prm33xx.h"
56 #include "prm44xx.h"
57 #include "opp2xxx.h"
58
59 /*
60 * omap_clk_soc_init: points to a function that does the SoC-specific
61 * clock initializations
62 */
63 static int (*omap_clk_soc_init)(void);
64
65 /*
66 * The machine specific code may provide the extra mapping besides the
67 * default mapping provided here.
68 */
69
70 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
71 static struct map_desc omap24xx_io_desc[] __initdata = {
72 {
73 .virtual = L3_24XX_VIRT,
74 .pfn = __phys_to_pfn(L3_24XX_PHYS),
75 .length = L3_24XX_SIZE,
76 .type = MT_DEVICE
77 },
78 {
79 .virtual = L4_24XX_VIRT,
80 .pfn = __phys_to_pfn(L4_24XX_PHYS),
81 .length = L4_24XX_SIZE,
82 .type = MT_DEVICE
83 },
84 };
85
86 #ifdef CONFIG_SOC_OMAP2420
87 static struct map_desc omap242x_io_desc[] __initdata = {
88 {
89 .virtual = DSP_MEM_2420_VIRT,
90 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
91 .length = DSP_MEM_2420_SIZE,
92 .type = MT_DEVICE
93 },
94 {
95 .virtual = DSP_IPI_2420_VIRT,
96 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
97 .length = DSP_IPI_2420_SIZE,
98 .type = MT_DEVICE
99 },
100 {
101 .virtual = DSP_MMU_2420_VIRT,
102 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
103 .length = DSP_MMU_2420_SIZE,
104 .type = MT_DEVICE
105 },
106 };
107
108 #endif
109
110 #ifdef CONFIG_SOC_OMAP2430
111 static struct map_desc omap243x_io_desc[] __initdata = {
112 {
113 .virtual = L4_WK_243X_VIRT,
114 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
115 .length = L4_WK_243X_SIZE,
116 .type = MT_DEVICE
117 },
118 {
119 .virtual = OMAP243X_GPMC_VIRT,
120 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
121 .length = OMAP243X_GPMC_SIZE,
122 .type = MT_DEVICE
123 },
124 {
125 .virtual = OMAP243X_SDRC_VIRT,
126 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
127 .length = OMAP243X_SDRC_SIZE,
128 .type = MT_DEVICE
129 },
130 {
131 .virtual = OMAP243X_SMS_VIRT,
132 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
133 .length = OMAP243X_SMS_SIZE,
134 .type = MT_DEVICE
135 },
136 };
137 #endif
138 #endif
139
140 #ifdef CONFIG_ARCH_OMAP3
141 static struct map_desc omap34xx_io_desc[] __initdata = {
142 {
143 .virtual = L3_34XX_VIRT,
144 .pfn = __phys_to_pfn(L3_34XX_PHYS),
145 .length = L3_34XX_SIZE,
146 .type = MT_DEVICE
147 },
148 {
149 .virtual = L4_34XX_VIRT,
150 .pfn = __phys_to_pfn(L4_34XX_PHYS),
151 .length = L4_34XX_SIZE,
152 .type = MT_DEVICE
153 },
154 {
155 .virtual = OMAP34XX_GPMC_VIRT,
156 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
157 .length = OMAP34XX_GPMC_SIZE,
158 .type = MT_DEVICE
159 },
160 {
161 .virtual = OMAP343X_SMS_VIRT,
162 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
163 .length = OMAP343X_SMS_SIZE,
164 .type = MT_DEVICE
165 },
166 {
167 .virtual = OMAP343X_SDRC_VIRT,
168 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
169 .length = OMAP343X_SDRC_SIZE,
170 .type = MT_DEVICE
171 },
172 {
173 .virtual = L4_PER_34XX_VIRT,
174 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
175 .length = L4_PER_34XX_SIZE,
176 .type = MT_DEVICE
177 },
178 {
179 .virtual = L4_EMU_34XX_VIRT,
180 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
181 .length = L4_EMU_34XX_SIZE,
182 .type = MT_DEVICE
183 },
184 };
185 #endif
186
187 #ifdef CONFIG_SOC_TI81XX
188 static struct map_desc omapti81xx_io_desc[] __initdata = {
189 {
190 .virtual = L4_34XX_VIRT,
191 .pfn = __phys_to_pfn(L4_34XX_PHYS),
192 .length = L4_34XX_SIZE,
193 .type = MT_DEVICE
194 }
195 };
196 #endif
197
198 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
199 static struct map_desc omapam33xx_io_desc[] __initdata = {
200 {
201 .virtual = L4_34XX_VIRT,
202 .pfn = __phys_to_pfn(L4_34XX_PHYS),
203 .length = L4_34XX_SIZE,
204 .type = MT_DEVICE
205 },
206 {
207 .virtual = L4_WK_AM33XX_VIRT,
208 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
209 .length = L4_WK_AM33XX_SIZE,
210 .type = MT_DEVICE
211 }
212 };
213 #endif
214
215 #ifdef CONFIG_ARCH_OMAP4
216 static struct map_desc omap44xx_io_desc[] __initdata = {
217 {
218 .virtual = L3_44XX_VIRT,
219 .pfn = __phys_to_pfn(L3_44XX_PHYS),
220 .length = L3_44XX_SIZE,
221 .type = MT_DEVICE,
222 },
223 {
224 .virtual = L4_44XX_VIRT,
225 .pfn = __phys_to_pfn(L4_44XX_PHYS),
226 .length = L4_44XX_SIZE,
227 .type = MT_DEVICE,
228 },
229 {
230 .virtual = L4_PER_44XX_VIRT,
231 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
232 .length = L4_PER_44XX_SIZE,
233 .type = MT_DEVICE,
234 },
235 };
236 #endif
237
238 #ifdef CONFIG_SOC_OMAP5
239 static struct map_desc omap54xx_io_desc[] __initdata = {
240 {
241 .virtual = L3_54XX_VIRT,
242 .pfn = __phys_to_pfn(L3_54XX_PHYS),
243 .length = L3_54XX_SIZE,
244 .type = MT_DEVICE,
245 },
246 {
247 .virtual = L4_54XX_VIRT,
248 .pfn = __phys_to_pfn(L4_54XX_PHYS),
249 .length = L4_54XX_SIZE,
250 .type = MT_DEVICE,
251 },
252 {
253 .virtual = L4_WK_54XX_VIRT,
254 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
255 .length = L4_WK_54XX_SIZE,
256 .type = MT_DEVICE,
257 },
258 {
259 .virtual = L4_PER_54XX_VIRT,
260 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
261 .length = L4_PER_54XX_SIZE,
262 .type = MT_DEVICE,
263 },
264 };
265 #endif
266
267 #ifdef CONFIG_SOC_DRA7XX
268 static struct map_desc dra7xx_io_desc[] __initdata = {
269 {
270 .virtual = L4_CFG_MPU_DRA7XX_VIRT,
271 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
272 .length = L4_CFG_MPU_DRA7XX_SIZE,
273 .type = MT_DEVICE,
274 },
275 {
276 .virtual = L3_MAIN_SN_DRA7XX_VIRT,
277 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
278 .length = L3_MAIN_SN_DRA7XX_SIZE,
279 .type = MT_DEVICE,
280 },
281 {
282 .virtual = L4_PER1_DRA7XX_VIRT,
283 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
284 .length = L4_PER1_DRA7XX_SIZE,
285 .type = MT_DEVICE,
286 },
287 {
288 .virtual = L4_PER2_DRA7XX_VIRT,
289 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
290 .length = L4_PER2_DRA7XX_SIZE,
291 .type = MT_DEVICE,
292 },
293 {
294 .virtual = L4_PER3_DRA7XX_VIRT,
295 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
296 .length = L4_PER3_DRA7XX_SIZE,
297 .type = MT_DEVICE,
298 },
299 {
300 .virtual = L4_CFG_DRA7XX_VIRT,
301 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
302 .length = L4_CFG_DRA7XX_SIZE,
303 .type = MT_DEVICE,
304 },
305 {
306 .virtual = L4_WKUP_DRA7XX_VIRT,
307 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
308 .length = L4_WKUP_DRA7XX_SIZE,
309 .type = MT_DEVICE,
310 },
311 };
312 #endif
313
314 #ifdef CONFIG_SOC_OMAP2420
omap242x_map_io(void)315 void __init omap242x_map_io(void)
316 {
317 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
318 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
319 }
320 #endif
321
322 #ifdef CONFIG_SOC_OMAP2430
omap243x_map_io(void)323 void __init omap243x_map_io(void)
324 {
325 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
326 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
327 }
328 #endif
329
330 #ifdef CONFIG_ARCH_OMAP3
omap3_map_io(void)331 void __init omap3_map_io(void)
332 {
333 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
334 }
335 #endif
336
337 #ifdef CONFIG_SOC_TI81XX
ti81xx_map_io(void)338 void __init ti81xx_map_io(void)
339 {
340 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
341 }
342 #endif
343
344 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
am33xx_map_io(void)345 void __init am33xx_map_io(void)
346 {
347 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
348 }
349 #endif
350
351 #ifdef CONFIG_ARCH_OMAP4
omap4_map_io(void)352 void __init omap4_map_io(void)
353 {
354 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
355 omap_barriers_init();
356 }
357 #endif
358
359 #ifdef CONFIG_SOC_OMAP5
omap5_map_io(void)360 void __init omap5_map_io(void)
361 {
362 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
363 omap_barriers_init();
364 }
365 #endif
366
367 #ifdef CONFIG_SOC_DRA7XX
dra7xx_map_io(void)368 void __init dra7xx_map_io(void)
369 {
370 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
371 omap_barriers_init();
372 }
373 #endif
374 /*
375 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
376 *
377 * Sets the CORE DPLL3 M2 divider to the same value that it's at
378 * currently. This has the effect of setting the SDRC SDRAM AC timing
379 * registers to the values currently defined by the kernel. Currently
380 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
381 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
382 * or passes along the return value of clk_set_rate().
383 */
_omap2_init_reprogram_sdrc(void)384 static int __init _omap2_init_reprogram_sdrc(void)
385 {
386 struct clk *dpll3_m2_ck;
387 int v = -EINVAL;
388 long rate;
389
390 if (!cpu_is_omap34xx())
391 return 0;
392
393 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
394 if (IS_ERR(dpll3_m2_ck))
395 return -EINVAL;
396
397 rate = clk_get_rate(dpll3_m2_ck);
398 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
399 v = clk_set_rate(dpll3_m2_ck, rate);
400 if (v)
401 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
402
403 clk_put(dpll3_m2_ck);
404
405 return v;
406 }
407
_set_hwmod_postsetup_state(struct omap_hwmod * oh,void * data)408 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
409 {
410 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
411 }
412
omap_hwmod_init_postsetup(void)413 static void __init omap_hwmod_init_postsetup(void)
414 {
415 u8 postsetup_state;
416
417 /* Set the default postsetup state for all hwmods */
418 #ifdef CONFIG_PM
419 postsetup_state = _HWMOD_STATE_IDLE;
420 #else
421 postsetup_state = _HWMOD_STATE_ENABLED;
422 #endif
423 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
424
425 omap_pm_if_early_init();
426 }
427
omap_common_late_init(void)428 static void __init __maybe_unused omap_common_late_init(void)
429 {
430 omap_mux_late_init();
431 omap2_common_pm_late_init();
432 omap_soc_device_init();
433 }
434
435 #ifdef CONFIG_SOC_OMAP2420
omap2420_init_early(void)436 void __init omap2420_init_early(void)
437 {
438 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
439 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
440 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
441 omap2_control_base_init();
442 omap2xxx_check_revision();
443 omap2_prcm_base_init();
444 omap2xxx_voltagedomains_init();
445 omap242x_powerdomains_init();
446 omap242x_clockdomains_init();
447 omap2420_hwmod_init();
448 omap_hwmod_init_postsetup();
449 omap_clk_soc_init = omap2420_dt_clk_init;
450 rate_table = omap2420_rate_table;
451 }
452
omap2420_init_late(void)453 void __init omap2420_init_late(void)
454 {
455 omap_common_late_init();
456 omap2_pm_init();
457 omap2_clk_enable_autoidle_all();
458 }
459 #endif
460
461 #ifdef CONFIG_SOC_OMAP2430
omap2430_init_early(void)462 void __init omap2430_init_early(void)
463 {
464 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
465 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
466 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
467 omap2_control_base_init();
468 omap2xxx_check_revision();
469 omap2_prcm_base_init();
470 omap2xxx_voltagedomains_init();
471 omap243x_powerdomains_init();
472 omap243x_clockdomains_init();
473 omap2430_hwmod_init();
474 omap_hwmod_init_postsetup();
475 omap_clk_soc_init = omap2430_dt_clk_init;
476 rate_table = omap2430_rate_table;
477 }
478
omap2430_init_late(void)479 void __init omap2430_init_late(void)
480 {
481 omap_common_late_init();
482 omap2_pm_init();
483 omap2_clk_enable_autoidle_all();
484 }
485 #endif
486
487 /*
488 * Currently only board-omap3beagle.c should call this because of the
489 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
490 */
491 #ifdef CONFIG_ARCH_OMAP3
omap3_init_early(void)492 void __init omap3_init_early(void)
493 {
494 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
495 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
496 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
497 /* XXX: remove these once OMAP3 is DT only */
498 if (!of_have_populated_dt()) {
499 omap2_set_globals_control(
500 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
501 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
502 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
503 NULL);
504 }
505 omap2_control_base_init();
506 omap3xxx_check_revision();
507 omap3xxx_check_features();
508 omap2_prcm_base_init();
509 /* XXX: remove these once OMAP3 is DT only */
510 if (!of_have_populated_dt()) {
511 omap3xxx_prm_init(NULL);
512 omap3xxx_cm_init(NULL);
513 }
514 omap3xxx_voltagedomains_init();
515 omap3xxx_powerdomains_init();
516 omap3xxx_clockdomains_init();
517 omap3xxx_hwmod_init();
518 omap_hwmod_init_postsetup();
519 if (!of_have_populated_dt()) {
520 omap3_control_legacy_iomap_init();
521 if (soc_is_am35xx())
522 omap_clk_soc_init = am35xx_clk_legacy_init;
523 else if (cpu_is_omap3630())
524 omap_clk_soc_init = omap36xx_clk_legacy_init;
525 else if (omap_rev() == OMAP3430_REV_ES1_0)
526 omap_clk_soc_init = omap3430es1_clk_legacy_init;
527 else
528 omap_clk_soc_init = omap3430_clk_legacy_init;
529 }
530 }
531
omap3430_init_early(void)532 void __init omap3430_init_early(void)
533 {
534 omap3_init_early();
535 if (of_have_populated_dt())
536 omap_clk_soc_init = omap3430_dt_clk_init;
537 }
538
omap35xx_init_early(void)539 void __init omap35xx_init_early(void)
540 {
541 omap3_init_early();
542 if (of_have_populated_dt())
543 omap_clk_soc_init = omap3430_dt_clk_init;
544 }
545
omap3630_init_early(void)546 void __init omap3630_init_early(void)
547 {
548 omap3_init_early();
549 if (of_have_populated_dt())
550 omap_clk_soc_init = omap3630_dt_clk_init;
551 }
552
am35xx_init_early(void)553 void __init am35xx_init_early(void)
554 {
555 omap3_init_early();
556 if (of_have_populated_dt())
557 omap_clk_soc_init = am35xx_dt_clk_init;
558 }
559
omap3_init_late(void)560 void __init omap3_init_late(void)
561 {
562 omap_common_late_init();
563 omap3_pm_init();
564 omap2_clk_enable_autoidle_all();
565 }
566
omap3430_init_late(void)567 void __init omap3430_init_late(void)
568 {
569 omap_common_late_init();
570 omap3_pm_init();
571 omap2_clk_enable_autoidle_all();
572 }
573
omap35xx_init_late(void)574 void __init omap35xx_init_late(void)
575 {
576 omap_common_late_init();
577 omap3_pm_init();
578 omap2_clk_enable_autoidle_all();
579 }
580
omap3630_init_late(void)581 void __init omap3630_init_late(void)
582 {
583 omap_common_late_init();
584 omap3_pm_init();
585 omap2_clk_enable_autoidle_all();
586 }
587
am35xx_init_late(void)588 void __init am35xx_init_late(void)
589 {
590 omap_common_late_init();
591 omap3_pm_init();
592 omap2_clk_enable_autoidle_all();
593 }
594
ti81xx_init_late(void)595 void __init ti81xx_init_late(void)
596 {
597 omap_common_late_init();
598 omap2_clk_enable_autoidle_all();
599 }
600 #endif
601
602 #ifdef CONFIG_SOC_TI81XX
ti814x_init_early(void)603 void __init ti814x_init_early(void)
604 {
605 omap2_set_globals_tap(TI814X_CLASS,
606 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
607 omap2_control_base_init();
608 omap3xxx_check_revision();
609 ti81xx_check_features();
610 omap2_prcm_base_init();
611 omap3xxx_voltagedomains_init();
612 omap3xxx_powerdomains_init();
613 ti814x_clockdomains_init();
614 dm814x_hwmod_init();
615 omap_hwmod_init_postsetup();
616 if (of_have_populated_dt())
617 omap_clk_soc_init = dm814x_dt_clk_init;
618 }
619
ti816x_init_early(void)620 void __init ti816x_init_early(void)
621 {
622 omap2_set_globals_tap(TI816X_CLASS,
623 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
624 omap2_control_base_init();
625 omap3xxx_check_revision();
626 ti81xx_check_features();
627 omap2_prcm_base_init();
628 omap3xxx_voltagedomains_init();
629 omap3xxx_powerdomains_init();
630 ti816x_clockdomains_init();
631 dm816x_hwmod_init();
632 omap_hwmod_init_postsetup();
633 if (of_have_populated_dt())
634 omap_clk_soc_init = dm816x_dt_clk_init;
635 }
636 #endif
637
638 #ifdef CONFIG_SOC_AM33XX
am33xx_init_early(void)639 void __init am33xx_init_early(void)
640 {
641 omap2_set_globals_tap(AM335X_CLASS,
642 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
643 omap2_control_base_init();
644 omap3xxx_check_revision();
645 am33xx_check_features();
646 omap2_prcm_base_init();
647 am33xx_powerdomains_init();
648 am33xx_clockdomains_init();
649 am33xx_hwmod_init();
650 omap_hwmod_init_postsetup();
651 omap_clk_soc_init = am33xx_dt_clk_init;
652 }
653
am33xx_init_late(void)654 void __init am33xx_init_late(void)
655 {
656 omap_common_late_init();
657 }
658 #endif
659
660 #ifdef CONFIG_SOC_AM43XX
am43xx_init_early(void)661 void __init am43xx_init_early(void)
662 {
663 omap2_set_globals_tap(AM335X_CLASS,
664 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
665 omap2_control_base_init();
666 omap3xxx_check_revision();
667 am33xx_check_features();
668 omap2_prcm_base_init();
669 am43xx_powerdomains_init();
670 am43xx_clockdomains_init();
671 am43xx_hwmod_init();
672 omap_hwmod_init_postsetup();
673 omap_l2_cache_init();
674 omap_clk_soc_init = am43xx_dt_clk_init;
675 }
676
am43xx_init_late(void)677 void __init am43xx_init_late(void)
678 {
679 omap_common_late_init();
680 omap2_clk_enable_autoidle_all();
681 }
682 #endif
683
684 #ifdef CONFIG_ARCH_OMAP4
omap4430_init_early(void)685 void __init omap4430_init_early(void)
686 {
687 omap2_set_globals_tap(OMAP443X_CLASS,
688 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
689 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
690 omap2_control_base_init();
691 omap4xxx_check_revision();
692 omap4xxx_check_features();
693 omap2_prcm_base_init();
694 omap4_pm_init_early();
695 omap44xx_voltagedomains_init();
696 omap44xx_powerdomains_init();
697 omap44xx_clockdomains_init();
698 omap44xx_hwmod_init();
699 omap_hwmod_init_postsetup();
700 omap_l2_cache_init();
701 omap_clk_soc_init = omap4xxx_dt_clk_init;
702 }
703
omap4430_init_late(void)704 void __init omap4430_init_late(void)
705 {
706 omap_common_late_init();
707 omap4_pm_init();
708 omap2_clk_enable_autoidle_all();
709 }
710 #endif
711
712 #ifdef CONFIG_SOC_OMAP5
omap5_init_early(void)713 void __init omap5_init_early(void)
714 {
715 omap2_set_globals_tap(OMAP54XX_CLASS,
716 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
717 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
718 omap2_control_base_init();
719 omap4_pm_init_early();
720 omap2_prcm_base_init();
721 omap5xxx_check_revision();
722 omap54xx_voltagedomains_init();
723 omap54xx_powerdomains_init();
724 omap54xx_clockdomains_init();
725 omap54xx_hwmod_init();
726 omap_hwmod_init_postsetup();
727 omap_clk_soc_init = omap5xxx_dt_clk_init;
728 }
729
omap5_init_late(void)730 void __init omap5_init_late(void)
731 {
732 omap_common_late_init();
733 omap4_pm_init();
734 omap2_clk_enable_autoidle_all();
735 }
736 #endif
737
738 #ifdef CONFIG_SOC_DRA7XX
dra7xx_init_early(void)739 void __init dra7xx_init_early(void)
740 {
741 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
742 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
743 omap2_control_base_init();
744 omap4_pm_init_early();
745 omap2_prcm_base_init();
746 dra7xxx_check_revision();
747 dra7xx_powerdomains_init();
748 dra7xx_clockdomains_init();
749 dra7xx_hwmod_init();
750 omap_hwmod_init_postsetup();
751 omap_clk_soc_init = dra7xx_dt_clk_init;
752 }
753
dra7xx_init_late(void)754 void __init dra7xx_init_late(void)
755 {
756 omap_common_late_init();
757 omap4_pm_init();
758 omap2_clk_enable_autoidle_all();
759 }
760 #endif
761
762
omap_sdrc_init(struct omap_sdrc_params * sdrc_cs0,struct omap_sdrc_params * sdrc_cs1)763 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
764 struct omap_sdrc_params *sdrc_cs1)
765 {
766 omap_sram_init();
767
768 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
769 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
770 _omap2_init_reprogram_sdrc();
771 }
772 }
773
omap_clk_init(void)774 int __init omap_clk_init(void)
775 {
776 int ret = 0;
777
778 if (!omap_clk_soc_init)
779 return 0;
780
781 ti_clk_init_features();
782
783 omap2_clk_setup_ll_ops();
784
785 if (of_have_populated_dt()) {
786 ret = omap_control_init();
787 if (ret)
788 return ret;
789
790 ret = omap_prcm_init();
791 if (ret)
792 return ret;
793
794 of_clk_init(NULL);
795
796 ti_dt_clk_init_retry_clks();
797
798 ti_dt_clockdomains_setup();
799 }
800
801 ret = omap_clk_soc_init();
802
803 return ret;
804 }
805