1 /*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21 #include <linux/pm.h>
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
31 #include <linux/omap-dma.h>
32 #include <linux/omap-gpmc.h>
33 #include <linux/platform_data/gpio-omap.h>
34
35 #include <trace/events/power.h>
36
37 #include <asm/fncpy.h>
38 #include <asm/suspend.h>
39 #include <asm/system_misc.h>
40
41 #include "clockdomain.h"
42 #include "powerdomain.h"
43 #include "soc.h"
44 #include "common.h"
45 #include "cm3xxx.h"
46 #include "cm-regbits-34xx.h"
47 #include "prm-regbits-34xx.h"
48 #include "prm3xxx.h"
49 #include "pm.h"
50 #include "sdrc.h"
51 #include "omap-secure.h"
52 #include "sram.h"
53 #include "control.h"
54 #include "vc.h"
55
56 /* pm34xx errata defined in pm.h */
57 u16 pm34xx_errata;
58
59 struct power_state {
60 struct powerdomain *pwrdm;
61 u32 next_state;
62 #ifdef CONFIG_SUSPEND
63 u32 saved_state;
64 #endif
65 struct list_head node;
66 };
67
68 static LIST_HEAD(pwrst_list);
69
70 void (*omap3_do_wfi_sram)(void);
71
72 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
73 static struct powerdomain *core_pwrdm, *per_pwrdm;
74
omap3_core_save_context(void)75 static void omap3_core_save_context(void)
76 {
77 omap3_ctrl_save_padconf();
78
79 /*
80 * Force write last pad into memory, as this can fail in some
81 * cases according to errata 1.157, 1.185
82 */
83 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
84 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
85
86 /* Save the Interrupt controller context */
87 omap_intc_save_context();
88 /* Save the GPMC context */
89 omap3_gpmc_save_context();
90 /* Save the system control module context, padconf already save above*/
91 omap3_control_save_context();
92 omap_dma_global_context_save();
93 }
94
omap3_core_restore_context(void)95 static void omap3_core_restore_context(void)
96 {
97 /* Restore the control module context, padconf restored by h/w */
98 omap3_control_restore_context();
99 /* Restore the GPMC context */
100 omap3_gpmc_restore_context();
101 /* Restore the interrupt controller context */
102 omap_intc_restore_context();
103 omap_dma_global_context_restore();
104 }
105
106 /*
107 * FIXME: This function should be called before entering off-mode after
108 * OMAP3 secure services have been accessed. Currently it is only called
109 * once during boot sequence, but this works as we are not using secure
110 * services.
111 */
omap3_save_secure_ram_context(void)112 static void omap3_save_secure_ram_context(void)
113 {
114 u32 ret;
115 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
116
117 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
118 /*
119 * MPU next state must be set to POWER_ON temporarily,
120 * otherwise the WFI executed inside the ROM code
121 * will hang the system.
122 */
123 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
124 ret = omap3_save_secure_ram(omap3_secure_ram_storage,
125 OMAP3_SAVE_SECURE_RAM_SZ);
126 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
127 /* Following is for error tracking, it should not happen */
128 if (ret) {
129 pr_err("save_secure_sram() returns %08x\n", ret);
130 while (1)
131 ;
132 }
133 }
134 }
135
_prcm_int_handle_io(int irq,void * unused)136 static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
137 {
138 int c;
139
140 c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
141 OMAP3430_ST_IO_CHAIN_MASK);
142
143 return c ? IRQ_HANDLED : IRQ_NONE;
144 }
145
_prcm_int_handle_wakeup(int irq,void * unused)146 static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
147 {
148 int c;
149
150 /*
151 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
152 * these are handled in a separate handler to avoid acking
153 * IO events before parsing in mux code
154 */
155 c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
156 OMAP3430_ST_IO_CHAIN_MASK));
157 c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
158 c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
159 if (omap_rev() > OMAP3430_REV_ES1_0) {
160 c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
161 c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
162 }
163
164 return c ? IRQ_HANDLED : IRQ_NONE;
165 }
166
omap34xx_save_context(u32 * save)167 static void omap34xx_save_context(u32 *save)
168 {
169 u32 val;
170
171 /* Read Auxiliary Control Register */
172 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
173 *save++ = 1;
174 *save++ = val;
175
176 /* Read L2 AUX ctrl register */
177 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
178 *save++ = 1;
179 *save++ = val;
180 }
181
omap34xx_do_sram_idle(unsigned long save_state)182 static int omap34xx_do_sram_idle(unsigned long save_state)
183 {
184 omap34xx_cpu_suspend(save_state);
185 return 0;
186 }
187
omap_sram_idle(void)188 void omap_sram_idle(void)
189 {
190 /* Variable to tell what needs to be saved and restored
191 * in omap_sram_idle*/
192 /* save_state = 0 => Nothing to save and restored */
193 /* save_state = 1 => Only L1 and logic lost */
194 /* save_state = 2 => Only L2 lost */
195 /* save_state = 3 => L1, L2 and logic lost */
196 int save_state = 0;
197 int mpu_next_state = PWRDM_POWER_ON;
198 int per_next_state = PWRDM_POWER_ON;
199 int core_next_state = PWRDM_POWER_ON;
200 int per_going_off;
201 int core_prev_state;
202 u32 sdrc_pwr = 0;
203
204 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
205 switch (mpu_next_state) {
206 case PWRDM_POWER_ON:
207 case PWRDM_POWER_RET:
208 /* No need to save context */
209 save_state = 0;
210 break;
211 case PWRDM_POWER_OFF:
212 save_state = 3;
213 break;
214 default:
215 /* Invalid state */
216 pr_err("Invalid mpu state in sram_idle\n");
217 return;
218 }
219
220 /* NEON control */
221 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
222 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
223
224 /* Enable IO-PAD and IO-CHAIN wakeups */
225 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
226 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
227
228 pwrdm_pre_transition(NULL);
229
230 /* PER */
231 if (per_next_state < PWRDM_POWER_ON) {
232 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
233 omap2_gpio_prepare_for_idle(per_going_off);
234 }
235
236 /* CORE */
237 if (core_next_state < PWRDM_POWER_ON) {
238 if (core_next_state == PWRDM_POWER_OFF) {
239 omap3_core_save_context();
240 omap3_cm_save_context();
241 }
242 }
243
244 /* Configure PMIC signaling for I2C4 or sys_off_mode */
245 omap3_vc_set_pmic_signaling(core_next_state);
246
247 omap3_intc_prepare_idle();
248
249 /*
250 * On EMU/HS devices ROM code restores a SRDC value
251 * from scratchpad which has automatic self refresh on timeout
252 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
253 * Hence store/restore the SDRC_POWER register here.
254 */
255 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
256 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
257 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
258 core_next_state == PWRDM_POWER_OFF)
259 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
260
261 /*
262 * omap3_arm_context is the location where some ARM context
263 * get saved. The rest is placed on the stack, and restored
264 * from there before resuming.
265 */
266 if (save_state)
267 omap34xx_save_context(omap3_arm_context);
268 if (save_state == 1 || save_state == 3)
269 cpu_suspend(save_state, omap34xx_do_sram_idle);
270 else
271 omap34xx_do_sram_idle(save_state);
272
273 /* Restore normal SDRC POWER settings */
274 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
275 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
276 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
277 core_next_state == PWRDM_POWER_OFF)
278 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
279
280 /* CORE */
281 if (core_next_state < PWRDM_POWER_ON) {
282 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
283 if (core_prev_state == PWRDM_POWER_OFF) {
284 omap3_core_restore_context();
285 omap3_cm_restore_context();
286 omap3_sram_restore_context();
287 omap2_sms_restore_context();
288 }
289 }
290 omap3_intc_resume_idle();
291
292 pwrdm_post_transition(NULL);
293
294 /* PER */
295 if (per_next_state < PWRDM_POWER_ON)
296 omap2_gpio_resume_after_idle();
297 }
298
omap3_pm_idle(void)299 static void omap3_pm_idle(void)
300 {
301 if (omap_irq_pending())
302 return;
303
304 trace_cpu_idle_rcuidle(1, smp_processor_id());
305
306 omap_sram_idle();
307
308 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
309 }
310
311 #ifdef CONFIG_SUSPEND
omap3_pm_suspend(void)312 static int omap3_pm_suspend(void)
313 {
314 struct power_state *pwrst;
315 int state, ret = 0;
316
317 /* Read current next_pwrsts */
318 list_for_each_entry(pwrst, &pwrst_list, node)
319 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
320 /* Set ones wanted by suspend */
321 list_for_each_entry(pwrst, &pwrst_list, node) {
322 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
323 goto restore;
324 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
325 goto restore;
326 }
327
328 omap3_intc_suspend();
329
330 omap_sram_idle();
331
332 restore:
333 /* Restore next_pwrsts */
334 list_for_each_entry(pwrst, &pwrst_list, node) {
335 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
336 if (state > pwrst->next_state) {
337 pr_info("Powerdomain (%s) didn't enter target state %d\n",
338 pwrst->pwrdm->name, pwrst->next_state);
339 ret = -1;
340 }
341 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
342 }
343 if (ret)
344 pr_err("Could not enter target state in pm_suspend\n");
345 else
346 pr_info("Successfully put all powerdomains to target state\n");
347
348 return ret;
349 }
350 #else
351 #define omap3_pm_suspend NULL
352 #endif /* CONFIG_SUSPEND */
353
prcm_setup_regs(void)354 static void __init prcm_setup_regs(void)
355 {
356 omap3_ctrl_init();
357
358 omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
359 }
360
omap3_pm_off_mode_enable(int enable)361 void omap3_pm_off_mode_enable(int enable)
362 {
363 struct power_state *pwrst;
364 u32 state;
365
366 if (enable)
367 state = PWRDM_POWER_OFF;
368 else
369 state = PWRDM_POWER_RET;
370
371 list_for_each_entry(pwrst, &pwrst_list, node) {
372 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
373 pwrst->pwrdm == core_pwrdm &&
374 state == PWRDM_POWER_OFF) {
375 pwrst->next_state = PWRDM_POWER_RET;
376 pr_warn("%s: Core OFF disabled due to errata i583\n",
377 __func__);
378 } else {
379 pwrst->next_state = state;
380 }
381 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
382 }
383 }
384
omap3_pm_get_suspend_state(struct powerdomain * pwrdm)385 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
386 {
387 struct power_state *pwrst;
388
389 list_for_each_entry(pwrst, &pwrst_list, node) {
390 if (pwrst->pwrdm == pwrdm)
391 return pwrst->next_state;
392 }
393 return -EINVAL;
394 }
395
omap3_pm_set_suspend_state(struct powerdomain * pwrdm,int state)396 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
397 {
398 struct power_state *pwrst;
399
400 list_for_each_entry(pwrst, &pwrst_list, node) {
401 if (pwrst->pwrdm == pwrdm) {
402 pwrst->next_state = state;
403 return 0;
404 }
405 }
406 return -EINVAL;
407 }
408
pwrdms_setup(struct powerdomain * pwrdm,void * unused)409 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
410 {
411 struct power_state *pwrst;
412
413 if (!pwrdm->pwrsts)
414 return 0;
415
416 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
417 if (!pwrst)
418 return -ENOMEM;
419 pwrst->pwrdm = pwrdm;
420 pwrst->next_state = PWRDM_POWER_RET;
421 list_add(&pwrst->node, &pwrst_list);
422
423 if (pwrdm_has_hdwr_sar(pwrdm))
424 pwrdm_enable_hdwr_sar(pwrdm);
425
426 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
427 }
428
429 /*
430 * Push functions to SRAM
431 *
432 * The minimum set of functions is pushed to SRAM for execution:
433 * - omap3_do_wfi for erratum i581 WA,
434 */
omap_push_sram_idle(void)435 void omap_push_sram_idle(void)
436 {
437 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
438 }
439
pm_errata_configure(void)440 static void __init pm_errata_configure(void)
441 {
442 if (cpu_is_omap3630()) {
443 pm34xx_errata |= PM_RTA_ERRATUM_i608;
444 /* Enable the l2 cache toggling in sleep logic */
445 enable_omap3630_toggle_l2_on_restore();
446 if (omap_rev() < OMAP3630_REV_ES1_2)
447 pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
448 PM_PER_MEMORIES_ERRATUM_i582);
449 } else if (cpu_is_omap34xx()) {
450 pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
451 }
452 }
453
omap3_pm_init(void)454 int __init omap3_pm_init(void)
455 {
456 struct power_state *pwrst, *tmp;
457 struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
458 int ret;
459
460 if (!omap3_has_io_chain_ctrl())
461 pr_warn("PM: no software I/O chain control; some wakeups may be lost\n");
462
463 pm_errata_configure();
464
465 /* XXX prcm_setup_regs needs to be before enabling hw
466 * supervised mode for powerdomains */
467 prcm_setup_regs();
468
469 ret = request_irq(omap_prcm_event_to_irq("wkup"),
470 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
471
472 if (ret) {
473 pr_err("pm: Failed to request pm_wkup irq\n");
474 goto err1;
475 }
476
477 /* IO interrupt is shared with mux code */
478 ret = request_irq(omap_prcm_event_to_irq("io"),
479 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
480 omap3_pm_init);
481 enable_irq(omap_prcm_event_to_irq("io"));
482
483 if (ret) {
484 pr_err("pm: Failed to request pm_io irq\n");
485 goto err2;
486 }
487
488 ret = pwrdm_for_each(pwrdms_setup, NULL);
489 if (ret) {
490 pr_err("Failed to setup powerdomains\n");
491 goto err3;
492 }
493
494 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
495
496 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
497 if (mpu_pwrdm == NULL) {
498 pr_err("Failed to get mpu_pwrdm\n");
499 ret = -EINVAL;
500 goto err3;
501 }
502
503 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
504 per_pwrdm = pwrdm_lookup("per_pwrdm");
505 core_pwrdm = pwrdm_lookup("core_pwrdm");
506
507 neon_clkdm = clkdm_lookup("neon_clkdm");
508 mpu_clkdm = clkdm_lookup("mpu_clkdm");
509 per_clkdm = clkdm_lookup("per_clkdm");
510 wkup_clkdm = clkdm_lookup("wkup_clkdm");
511
512 omap_common_suspend_init(omap3_pm_suspend);
513
514 arm_pm_idle = omap3_pm_idle;
515 omap3_idle_init();
516
517 /*
518 * RTA is disabled during initialization as per erratum i608
519 * it is safer to disable RTA by the bootloader, but we would like
520 * to be doubly sure here and prevent any mishaps.
521 */
522 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
523 omap3630_ctrl_disable_rta();
524
525 /*
526 * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
527 * not correctly reset when the PER powerdomain comes back
528 * from OFF or OSWR when the CORE powerdomain is kept active.
529 * See OMAP36xx Erratum i582 "PER Domain reset issue after
530 * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a
531 * complete workaround. The kernel must also prevent the PER
532 * powerdomain from going to OSWR/OFF while the CORE
533 * powerdomain is not going to OSWR/OFF. And if PER last
534 * power state was off while CORE last power state was ON, the
535 * UART3/4 and McBSP2/3 SIDETONE devices need to run a
536 * self-test using their loopback tests; if that fails, those
537 * devices are unusable until the PER/CORE can complete a transition
538 * from ON to OSWR/OFF and then back to ON.
539 *
540 * XXX Technically this workaround is only needed if off-mode
541 * or OSWR is enabled.
542 */
543 if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
544 clkdm_add_wkdep(per_clkdm, wkup_clkdm);
545
546 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
547 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
548 omap3_secure_ram_storage =
549 kmalloc(OMAP3_SAVE_SECURE_RAM_SZ, GFP_KERNEL);
550 if (!omap3_secure_ram_storage)
551 pr_err("Memory allocation failed when allocating for secure sram context\n");
552
553 local_irq_disable();
554
555 omap_dma_global_context_save();
556 omap3_save_secure_ram_context();
557 omap_dma_global_context_restore();
558
559 local_irq_enable();
560 }
561
562 omap3_save_scratchpad_contents();
563 return ret;
564
565 err3:
566 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
567 list_del(&pwrst->node);
568 kfree(pwrst);
569 }
570 free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
571 err2:
572 free_irq(omap_prcm_event_to_irq("wkup"), NULL);
573 err1:
574 return ret;
575 }
576