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1 /*
2  * OMAP3xxx CM module functions
3  *
4  * Copyright (C) 2009 Nokia Corporation
5  * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
6  * Paul Walmsley
7  * Rajendra Nayak <rnayak@ti.com>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13 
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/delay.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20 
21 #include "prm2xxx_3xxx.h"
22 #include "cm.h"
23 #include "cm3xxx.h"
24 #include "cm-regbits-34xx.h"
25 #include "clockdomain.h"
26 
27 static const u8 omap3xxx_cm_idlest_offs[] = {
28 	CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
29 };
30 
31 /*
32  *
33  */
34 
_write_clktrctrl(u8 c,s16 module,u32 mask)35 static void _write_clktrctrl(u8 c, s16 module, u32 mask)
36 {
37 	u32 v;
38 
39 	v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
40 	v &= ~mask;
41 	v |= c << __ffs(mask);
42 	omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
43 }
44 
omap3xxx_cm_is_clkdm_in_hwsup(s16 module,u32 mask)45 static bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
46 {
47 	u32 v;
48 
49 	v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
50 	v &= mask;
51 	v >>= __ffs(mask);
52 
53 	return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
54 }
55 
omap3xxx_cm_clkdm_enable_hwsup(s16 module,u32 mask)56 static void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
57 {
58 	_write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
59 }
60 
omap3xxx_cm_clkdm_disable_hwsup(s16 module,u32 mask)61 static void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
62 {
63 	_write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
64 }
65 
omap3xxx_cm_clkdm_force_sleep(s16 module,u32 mask)66 static void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
67 {
68 	_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
69 }
70 
omap3xxx_cm_clkdm_force_wakeup(s16 module,u32 mask)71 static void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
72 {
73 	_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
74 }
75 
76 /*
77  *
78  */
79 
80 /**
81  * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby
82  * @part: PRCM partition, ignored for OMAP3
83  * @prcm_mod: PRCM module offset
84  * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
85  * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
86  *
87  * Wait for the PRCM to indicate that the module identified by
88  * (@prcm_mod, @idlest_id, @idlest_shift) is clocked.  Return 0 upon
89  * success or -EBUSY if the module doesn't enable in time.
90  */
omap3xxx_cm_wait_module_ready(u8 part,s16 prcm_mod,u16 idlest_id,u8 idlest_shift)91 static int omap3xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
92 					 u8 idlest_shift)
93 {
94 	int ena = 0, i = 0;
95 	u8 cm_idlest_reg;
96 	u32 mask;
97 
98 	if (!idlest_id || (idlest_id > ARRAY_SIZE(omap3xxx_cm_idlest_offs)))
99 		return -EINVAL;
100 
101 	cm_idlest_reg = omap3xxx_cm_idlest_offs[idlest_id - 1];
102 
103 	mask = 1 << idlest_shift;
104 	ena = 0;
105 
106 	omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
107 			    mask) == ena), MAX_MODULE_READY_TIME, i);
108 
109 	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
110 }
111 
112 /**
113  * omap3xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
114  * @idlest_reg: CM_IDLEST* virtual address
115  * @prcm_inst: pointer to an s16 to return the PRCM instance offset
116  * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
117  *
118  * XXX This function is only needed until absolute register addresses are
119  * removed from the OMAP struct clk records.
120  */
omap3xxx_cm_split_idlest_reg(void __iomem * idlest_reg,s16 * prcm_inst,u8 * idlest_reg_id)121 static int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
122 					s16 *prcm_inst,
123 					u8 *idlest_reg_id)
124 {
125 	unsigned long offs;
126 	u8 idlest_offs;
127 	int i;
128 
129 	if (idlest_reg < (cm_base + OMAP3430_IVA2_MOD) ||
130 	    idlest_reg > (cm_base + 0x1ffff))
131 		return -EINVAL;
132 
133 	idlest_offs = (unsigned long)idlest_reg & 0xff;
134 	for (i = 0; i < ARRAY_SIZE(omap3xxx_cm_idlest_offs); i++) {
135 		if (idlest_offs == omap3xxx_cm_idlest_offs[i]) {
136 			*idlest_reg_id = i + 1;
137 			break;
138 		}
139 	}
140 
141 	if (i == ARRAY_SIZE(omap3xxx_cm_idlest_offs))
142 		return -EINVAL;
143 
144 	offs = idlest_reg - cm_base;
145 	offs &= 0xff00;
146 	*prcm_inst = offs;
147 
148 	return 0;
149 }
150 
151 /* Clockdomain low-level operations */
152 
omap3xxx_clkdm_add_sleepdep(struct clockdomain * clkdm1,struct clockdomain * clkdm2)153 static int omap3xxx_clkdm_add_sleepdep(struct clockdomain *clkdm1,
154 				       struct clockdomain *clkdm2)
155 {
156 	omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
157 				  clkdm1->pwrdm.ptr->prcm_offs,
158 				  OMAP3430_CM_SLEEPDEP);
159 	return 0;
160 }
161 
omap3xxx_clkdm_del_sleepdep(struct clockdomain * clkdm1,struct clockdomain * clkdm2)162 static int omap3xxx_clkdm_del_sleepdep(struct clockdomain *clkdm1,
163 				       struct clockdomain *clkdm2)
164 {
165 	omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
166 				    clkdm1->pwrdm.ptr->prcm_offs,
167 				    OMAP3430_CM_SLEEPDEP);
168 	return 0;
169 }
170 
omap3xxx_clkdm_read_sleepdep(struct clockdomain * clkdm1,struct clockdomain * clkdm2)171 static int omap3xxx_clkdm_read_sleepdep(struct clockdomain *clkdm1,
172 					struct clockdomain *clkdm2)
173 {
174 	return omap2_cm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
175 					    OMAP3430_CM_SLEEPDEP,
176 					    (1 << clkdm2->dep_bit));
177 }
178 
omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain * clkdm)179 static int omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
180 {
181 	struct clkdm_dep *cd;
182 	u32 mask = 0;
183 
184 	for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
185 		if (!cd->clkdm)
186 			continue; /* only happens if data is erroneous */
187 
188 		mask |= 1 << cd->clkdm->dep_bit;
189 		cd->sleepdep_usecount = 0;
190 	}
191 	omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
192 				    OMAP3430_CM_SLEEPDEP);
193 	return 0;
194 }
195 
omap3xxx_clkdm_sleep(struct clockdomain * clkdm)196 static int omap3xxx_clkdm_sleep(struct clockdomain *clkdm)
197 {
198 	omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
199 				      clkdm->clktrctrl_mask);
200 	return 0;
201 }
202 
omap3xxx_clkdm_wakeup(struct clockdomain * clkdm)203 static int omap3xxx_clkdm_wakeup(struct clockdomain *clkdm)
204 {
205 	omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
206 				       clkdm->clktrctrl_mask);
207 	return 0;
208 }
209 
omap3xxx_clkdm_allow_idle(struct clockdomain * clkdm)210 static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm)
211 {
212 	if (clkdm->usecount > 0)
213 		clkdm_add_autodeps(clkdm);
214 
215 	omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
216 				       clkdm->clktrctrl_mask);
217 }
218 
omap3xxx_clkdm_deny_idle(struct clockdomain * clkdm)219 static void omap3xxx_clkdm_deny_idle(struct clockdomain *clkdm)
220 {
221 	omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
222 					clkdm->clktrctrl_mask);
223 
224 	if (clkdm->usecount > 0)
225 		clkdm_del_autodeps(clkdm);
226 }
227 
omap3xxx_clkdm_clk_enable(struct clockdomain * clkdm)228 static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
229 {
230 	bool hwsup = false;
231 
232 	if (!clkdm->clktrctrl_mask)
233 		return 0;
234 
235 	/*
236 	 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
237 	 * more details on the unpleasant problem this is working
238 	 * around
239 	 */
240 	if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
241 	    (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
242 		omap3xxx_clkdm_wakeup(clkdm);
243 		return 0;
244 	}
245 
246 	hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
247 					      clkdm->clktrctrl_mask);
248 
249 	if (hwsup) {
250 		/* Disable HW transitions when we are changing deps */
251 		omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
252 						clkdm->clktrctrl_mask);
253 		clkdm_add_autodeps(clkdm);
254 		omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
255 					       clkdm->clktrctrl_mask);
256 	} else {
257 		if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
258 			omap3xxx_clkdm_wakeup(clkdm);
259 	}
260 
261 	return 0;
262 }
263 
omap3xxx_clkdm_clk_disable(struct clockdomain * clkdm)264 static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
265 {
266 	bool hwsup = false;
267 
268 	if (!clkdm->clktrctrl_mask)
269 		return 0;
270 
271 	/*
272 	 * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
273 	 * more details on the unpleasant problem this is working
274 	 * around
275 	 */
276 	if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
277 	    !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
278 		omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
279 					       clkdm->clktrctrl_mask);
280 		return 0;
281 	}
282 
283 	hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
284 					      clkdm->clktrctrl_mask);
285 
286 	if (hwsup) {
287 		/* Disable HW transitions when we are changing deps */
288 		omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
289 						clkdm->clktrctrl_mask);
290 		clkdm_del_autodeps(clkdm);
291 		omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
292 					       clkdm->clktrctrl_mask);
293 	} else {
294 		if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
295 			omap3xxx_clkdm_sleep(clkdm);
296 	}
297 
298 	return 0;
299 }
300 
301 struct clkdm_ops omap3_clkdm_operations = {
302 	.clkdm_add_wkdep	= omap2_clkdm_add_wkdep,
303 	.clkdm_del_wkdep	= omap2_clkdm_del_wkdep,
304 	.clkdm_read_wkdep	= omap2_clkdm_read_wkdep,
305 	.clkdm_clear_all_wkdeps	= omap2_clkdm_clear_all_wkdeps,
306 	.clkdm_add_sleepdep	= omap3xxx_clkdm_add_sleepdep,
307 	.clkdm_del_sleepdep	= omap3xxx_clkdm_del_sleepdep,
308 	.clkdm_read_sleepdep	= omap3xxx_clkdm_read_sleepdep,
309 	.clkdm_clear_all_sleepdeps	= omap3xxx_clkdm_clear_all_sleepdeps,
310 	.clkdm_sleep		= omap3xxx_clkdm_sleep,
311 	.clkdm_wakeup		= omap3xxx_clkdm_wakeup,
312 	.clkdm_allow_idle	= omap3xxx_clkdm_allow_idle,
313 	.clkdm_deny_idle	= omap3xxx_clkdm_deny_idle,
314 	.clkdm_clk_enable	= omap3xxx_clkdm_clk_enable,
315 	.clkdm_clk_disable	= omap3xxx_clkdm_clk_disable,
316 };
317 
318 /*
319  * Context save/restore code - OMAP3 only
320  */
321 struct omap3_cm_regs {
322 	u32 iva2_cm_clksel1;
323 	u32 iva2_cm_clksel2;
324 	u32 cm_sysconfig;
325 	u32 sgx_cm_clksel;
326 	u32 dss_cm_clksel;
327 	u32 cam_cm_clksel;
328 	u32 per_cm_clksel;
329 	u32 emu_cm_clksel;
330 	u32 emu_cm_clkstctrl;
331 	u32 pll_cm_autoidle;
332 	u32 pll_cm_autoidle2;
333 	u32 pll_cm_clksel4;
334 	u32 pll_cm_clksel5;
335 	u32 pll_cm_clken2;
336 	u32 cm_polctrl;
337 	u32 iva2_cm_fclken;
338 	u32 iva2_cm_clken_pll;
339 	u32 core_cm_fclken1;
340 	u32 core_cm_fclken3;
341 	u32 sgx_cm_fclken;
342 	u32 wkup_cm_fclken;
343 	u32 dss_cm_fclken;
344 	u32 cam_cm_fclken;
345 	u32 per_cm_fclken;
346 	u32 usbhost_cm_fclken;
347 	u32 core_cm_iclken1;
348 	u32 core_cm_iclken2;
349 	u32 core_cm_iclken3;
350 	u32 sgx_cm_iclken;
351 	u32 wkup_cm_iclken;
352 	u32 dss_cm_iclken;
353 	u32 cam_cm_iclken;
354 	u32 per_cm_iclken;
355 	u32 usbhost_cm_iclken;
356 	u32 iva2_cm_autoidle2;
357 	u32 mpu_cm_autoidle2;
358 	u32 iva2_cm_clkstctrl;
359 	u32 mpu_cm_clkstctrl;
360 	u32 core_cm_clkstctrl;
361 	u32 sgx_cm_clkstctrl;
362 	u32 dss_cm_clkstctrl;
363 	u32 cam_cm_clkstctrl;
364 	u32 per_cm_clkstctrl;
365 	u32 neon_cm_clkstctrl;
366 	u32 usbhost_cm_clkstctrl;
367 	u32 core_cm_autoidle1;
368 	u32 core_cm_autoidle2;
369 	u32 core_cm_autoidle3;
370 	u32 wkup_cm_autoidle;
371 	u32 dss_cm_autoidle;
372 	u32 cam_cm_autoidle;
373 	u32 per_cm_autoidle;
374 	u32 usbhost_cm_autoidle;
375 	u32 sgx_cm_sleepdep;
376 	u32 dss_cm_sleepdep;
377 	u32 cam_cm_sleepdep;
378 	u32 per_cm_sleepdep;
379 	u32 usbhost_cm_sleepdep;
380 	u32 cm_clkout_ctrl;
381 };
382 
383 static struct omap3_cm_regs cm_context;
384 
omap3_cm_save_context(void)385 void omap3_cm_save_context(void)
386 {
387 	cm_context.iva2_cm_clksel1 =
388 		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
389 	cm_context.iva2_cm_clksel2 =
390 		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
391 	cm_context.cm_sysconfig =
392 		omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_SYSCONFIG);
393 	cm_context.sgx_cm_clksel =
394 		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
395 	cm_context.dss_cm_clksel =
396 		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
397 	cm_context.cam_cm_clksel =
398 		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
399 	cm_context.per_cm_clksel =
400 		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
401 	cm_context.emu_cm_clksel =
402 		omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
403 	cm_context.emu_cm_clkstctrl =
404 		omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
405 	/*
406 	 * As per erratum i671, ROM code does not respect the PER DPLL
407 	 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
408 	 * In this case, even though this register has been saved in
409 	 * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
410 	 * by ourselves. So, we need to save it anyway.
411 	 */
412 	cm_context.pll_cm_autoidle =
413 		omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
414 	cm_context.pll_cm_autoidle2 =
415 		omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
416 	cm_context.pll_cm_clksel4 =
417 		omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
418 	cm_context.pll_cm_clksel5 =
419 		omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
420 	cm_context.pll_cm_clken2 =
421 		omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
422 	cm_context.cm_polctrl =
423 		omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_POLCTRL);
424 	cm_context.iva2_cm_fclken =
425 		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
426 	cm_context.iva2_cm_clken_pll =
427 		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
428 	cm_context.core_cm_fclken1 =
429 		omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
430 	cm_context.core_cm_fclken3 =
431 		omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
432 	cm_context.sgx_cm_fclken =
433 		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
434 	cm_context.wkup_cm_fclken =
435 		omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
436 	cm_context.dss_cm_fclken =
437 		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
438 	cm_context.cam_cm_fclken =
439 		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
440 	cm_context.per_cm_fclken =
441 		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
442 	cm_context.usbhost_cm_fclken =
443 		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
444 	cm_context.core_cm_iclken1 =
445 		omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
446 	cm_context.core_cm_iclken2 =
447 		omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
448 	cm_context.core_cm_iclken3 =
449 		omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
450 	cm_context.sgx_cm_iclken =
451 		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
452 	cm_context.wkup_cm_iclken =
453 		omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
454 	cm_context.dss_cm_iclken =
455 		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
456 	cm_context.cam_cm_iclken =
457 		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
458 	cm_context.per_cm_iclken =
459 		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
460 	cm_context.usbhost_cm_iclken =
461 		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
462 	cm_context.iva2_cm_autoidle2 =
463 		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
464 	cm_context.mpu_cm_autoidle2 =
465 		omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
466 	cm_context.iva2_cm_clkstctrl =
467 		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
468 	cm_context.mpu_cm_clkstctrl =
469 		omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
470 	cm_context.core_cm_clkstctrl =
471 		omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
472 	cm_context.sgx_cm_clkstctrl =
473 		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
474 	cm_context.dss_cm_clkstctrl =
475 		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
476 	cm_context.cam_cm_clkstctrl =
477 		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
478 	cm_context.per_cm_clkstctrl =
479 		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
480 	cm_context.neon_cm_clkstctrl =
481 		omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
482 	cm_context.usbhost_cm_clkstctrl =
483 		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
484 				      OMAP2_CM_CLKSTCTRL);
485 	cm_context.core_cm_autoidle1 =
486 		omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
487 	cm_context.core_cm_autoidle2 =
488 		omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
489 	cm_context.core_cm_autoidle3 =
490 		omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
491 	cm_context.wkup_cm_autoidle =
492 		omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
493 	cm_context.dss_cm_autoidle =
494 		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
495 	cm_context.cam_cm_autoidle =
496 		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
497 	cm_context.per_cm_autoidle =
498 		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
499 	cm_context.usbhost_cm_autoidle =
500 		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
501 	cm_context.sgx_cm_sleepdep =
502 		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
503 				      OMAP3430_CM_SLEEPDEP);
504 	cm_context.dss_cm_sleepdep =
505 		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
506 	cm_context.cam_cm_sleepdep =
507 		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
508 	cm_context.per_cm_sleepdep =
509 		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
510 	cm_context.usbhost_cm_sleepdep =
511 		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
512 				      OMAP3430_CM_SLEEPDEP);
513 	cm_context.cm_clkout_ctrl =
514 		omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
515 				      OMAP3_CM_CLKOUT_CTRL_OFFSET);
516 }
517 
omap3_cm_restore_context(void)518 void omap3_cm_restore_context(void)
519 {
520 	omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
521 			       CM_CLKSEL1);
522 	omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
523 			       CM_CLKSEL2);
524 	omap2_cm_write_mod_reg(cm_context.cm_sysconfig, OCP_MOD,
525 			       OMAP3430_CM_SYSCONFIG);
526 	omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
527 			       CM_CLKSEL);
528 	omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
529 			       CM_CLKSEL);
530 	omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
531 			       CM_CLKSEL);
532 	omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
533 			       CM_CLKSEL);
534 	omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
535 			       CM_CLKSEL1);
536 	omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
537 			       OMAP2_CM_CLKSTCTRL);
538 	/*
539 	 * As per erratum i671, ROM code does not respect the PER DPLL
540 	 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
541 	 * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
542 	 */
543 	omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
544 			       CM_AUTOIDLE);
545 	omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
546 			       CM_AUTOIDLE2);
547 	omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
548 			       OMAP3430ES2_CM_CLKSEL4);
549 	omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
550 			       OMAP3430ES2_CM_CLKSEL5);
551 	omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
552 			       OMAP3430ES2_CM_CLKEN2);
553 	omap2_cm_write_mod_reg(cm_context.cm_polctrl, OCP_MOD,
554 			       OMAP3430_CM_POLCTRL);
555 	omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
556 			       CM_FCLKEN);
557 	omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
558 			       OMAP3430_CM_CLKEN_PLL);
559 	omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
560 			       CM_FCLKEN1);
561 	omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
562 			       OMAP3430ES2_CM_FCLKEN3);
563 	omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
564 			       CM_FCLKEN);
565 	omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
566 	omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
567 			       CM_FCLKEN);
568 	omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
569 			       CM_FCLKEN);
570 	omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
571 			       CM_FCLKEN);
572 	omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
573 			       OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
574 	omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
575 			       CM_ICLKEN1);
576 	omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
577 			       CM_ICLKEN2);
578 	omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
579 			       CM_ICLKEN3);
580 	omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
581 			       CM_ICLKEN);
582 	omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
583 	omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
584 			       CM_ICLKEN);
585 	omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
586 			       CM_ICLKEN);
587 	omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
588 			       CM_ICLKEN);
589 	omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
590 			       OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
591 	omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
592 			       CM_AUTOIDLE2);
593 	omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
594 			       CM_AUTOIDLE2);
595 	omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
596 			       OMAP2_CM_CLKSTCTRL);
597 	omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
598 			       OMAP2_CM_CLKSTCTRL);
599 	omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
600 			       OMAP2_CM_CLKSTCTRL);
601 	omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
602 			       OMAP2_CM_CLKSTCTRL);
603 	omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
604 			       OMAP2_CM_CLKSTCTRL);
605 	omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
606 			       OMAP2_CM_CLKSTCTRL);
607 	omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
608 			       OMAP2_CM_CLKSTCTRL);
609 	omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
610 			       OMAP2_CM_CLKSTCTRL);
611 	omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
612 			       OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
613 	omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
614 			       CM_AUTOIDLE1);
615 	omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
616 			       CM_AUTOIDLE2);
617 	omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
618 			       CM_AUTOIDLE3);
619 	omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
620 			       CM_AUTOIDLE);
621 	omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
622 			       CM_AUTOIDLE);
623 	omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
624 			       CM_AUTOIDLE);
625 	omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
626 			       CM_AUTOIDLE);
627 	omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
628 			       OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
629 	omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
630 			       OMAP3430_CM_SLEEPDEP);
631 	omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
632 			       OMAP3430_CM_SLEEPDEP);
633 	omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
634 			       OMAP3430_CM_SLEEPDEP);
635 	omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
636 			       OMAP3430_CM_SLEEPDEP);
637 	omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
638 			       OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
639 	omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
640 			       OMAP3_CM_CLKOUT_CTRL_OFFSET);
641 }
642 
omap3_cm_save_scratchpad_contents(u32 * ptr)643 void omap3_cm_save_scratchpad_contents(u32 *ptr)
644 {
645 	*ptr++ = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
646 	*ptr++ = omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
647 	*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
648 
649 	/*
650 	 * As per erratum i671, ROM code does not respect the PER DPLL
651 	 * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
652 	 * Then,  in anycase, clear these bits to avoid extra latencies.
653 	 */
654 	*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
655 		~OMAP3430_AUTO_PERIPH_DPLL_MASK;
656 	*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
657 	*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
658 	*ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
659 	*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
660 	*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
661 	*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
662 	*ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
663 }
664 
665 /*
666  *
667  */
668 
669 static struct cm_ll_data omap3xxx_cm_ll_data = {
670 	.split_idlest_reg	= &omap3xxx_cm_split_idlest_reg,
671 	.wait_module_ready	= &omap3xxx_cm_wait_module_ready,
672 };
673 
omap3xxx_cm_init(const struct omap_prcm_init_data * data)674 int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data)
675 {
676 	omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD);
677 	return cm_register(&omap3xxx_cm_ll_data);
678 }
679 
omap3xxx_cm_exit(void)680 static void __exit omap3xxx_cm_exit(void)
681 {
682 	cm_unregister(&omap3xxx_cm_ll_data);
683 }
684 __exitcall(omap3xxx_cm_exit);
685