1 /*
2 * OMAP2plus display device setup / initialization.
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Senthilvadivu Guruswamy
6 * Sumit Semwal
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/string.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
25 #include <linux/delay.h>
26 #include <linux/of.h>
27 #include <linux/of_platform.h>
28 #include <linux/slab.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/regmap.h>
31
32 #include <video/omapdss.h>
33 #include "omap_hwmod.h"
34 #include "omap_device.h"
35 #include "omap-pm.h"
36 #include "common.h"
37
38 #include "soc.h"
39 #include "iomap.h"
40 #include "control.h"
41 #include "display.h"
42 #include "prm.h"
43
44 #define DISPC_CONTROL 0x0040
45 #define DISPC_CONTROL2 0x0238
46 #define DISPC_CONTROL3 0x0848
47 #define DISPC_IRQSTATUS 0x0018
48
49 #define DSS_SYSCONFIG 0x10
50 #define DSS_SYSSTATUS 0x14
51 #define DSS_CONTROL 0x40
52 #define DSS_SDI_CONTROL 0x44
53 #define DSS_PLL_CONTROL 0x48
54
55 #define LCD_EN_MASK (0x1 << 0)
56 #define DIGIT_EN_MASK (0x1 << 1)
57
58 #define FRAMEDONE_IRQ_SHIFT 0
59 #define EVSYNC_EVEN_IRQ_SHIFT 2
60 #define EVSYNC_ODD_IRQ_SHIFT 3
61 #define FRAMEDONE2_IRQ_SHIFT 22
62 #define FRAMEDONE3_IRQ_SHIFT 30
63 #define FRAMEDONETV_IRQ_SHIFT 24
64
65 /*
66 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
67 * reset before deciding that something has gone wrong
68 */
69 #define FRAMEDONE_IRQ_TIMEOUT 100
70
71 static struct platform_device omap_display_device = {
72 .name = "omapdss",
73 .id = -1,
74 .dev = {
75 .platform_data = NULL,
76 },
77 };
78
79 struct omap_dss_hwmod_data {
80 const char *oh_name;
81 const char *dev_name;
82 const int id;
83 };
84
85 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
86 { "dss_core", "omapdss_dss", -1 },
87 { "dss_dispc", "omapdss_dispc", -1 },
88 { "dss_rfbi", "omapdss_rfbi", -1 },
89 { "dss_venc", "omapdss_venc", -1 },
90 };
91
92 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
93 { "dss_core", "omapdss_dss", -1 },
94 { "dss_dispc", "omapdss_dispc", -1 },
95 { "dss_rfbi", "omapdss_rfbi", -1 },
96 { "dss_venc", "omapdss_venc", -1 },
97 { "dss_dsi1", "omapdss_dsi", 0 },
98 };
99
100 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
101 { "dss_core", "omapdss_dss", -1 },
102 { "dss_dispc", "omapdss_dispc", -1 },
103 { "dss_rfbi", "omapdss_rfbi", -1 },
104 { "dss_dsi1", "omapdss_dsi", 0 },
105 { "dss_dsi2", "omapdss_dsi", 1 },
106 { "dss_hdmi", "omapdss_hdmi", -1 },
107 };
108
109 #define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
110
111 static struct regmap *omap4_dsi_mux_syscon;
112
omap4_dsi_mux_pads(int dsi_id,unsigned lanes)113 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
114 {
115 u32 enable_mask, enable_shift;
116 u32 pipd_mask, pipd_shift;
117 u32 reg;
118 int ret;
119
120 if (dsi_id == 0) {
121 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
122 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
123 pipd_mask = OMAP4_DSI1_PIPD_MASK;
124 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
125 } else if (dsi_id == 1) {
126 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
127 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
128 pipd_mask = OMAP4_DSI2_PIPD_MASK;
129 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
130 } else {
131 return -ENODEV;
132 }
133
134 ret = regmap_read(omap4_dsi_mux_syscon,
135 OMAP4_DSIPHY_SYSCON_OFFSET,
136 ®);
137 if (ret)
138 return ret;
139
140 reg &= ~enable_mask;
141 reg &= ~pipd_mask;
142
143 reg |= (lanes << enable_shift) & enable_mask;
144 reg |= (lanes << pipd_shift) & pipd_mask;
145
146 regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
147
148 return 0;
149 }
150
omap_dsi_enable_pads(int dsi_id,unsigned lane_mask)151 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
152 {
153 if (cpu_is_omap44xx())
154 return omap4_dsi_mux_pads(dsi_id, lane_mask);
155
156 return 0;
157 }
158
omap_dsi_disable_pads(int dsi_id,unsigned lane_mask)159 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
160 {
161 if (cpu_is_omap44xx())
162 omap4_dsi_mux_pads(dsi_id, 0);
163 }
164
omap_dss_set_min_bus_tput(struct device * dev,unsigned long tput)165 static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
166 {
167 return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
168 }
169
create_dss_pdev(const char * pdev_name,int pdev_id,const char * oh_name,void * pdata,int pdata_len,struct platform_device * parent)170 static struct platform_device *create_dss_pdev(const char *pdev_name,
171 int pdev_id, const char *oh_name, void *pdata, int pdata_len,
172 struct platform_device *parent)
173 {
174 struct platform_device *pdev;
175 struct omap_device *od;
176 struct omap_hwmod *ohs[1];
177 struct omap_hwmod *oh;
178 int r;
179
180 oh = omap_hwmod_lookup(oh_name);
181 if (!oh) {
182 pr_err("Could not look up %s\n", oh_name);
183 r = -ENODEV;
184 goto err;
185 }
186
187 pdev = platform_device_alloc(pdev_name, pdev_id);
188 if (!pdev) {
189 pr_err("Could not create pdev for %s\n", pdev_name);
190 r = -ENOMEM;
191 goto err;
192 }
193
194 if (parent != NULL)
195 pdev->dev.parent = &parent->dev;
196
197 if (pdev->id != -1)
198 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
199 else
200 dev_set_name(&pdev->dev, "%s", pdev->name);
201
202 ohs[0] = oh;
203 od = omap_device_alloc(pdev, ohs, 1);
204 if (IS_ERR(od)) {
205 pr_err("Could not alloc omap_device for %s\n", pdev_name);
206 r = -ENOMEM;
207 goto err;
208 }
209
210 r = platform_device_add_data(pdev, pdata, pdata_len);
211 if (r) {
212 pr_err("Could not set pdata for %s\n", pdev_name);
213 goto err;
214 }
215
216 r = omap_device_register(pdev);
217 if (r) {
218 pr_err("Could not register omap_device for %s\n", pdev_name);
219 goto err;
220 }
221
222 return pdev;
223
224 err:
225 return ERR_PTR(r);
226 }
227
create_simple_dss_pdev(const char * pdev_name,int pdev_id,void * pdata,int pdata_len,struct platform_device * parent)228 static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
229 int pdev_id, void *pdata, int pdata_len,
230 struct platform_device *parent)
231 {
232 struct platform_device *pdev;
233 int r;
234
235 pdev = platform_device_alloc(pdev_name, pdev_id);
236 if (!pdev) {
237 pr_err("Could not create pdev for %s\n", pdev_name);
238 r = -ENOMEM;
239 goto err;
240 }
241
242 if (parent != NULL)
243 pdev->dev.parent = &parent->dev;
244
245 if (pdev->id != -1)
246 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
247 else
248 dev_set_name(&pdev->dev, "%s", pdev->name);
249
250 r = platform_device_add_data(pdev, pdata, pdata_len);
251 if (r) {
252 pr_err("Could not set pdata for %s\n", pdev_name);
253 goto err;
254 }
255
256 r = platform_device_add(pdev);
257 if (r) {
258 pr_err("Could not register platform_device for %s\n", pdev_name);
259 goto err;
260 }
261
262 return pdev;
263
264 err:
265 return ERR_PTR(r);
266 }
267
omap_display_get_version(void)268 static enum omapdss_version __init omap_display_get_version(void)
269 {
270 if (cpu_is_omap24xx())
271 return OMAPDSS_VER_OMAP24xx;
272 else if (cpu_is_omap3630())
273 return OMAPDSS_VER_OMAP3630;
274 else if (cpu_is_omap34xx()) {
275 if (soc_is_am35xx()) {
276 return OMAPDSS_VER_AM35xx;
277 } else {
278 if (omap_rev() < OMAP3430_REV_ES3_0)
279 return OMAPDSS_VER_OMAP34xx_ES1;
280 else
281 return OMAPDSS_VER_OMAP34xx_ES3;
282 }
283 } else if (omap_rev() == OMAP4430_REV_ES1_0)
284 return OMAPDSS_VER_OMAP4430_ES1;
285 else if (omap_rev() == OMAP4430_REV_ES2_0 ||
286 omap_rev() == OMAP4430_REV_ES2_1 ||
287 omap_rev() == OMAP4430_REV_ES2_2)
288 return OMAPDSS_VER_OMAP4430_ES2;
289 else if (cpu_is_omap44xx())
290 return OMAPDSS_VER_OMAP4;
291 else if (soc_is_omap54xx())
292 return OMAPDSS_VER_OMAP5;
293 else if (soc_is_am43xx())
294 return OMAPDSS_VER_AM43xx;
295 else if (soc_is_dra7xx())
296 return OMAPDSS_VER_DRA7xx;
297 else
298 return OMAPDSS_VER_UNKNOWN;
299 }
300
omap_display_init(struct omap_dss_board_info * board_data)301 int __init omap_display_init(struct omap_dss_board_info *board_data)
302 {
303 int r = 0;
304 struct platform_device *pdev;
305 int i, oh_count;
306 const struct omap_dss_hwmod_data *curr_dss_hwmod;
307 struct platform_device *dss_pdev;
308 enum omapdss_version ver;
309
310 /* create omapdss device */
311
312 ver = omap_display_get_version();
313
314 if (ver == OMAPDSS_VER_UNKNOWN) {
315 pr_err("DSS not supported on this SoC\n");
316 return -ENODEV;
317 }
318
319 board_data->version = ver;
320 board_data->dsi_enable_pads = omap_dsi_enable_pads;
321 board_data->dsi_disable_pads = omap_dsi_disable_pads;
322 board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
323
324 omap_display_device.dev.platform_data = board_data;
325
326 r = platform_device_register(&omap_display_device);
327 if (r < 0) {
328 pr_err("Unable to register omapdss device\n");
329 return r;
330 }
331
332 /* create devices for dss hwmods */
333
334 if (cpu_is_omap24xx()) {
335 curr_dss_hwmod = omap2_dss_hwmod_data;
336 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
337 } else if (cpu_is_omap34xx()) {
338 curr_dss_hwmod = omap3_dss_hwmod_data;
339 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
340 } else {
341 curr_dss_hwmod = omap4_dss_hwmod_data;
342 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
343 }
344
345 /*
346 * First create the pdev for dss_core, which is used as a parent device
347 * by the other dss pdevs. Note: dss_core has to be the first item in
348 * the hwmod list.
349 */
350 dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
351 curr_dss_hwmod[0].id,
352 curr_dss_hwmod[0].oh_name,
353 board_data, sizeof(*board_data),
354 NULL);
355
356 if (IS_ERR(dss_pdev)) {
357 pr_err("Could not build omap_device for %s\n",
358 curr_dss_hwmod[0].oh_name);
359
360 return PTR_ERR(dss_pdev);
361 }
362
363 for (i = 1; i < oh_count; i++) {
364 pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
365 curr_dss_hwmod[i].id,
366 curr_dss_hwmod[i].oh_name,
367 board_data, sizeof(*board_data),
368 dss_pdev);
369
370 if (IS_ERR(pdev)) {
371 pr_err("Could not build omap_device for %s\n",
372 curr_dss_hwmod[i].oh_name);
373
374 return PTR_ERR(pdev);
375 }
376 }
377
378 /* Create devices for DPI and SDI */
379
380 pdev = create_simple_dss_pdev("omapdss_dpi", 0,
381 board_data, sizeof(*board_data), dss_pdev);
382 if (IS_ERR(pdev)) {
383 pr_err("Could not build platform_device for omapdss_dpi\n");
384 return PTR_ERR(pdev);
385 }
386
387 if (cpu_is_omap34xx()) {
388 pdev = create_simple_dss_pdev("omapdss_sdi", 0,
389 board_data, sizeof(*board_data), dss_pdev);
390 if (IS_ERR(pdev)) {
391 pr_err("Could not build platform_device for omapdss_sdi\n");
392 return PTR_ERR(pdev);
393 }
394 }
395
396 /* create DRM device */
397 r = omap_init_drm();
398 if (r < 0) {
399 pr_err("Unable to register omapdrm device\n");
400 return r;
401 }
402
403 /* create vrfb device */
404 r = omap_init_vrfb();
405 if (r < 0) {
406 pr_err("Unable to register omapvrfb device\n");
407 return r;
408 }
409
410 /* create FB device */
411 r = omap_init_fb();
412 if (r < 0) {
413 pr_err("Unable to register omapfb device\n");
414 return r;
415 }
416
417 /* create V4L2 display device */
418 r = omap_init_vout();
419 if (r < 0) {
420 pr_err("Unable to register omap_vout device\n");
421 return r;
422 }
423
424 return 0;
425 }
426
dispc_disable_outputs(void)427 static void dispc_disable_outputs(void)
428 {
429 u32 v, irq_mask = 0;
430 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
431 int i;
432 struct omap_dss_dispc_dev_attr *da;
433 struct omap_hwmod *oh;
434
435 oh = omap_hwmod_lookup("dss_dispc");
436 if (!oh) {
437 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
438 return;
439 }
440
441 if (!oh->dev_attr) {
442 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
443 return;
444 }
445
446 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
447
448 /* store value of LCDENABLE and DIGITENABLE bits */
449 v = omap_hwmod_read(oh, DISPC_CONTROL);
450 lcd_en = v & LCD_EN_MASK;
451 digit_en = v & DIGIT_EN_MASK;
452
453 /* store value of LCDENABLE for LCD2 */
454 if (da->manager_count > 2) {
455 v = omap_hwmod_read(oh, DISPC_CONTROL2);
456 lcd2_en = v & LCD_EN_MASK;
457 }
458
459 /* store value of LCDENABLE for LCD3 */
460 if (da->manager_count > 3) {
461 v = omap_hwmod_read(oh, DISPC_CONTROL3);
462 lcd3_en = v & LCD_EN_MASK;
463 }
464
465 if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
466 return; /* no managers currently enabled */
467
468 /*
469 * If any manager was enabled, we need to disable it before
470 * DSS clocks are disabled or DISPC module is reset
471 */
472 if (lcd_en)
473 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
474
475 if (digit_en) {
476 if (da->has_framedonetv_irq) {
477 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
478 } else {
479 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
480 1 << EVSYNC_ODD_IRQ_SHIFT;
481 }
482 }
483
484 if (lcd2_en)
485 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
486 if (lcd3_en)
487 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
488
489 /*
490 * clear any previous FRAMEDONE, FRAMEDONETV,
491 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
492 */
493 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
494
495 /* disable LCD and TV managers */
496 v = omap_hwmod_read(oh, DISPC_CONTROL);
497 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
498 omap_hwmod_write(v, oh, DISPC_CONTROL);
499
500 /* disable LCD2 manager */
501 if (da->manager_count > 2) {
502 v = omap_hwmod_read(oh, DISPC_CONTROL2);
503 v &= ~LCD_EN_MASK;
504 omap_hwmod_write(v, oh, DISPC_CONTROL2);
505 }
506
507 /* disable LCD3 manager */
508 if (da->manager_count > 3) {
509 v = omap_hwmod_read(oh, DISPC_CONTROL3);
510 v &= ~LCD_EN_MASK;
511 omap_hwmod_write(v, oh, DISPC_CONTROL3);
512 }
513
514 i = 0;
515 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
516 irq_mask) {
517 i++;
518 if (i > FRAMEDONE_IRQ_TIMEOUT) {
519 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
520 break;
521 }
522 mdelay(1);
523 }
524 }
525
omap_dss_reset(struct omap_hwmod * oh)526 int omap_dss_reset(struct omap_hwmod *oh)
527 {
528 struct omap_hwmod_opt_clk *oc;
529 int c = 0;
530 int i, r;
531
532 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
533 pr_err("dss_core: hwmod data doesn't contain reset data\n");
534 return -EINVAL;
535 }
536
537 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
538 if (oc->_clk)
539 clk_prepare_enable(oc->_clk);
540
541 dispc_disable_outputs();
542
543 /* clear SDI registers */
544 if (cpu_is_omap3430()) {
545 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
546 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
547 }
548
549 /*
550 * clear DSS_CONTROL register to switch DSS clock sources to
551 * PRCM clock, if any
552 */
553 omap_hwmod_write(0x0, oh, DSS_CONTROL);
554
555 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
556 & SYSS_RESETDONE_MASK),
557 MAX_MODULE_SOFTRESET_WAIT, c);
558
559 if (c == MAX_MODULE_SOFTRESET_WAIT)
560 pr_warn("dss_core: waiting for reset to finish failed\n");
561 else
562 pr_debug("dss_core: softreset done\n");
563
564 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
565 if (oc->_clk)
566 clk_disable_unprepare(oc->_clk);
567
568 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
569
570 return r;
571 }
572
omapdss_early_init_of(void)573 void __init omapdss_early_init_of(void)
574 {
575
576 }
577
578 static const char * const omapdss_compat_names[] __initconst = {
579 "ti,omap2-dss",
580 "ti,omap3-dss",
581 "ti,omap4-dss",
582 "ti,omap5-dss",
583 "ti,dra7-dss",
584 };
585
omapdss_find_dss_of_node(void)586 struct device_node * __init omapdss_find_dss_of_node(void)
587 {
588 struct device_node *node;
589 int i;
590
591 for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) {
592 node = of_find_compatible_node(NULL, NULL,
593 omapdss_compat_names[i]);
594 if (node)
595 return node;
596 }
597
598 return NULL;
599 }
600
omapdss_init_of(void)601 int __init omapdss_init_of(void)
602 {
603 int r;
604 enum omapdss_version ver;
605 struct device_node *node;
606 struct platform_device *pdev;
607
608 static struct omap_dss_board_info board_data = {
609 .dsi_enable_pads = omap_dsi_enable_pads,
610 .dsi_disable_pads = omap_dsi_disable_pads,
611 .set_min_bus_tput = omap_dss_set_min_bus_tput,
612 };
613
614 /* only create dss helper devices if dss is enabled in the .dts */
615
616 node = omapdss_find_dss_of_node();
617 if (!node)
618 return 0;
619
620 if (!of_device_is_available(node))
621 return 0;
622
623 ver = omap_display_get_version();
624
625 if (ver == OMAPDSS_VER_UNKNOWN) {
626 pr_err("DSS not supported on this SoC\n");
627 return -ENODEV;
628 }
629
630 pdev = of_find_device_by_node(node);
631
632 if (!pdev) {
633 pr_err("Unable to find DSS platform device\n");
634 return -ENODEV;
635 }
636
637 r = of_platform_populate(node, NULL, NULL, &pdev->dev);
638 if (r) {
639 pr_err("Unable to populate DSS submodule devices\n");
640 return r;
641 }
642
643 board_data.version = ver;
644
645 omap_display_device.dev.platform_data = &board_data;
646
647 r = platform_device_register(&omap_display_device);
648 if (r < 0) {
649 pr_err("Unable to register omapdss device\n");
650 return r;
651 }
652
653 /* create DRM device */
654 r = omap_init_drm();
655 if (r < 0) {
656 pr_err("Unable to register omapdrm device\n");
657 return r;
658 }
659
660 /* create vrfb device */
661 r = omap_init_vrfb();
662 if (r < 0) {
663 pr_err("Unable to register omapvrfb device\n");
664 return r;
665 }
666
667 /* create FB device */
668 r = omap_init_fb();
669 if (r < 0) {
670 pr_err("Unable to register omapfb device\n");
671 return r;
672 }
673
674 /* create V4L2 display device */
675 r = omap_init_vout();
676 if (r < 0) {
677 pr_err("Unable to register omap_vout device\n");
678 return r;
679 }
680
681 /* add DSI info for omap4 */
682 node = of_find_node_by_name(NULL, "omap4_padconf_global");
683 if (node)
684 omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
685
686 return 0;
687 }
688