1 /*
2 * Low-Level PCI Support for PC -- Routing of Interrupts
3 *
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
5 */
6
7 #include <linux/types.h>
8 #include <linux/kernel.h>
9 #include <linux/pci.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/dmi.h>
13 #include <linux/io.h>
14 #include <linux/smp.h>
15 #include <asm/io_apic.h>
16 #include <linux/irq.h>
17 #include <linux/acpi.h>
18 #include <asm/pci_x86.h>
19
20 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
21 #define PIRQ_VERSION 0x0100
22
23 static int broken_hp_bios_irq9;
24 static int acer_tm360_irqrouting;
25
26 static struct irq_routing_table *pirq_table;
27
28 static int pirq_enable_irq(struct pci_dev *dev);
29 static void pirq_disable_irq(struct pci_dev *dev);
30
31 /*
32 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
33 * Avoid using: 13, 14 and 15 (FP error and IDE).
34 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
35 */
36 unsigned int pcibios_irq_mask = 0xfff8;
37
38 static int pirq_penalty[16] = {
39 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
40 0, 0, 0, 0, 1000, 100000, 100000, 100000
41 };
42
43 struct irq_router {
44 char *name;
45 u16 vendor, device;
46 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
47 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq,
48 int new);
49 };
50
51 struct irq_router_handler {
52 u16 vendor;
53 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
54 };
55
56 int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq;
57 void (*pcibios_disable_irq)(struct pci_dev *dev) = pirq_disable_irq;
58
59 /*
60 * Check passed address for the PCI IRQ Routing Table signature
61 * and perform checksum verification.
62 */
63
pirq_check_routing_table(u8 * addr)64 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr)
65 {
66 struct irq_routing_table *rt;
67 int i;
68 u8 sum;
69
70 rt = (struct irq_routing_table *) addr;
71 if (rt->signature != PIRQ_SIGNATURE ||
72 rt->version != PIRQ_VERSION ||
73 rt->size % 16 ||
74 rt->size < sizeof(struct irq_routing_table))
75 return NULL;
76 sum = 0;
77 for (i = 0; i < rt->size; i++)
78 sum += addr[i];
79 if (!sum) {
80 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n",
81 rt);
82 return rt;
83 }
84 return NULL;
85 }
86
87
88
89 /*
90 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
91 */
92
pirq_find_routing_table(void)93 static struct irq_routing_table * __init pirq_find_routing_table(void)
94 {
95 u8 *addr;
96 struct irq_routing_table *rt;
97
98 if (pirq_table_addr) {
99 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr));
100 if (rt)
101 return rt;
102 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
103 }
104 for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
105 rt = pirq_check_routing_table(addr);
106 if (rt)
107 return rt;
108 }
109 return NULL;
110 }
111
112 /*
113 * If we have a IRQ routing table, use it to search for peer host
114 * bridges. It's a gross hack, but since there are no other known
115 * ways how to get a list of buses, we have to go this way.
116 */
117
pirq_peer_trick(void)118 static void __init pirq_peer_trick(void)
119 {
120 struct irq_routing_table *rt = pirq_table;
121 u8 busmap[256];
122 int i;
123 struct irq_info *e;
124
125 memset(busmap, 0, sizeof(busmap));
126 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
127 e = &rt->slots[i];
128 #ifdef DEBUG
129 {
130 int j;
131 DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
132 for (j = 0; j < 4; j++)
133 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
134 DBG("\n");
135 }
136 #endif
137 busmap[e->bus] = 1;
138 }
139 for (i = 1; i < 256; i++) {
140 if (!busmap[i] || pci_find_bus(0, i))
141 continue;
142 pcibios_scan_root(i);
143 }
144 pcibios_last_bus = -1;
145 }
146
147 /*
148 * Code for querying and setting of IRQ routes on various interrupt routers.
149 * PIC Edge/Level Control Registers (ELCR) 0x4d0 & 0x4d1.
150 */
151
elcr_set_level_irq(unsigned int irq)152 void elcr_set_level_irq(unsigned int irq)
153 {
154 unsigned char mask = 1 << (irq & 7);
155 unsigned int port = 0x4d0 + (irq >> 3);
156 unsigned char val;
157 static u16 elcr_irq_mask;
158
159 if (irq >= 16 || (1 << irq) & elcr_irq_mask)
160 return;
161
162 elcr_irq_mask |= (1 << irq);
163 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq);
164 val = inb(port);
165 if (!(val & mask)) {
166 DBG(KERN_DEBUG " -> edge");
167 outb(val | mask, port);
168 }
169 }
170
171 /*
172 * Common IRQ routing practice: nibbles in config space,
173 * offset by some magic constant.
174 */
read_config_nybble(struct pci_dev * router,unsigned offset,unsigned nr)175 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
176 {
177 u8 x;
178 unsigned reg = offset + (nr >> 1);
179
180 pci_read_config_byte(router, reg, &x);
181 return (nr & 1) ? (x >> 4) : (x & 0xf);
182 }
183
write_config_nybble(struct pci_dev * router,unsigned offset,unsigned nr,unsigned int val)184 static void write_config_nybble(struct pci_dev *router, unsigned offset,
185 unsigned nr, unsigned int val)
186 {
187 u8 x;
188 unsigned reg = offset + (nr >> 1);
189
190 pci_read_config_byte(router, reg, &x);
191 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
192 pci_write_config_byte(router, reg, x);
193 }
194
195 /*
196 * ALI pirq entries are damn ugly, and completely undocumented.
197 * This has been figured out from pirq tables, and it's not a pretty
198 * picture.
199 */
pirq_ali_get(struct pci_dev * router,struct pci_dev * dev,int pirq)200 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
201 {
202 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
203
204 WARN_ON_ONCE(pirq > 16);
205 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
206 }
207
pirq_ali_set(struct pci_dev * router,struct pci_dev * dev,int pirq,int irq)208 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
209 {
210 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
211 unsigned int val = irqmap[irq];
212
213 WARN_ON_ONCE(pirq > 16);
214 if (val) {
215 write_config_nybble(router, 0x48, pirq-1, val);
216 return 1;
217 }
218 return 0;
219 }
220
221 /*
222 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
223 * just a pointer to the config space.
224 */
pirq_piix_get(struct pci_dev * router,struct pci_dev * dev,int pirq)225 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
226 {
227 u8 x;
228
229 pci_read_config_byte(router, pirq, &x);
230 return (x < 16) ? x : 0;
231 }
232
pirq_piix_set(struct pci_dev * router,struct pci_dev * dev,int pirq,int irq)233 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
234 {
235 pci_write_config_byte(router, pirq, irq);
236 return 1;
237 }
238
239 /*
240 * The VIA pirq rules are nibble-based, like ALI,
241 * but without the ugly irq number munging.
242 * However, PIRQD is in the upper instead of lower 4 bits.
243 */
pirq_via_get(struct pci_dev * router,struct pci_dev * dev,int pirq)244 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
245 {
246 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
247 }
248
pirq_via_set(struct pci_dev * router,struct pci_dev * dev,int pirq,int irq)249 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
250 {
251 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
252 return 1;
253 }
254
255 /*
256 * The VIA pirq rules are nibble-based, like ALI,
257 * but without the ugly irq number munging.
258 * However, for 82C586, nibble map is different .
259 */
pirq_via586_get(struct pci_dev * router,struct pci_dev * dev,int pirq)260 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
261 {
262 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
263
264 WARN_ON_ONCE(pirq > 5);
265 return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
266 }
267
pirq_via586_set(struct pci_dev * router,struct pci_dev * dev,int pirq,int irq)268 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
269 {
270 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
271
272 WARN_ON_ONCE(pirq > 5);
273 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
274 return 1;
275 }
276
277 /*
278 * ITE 8330G pirq rules are nibble-based
279 * FIXME: pirqmap may be { 1, 0, 3, 2 },
280 * 2+3 are both mapped to irq 9 on my system
281 */
pirq_ite_get(struct pci_dev * router,struct pci_dev * dev,int pirq)282 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
283 {
284 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
285
286 WARN_ON_ONCE(pirq > 4);
287 return read_config_nybble(router, 0x43, pirqmap[pirq-1]);
288 }
289
pirq_ite_set(struct pci_dev * router,struct pci_dev * dev,int pirq,int irq)290 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
291 {
292 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
293
294 WARN_ON_ONCE(pirq > 4);
295 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
296 return 1;
297 }
298
299 /*
300 * OPTI: high four bits are nibble pointer..
301 * I wonder what the low bits do?
302 */
pirq_opti_get(struct pci_dev * router,struct pci_dev * dev,int pirq)303 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
304 {
305 return read_config_nybble(router, 0xb8, pirq >> 4);
306 }
307
pirq_opti_set(struct pci_dev * router,struct pci_dev * dev,int pirq,int irq)308 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
309 {
310 write_config_nybble(router, 0xb8, pirq >> 4, irq);
311 return 1;
312 }
313
314 /*
315 * Cyrix: nibble offset 0x5C
316 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
317 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
318 */
pirq_cyrix_get(struct pci_dev * router,struct pci_dev * dev,int pirq)319 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
320 {
321 return read_config_nybble(router, 0x5C, (pirq-1)^1);
322 }
323
pirq_cyrix_set(struct pci_dev * router,struct pci_dev * dev,int pirq,int irq)324 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
325 {
326 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
327 return 1;
328 }
329
330 /*
331 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
332 * We have to deal with the following issues here:
333 * - vendors have different ideas about the meaning of link values
334 * - some onboard devices (integrated in the chipset) have special
335 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
336 * - different revision of the router have a different layout for
337 * the routing registers, particularly for the onchip devices
338 *
339 * For all routing registers the common thing is we have one byte
340 * per routeable link which is defined as:
341 * bit 7 IRQ mapping enabled (0) or disabled (1)
342 * bits [6:4] reserved (sometimes used for onchip devices)
343 * bits [3:0] IRQ to map to
344 * allowed: 3-7, 9-12, 14-15
345 * reserved: 0, 1, 2, 8, 13
346 *
347 * The config-space registers located at 0x41/0x42/0x43/0x44 are
348 * always used to route the normal PCI INT A/B/C/D respectively.
349 * Apparently there are systems implementing PCI routing table using
350 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
351 * We try our best to handle both link mappings.
352 *
353 * Currently (2003-05-21) it appears most SiS chipsets follow the
354 * definition of routing registers from the SiS-5595 southbridge.
355 * According to the SiS 5595 datasheets the revision id's of the
356 * router (ISA-bridge) should be 0x01 or 0xb0.
357 *
358 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
359 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
360 * They seem to work with the current routing code. However there is
361 * some concern because of the two USB-OHCI HCs (original SiS 5595
362 * had only one). YMMV.
363 *
364 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
365 *
366 * 0x61: IDEIRQ:
367 * bits [6:5] must be written 01
368 * bit 4 channel-select primary (0), secondary (1)
369 *
370 * 0x62: USBIRQ:
371 * bit 6 OHCI function disabled (0), enabled (1)
372 *
373 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
374 *
375 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
376 *
377 * We support USBIRQ (in addition to INTA-INTD) and keep the
378 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
379 *
380 * Currently the only reported exception is the new SiS 65x chipset
381 * which includes the SiS 69x southbridge. Here we have the 85C503
382 * router revision 0x04 and there are changes in the register layout
383 * mostly related to the different USB HCs with USB 2.0 support.
384 *
385 * Onchip routing for router rev-id 0x04 (try-and-error observation)
386 *
387 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
388 * bit 6-4 are probably unused, not like 5595
389 */
390
391 #define PIRQ_SIS_IRQ_MASK 0x0f
392 #define PIRQ_SIS_IRQ_DISABLE 0x80
393 #define PIRQ_SIS_USB_ENABLE 0x40
394
pirq_sis_get(struct pci_dev * router,struct pci_dev * dev,int pirq)395 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
396 {
397 u8 x;
398 int reg;
399
400 reg = pirq;
401 if (reg >= 0x01 && reg <= 0x04)
402 reg += 0x40;
403 pci_read_config_byte(router, reg, &x);
404 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
405 }
406
pirq_sis_set(struct pci_dev * router,struct pci_dev * dev,int pirq,int irq)407 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
408 {
409 u8 x;
410 int reg;
411
412 reg = pirq;
413 if (reg >= 0x01 && reg <= 0x04)
414 reg += 0x40;
415 pci_read_config_byte(router, reg, &x);
416 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
417 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
418 pci_write_config_byte(router, reg, x);
419 return 1;
420 }
421
422
423 /*
424 * VLSI: nibble offset 0x74 - educated guess due to routing table and
425 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
426 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
427 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
428 * for the busbridge to the docking station.
429 */
430
pirq_vlsi_get(struct pci_dev * router,struct pci_dev * dev,int pirq)431 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
432 {
433 WARN_ON_ONCE(pirq >= 9);
434 if (pirq > 8) {
435 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
436 return 0;
437 }
438 return read_config_nybble(router, 0x74, pirq-1);
439 }
440
pirq_vlsi_set(struct pci_dev * router,struct pci_dev * dev,int pirq,int irq)441 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
442 {
443 WARN_ON_ONCE(pirq >= 9);
444 if (pirq > 8) {
445 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
446 return 0;
447 }
448 write_config_nybble(router, 0x74, pirq-1, irq);
449 return 1;
450 }
451
452 /*
453 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
454 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
455 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
456 * register is a straight binary coding of desired PIC IRQ (low nibble).
457 *
458 * The 'link' value in the PIRQ table is already in the correct format
459 * for the Index register. There are some special index values:
460 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
461 * and 0x03 for SMBus.
462 */
pirq_serverworks_get(struct pci_dev * router,struct pci_dev * dev,int pirq)463 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
464 {
465 outb(pirq, 0xc00);
466 return inb(0xc01) & 0xf;
467 }
468
pirq_serverworks_set(struct pci_dev * router,struct pci_dev * dev,int pirq,int irq)469 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev,
470 int pirq, int irq)
471 {
472 outb(pirq, 0xc00);
473 outb(irq, 0xc01);
474 return 1;
475 }
476
477 /* Support for AMD756 PCI IRQ Routing
478 * Jhon H. Caicedo <jhcaiced@osso.org.co>
479 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
480 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
481 * The AMD756 pirq rules are nibble-based
482 * offset 0x56 0-3 PIRQA 4-7 PIRQB
483 * offset 0x57 0-3 PIRQC 4-7 PIRQD
484 */
pirq_amd756_get(struct pci_dev * router,struct pci_dev * dev,int pirq)485 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
486 {
487 u8 irq;
488 irq = 0;
489 if (pirq <= 4)
490 irq = read_config_nybble(router, 0x56, pirq - 1);
491 dev_info(&dev->dev,
492 "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n",
493 dev->vendor, dev->device, pirq, irq);
494 return irq;
495 }
496
pirq_amd756_set(struct pci_dev * router,struct pci_dev * dev,int pirq,int irq)497 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
498 {
499 dev_info(&dev->dev,
500 "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n",
501 dev->vendor, dev->device, pirq, irq);
502 if (pirq <= 4)
503 write_config_nybble(router, 0x56, pirq - 1, irq);
504 return 1;
505 }
506
507 /*
508 * PicoPower PT86C523
509 */
pirq_pico_get(struct pci_dev * router,struct pci_dev * dev,int pirq)510 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
511 {
512 outb(0x10 + ((pirq - 1) >> 1), 0x24);
513 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf);
514 }
515
pirq_pico_set(struct pci_dev * router,struct pci_dev * dev,int pirq,int irq)516 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
517 int irq)
518 {
519 unsigned int x;
520 outb(0x10 + ((pirq - 1) >> 1), 0x24);
521 x = inb(0x26);
522 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq));
523 outb(x, 0x26);
524 return 1;
525 }
526
527 #ifdef CONFIG_PCI_BIOS
528
pirq_bios_set(struct pci_dev * router,struct pci_dev * dev,int pirq,int irq)529 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
530 {
531 struct pci_dev *bridge;
532 int pin = pci_get_interrupt_pin(dev, &bridge);
533 return pcibios_set_irq_routing(bridge, pin - 1, irq);
534 }
535
536 #endif
537
intel_router_probe(struct irq_router * r,struct pci_dev * router,u16 device)538 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
539 {
540 static struct pci_device_id __initdata pirq_440gx[] = {
541 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
542 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
543 { },
544 };
545
546 /* 440GX has a proprietary PIRQ router -- don't use it */
547 if (pci_dev_present(pirq_440gx))
548 return 0;
549
550 switch (device) {
551 case PCI_DEVICE_ID_INTEL_82371FB_0:
552 case PCI_DEVICE_ID_INTEL_82371SB_0:
553 case PCI_DEVICE_ID_INTEL_82371AB_0:
554 case PCI_DEVICE_ID_INTEL_82371MX:
555 case PCI_DEVICE_ID_INTEL_82443MX_0:
556 case PCI_DEVICE_ID_INTEL_82801AA_0:
557 case PCI_DEVICE_ID_INTEL_82801AB_0:
558 case PCI_DEVICE_ID_INTEL_82801BA_0:
559 case PCI_DEVICE_ID_INTEL_82801BA_10:
560 case PCI_DEVICE_ID_INTEL_82801CA_0:
561 case PCI_DEVICE_ID_INTEL_82801CA_12:
562 case PCI_DEVICE_ID_INTEL_82801DB_0:
563 case PCI_DEVICE_ID_INTEL_82801E_0:
564 case PCI_DEVICE_ID_INTEL_82801EB_0:
565 case PCI_DEVICE_ID_INTEL_ESB_1:
566 case PCI_DEVICE_ID_INTEL_ICH6_0:
567 case PCI_DEVICE_ID_INTEL_ICH6_1:
568 case PCI_DEVICE_ID_INTEL_ICH7_0:
569 case PCI_DEVICE_ID_INTEL_ICH7_1:
570 case PCI_DEVICE_ID_INTEL_ICH7_30:
571 case PCI_DEVICE_ID_INTEL_ICH7_31:
572 case PCI_DEVICE_ID_INTEL_TGP_LPC:
573 case PCI_DEVICE_ID_INTEL_ESB2_0:
574 case PCI_DEVICE_ID_INTEL_ICH8_0:
575 case PCI_DEVICE_ID_INTEL_ICH8_1:
576 case PCI_DEVICE_ID_INTEL_ICH8_2:
577 case PCI_DEVICE_ID_INTEL_ICH8_3:
578 case PCI_DEVICE_ID_INTEL_ICH8_4:
579 case PCI_DEVICE_ID_INTEL_ICH9_0:
580 case PCI_DEVICE_ID_INTEL_ICH9_1:
581 case PCI_DEVICE_ID_INTEL_ICH9_2:
582 case PCI_DEVICE_ID_INTEL_ICH9_3:
583 case PCI_DEVICE_ID_INTEL_ICH9_4:
584 case PCI_DEVICE_ID_INTEL_ICH9_5:
585 case PCI_DEVICE_ID_INTEL_EP80579_0:
586 case PCI_DEVICE_ID_INTEL_ICH10_0:
587 case PCI_DEVICE_ID_INTEL_ICH10_1:
588 case PCI_DEVICE_ID_INTEL_ICH10_2:
589 case PCI_DEVICE_ID_INTEL_ICH10_3:
590 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0:
591 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1:
592 r->name = "PIIX/ICH";
593 r->get = pirq_piix_get;
594 r->set = pirq_piix_set;
595 return 1;
596 }
597
598 if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN &&
599 device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX)
600 || (device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
601 device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX)
602 || (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN &&
603 device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX)
604 || (device >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
605 device <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) {
606 r->name = "PIIX/ICH";
607 r->get = pirq_piix_get;
608 r->set = pirq_piix_set;
609 return 1;
610 }
611
612 return 0;
613 }
614
via_router_probe(struct irq_router * r,struct pci_dev * router,u16 device)615 static __init int via_router_probe(struct irq_router *r,
616 struct pci_dev *router, u16 device)
617 {
618 /* FIXME: We should move some of the quirk fixup stuff here */
619
620 /*
621 * workarounds for some buggy BIOSes
622 */
623 if (device == PCI_DEVICE_ID_VIA_82C586_0) {
624 switch (router->device) {
625 case PCI_DEVICE_ID_VIA_82C686:
626 /*
627 * Asus k7m bios wrongly reports 82C686A
628 * as 586-compatible
629 */
630 device = PCI_DEVICE_ID_VIA_82C686;
631 break;
632 case PCI_DEVICE_ID_VIA_8235:
633 /**
634 * Asus a7v-x bios wrongly reports 8235
635 * as 586-compatible
636 */
637 device = PCI_DEVICE_ID_VIA_8235;
638 break;
639 case PCI_DEVICE_ID_VIA_8237:
640 /**
641 * Asus a7v600 bios wrongly reports 8237
642 * as 586-compatible
643 */
644 device = PCI_DEVICE_ID_VIA_8237;
645 break;
646 }
647 }
648
649 switch (device) {
650 case PCI_DEVICE_ID_VIA_82C586_0:
651 r->name = "VIA";
652 r->get = pirq_via586_get;
653 r->set = pirq_via586_set;
654 return 1;
655 case PCI_DEVICE_ID_VIA_82C596:
656 case PCI_DEVICE_ID_VIA_82C686:
657 case PCI_DEVICE_ID_VIA_8231:
658 case PCI_DEVICE_ID_VIA_8233A:
659 case PCI_DEVICE_ID_VIA_8235:
660 case PCI_DEVICE_ID_VIA_8237:
661 /* FIXME: add new ones for 8233/5 */
662 r->name = "VIA";
663 r->get = pirq_via_get;
664 r->set = pirq_via_set;
665 return 1;
666 }
667 return 0;
668 }
669
vlsi_router_probe(struct irq_router * r,struct pci_dev * router,u16 device)670 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
671 {
672 switch (device) {
673 case PCI_DEVICE_ID_VLSI_82C534:
674 r->name = "VLSI 82C534";
675 r->get = pirq_vlsi_get;
676 r->set = pirq_vlsi_set;
677 return 1;
678 }
679 return 0;
680 }
681
682
serverworks_router_probe(struct irq_router * r,struct pci_dev * router,u16 device)683 static __init int serverworks_router_probe(struct irq_router *r,
684 struct pci_dev *router, u16 device)
685 {
686 switch (device) {
687 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
688 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
689 r->name = "ServerWorks";
690 r->get = pirq_serverworks_get;
691 r->set = pirq_serverworks_set;
692 return 1;
693 }
694 return 0;
695 }
696
sis_router_probe(struct irq_router * r,struct pci_dev * router,u16 device)697 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
698 {
699 if (device != PCI_DEVICE_ID_SI_503)
700 return 0;
701
702 r->name = "SIS";
703 r->get = pirq_sis_get;
704 r->set = pirq_sis_set;
705 return 1;
706 }
707
cyrix_router_probe(struct irq_router * r,struct pci_dev * router,u16 device)708 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
709 {
710 switch (device) {
711 case PCI_DEVICE_ID_CYRIX_5520:
712 r->name = "NatSemi";
713 r->get = pirq_cyrix_get;
714 r->set = pirq_cyrix_set;
715 return 1;
716 }
717 return 0;
718 }
719
opti_router_probe(struct irq_router * r,struct pci_dev * router,u16 device)720 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
721 {
722 switch (device) {
723 case PCI_DEVICE_ID_OPTI_82C700:
724 r->name = "OPTI";
725 r->get = pirq_opti_get;
726 r->set = pirq_opti_set;
727 return 1;
728 }
729 return 0;
730 }
731
ite_router_probe(struct irq_router * r,struct pci_dev * router,u16 device)732 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
733 {
734 switch (device) {
735 case PCI_DEVICE_ID_ITE_IT8330G_0:
736 r->name = "ITE";
737 r->get = pirq_ite_get;
738 r->set = pirq_ite_set;
739 return 1;
740 }
741 return 0;
742 }
743
ali_router_probe(struct irq_router * r,struct pci_dev * router,u16 device)744 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
745 {
746 switch (device) {
747 case PCI_DEVICE_ID_AL_M1533:
748 case PCI_DEVICE_ID_AL_M1563:
749 r->name = "ALI";
750 r->get = pirq_ali_get;
751 r->set = pirq_ali_set;
752 return 1;
753 }
754 return 0;
755 }
756
amd_router_probe(struct irq_router * r,struct pci_dev * router,u16 device)757 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
758 {
759 switch (device) {
760 case PCI_DEVICE_ID_AMD_VIPER_740B:
761 r->name = "AMD756";
762 break;
763 case PCI_DEVICE_ID_AMD_VIPER_7413:
764 r->name = "AMD766";
765 break;
766 case PCI_DEVICE_ID_AMD_VIPER_7443:
767 r->name = "AMD768";
768 break;
769 default:
770 return 0;
771 }
772 r->get = pirq_amd756_get;
773 r->set = pirq_amd756_set;
774 return 1;
775 }
776
pico_router_probe(struct irq_router * r,struct pci_dev * router,u16 device)777 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
778 {
779 switch (device) {
780 case PCI_DEVICE_ID_PICOPOWER_PT86C523:
781 r->name = "PicoPower PT86C523";
782 r->get = pirq_pico_get;
783 r->set = pirq_pico_set;
784 return 1;
785
786 case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP:
787 r->name = "PicoPower PT86C523 rev. BB+";
788 r->get = pirq_pico_get;
789 r->set = pirq_pico_set;
790 return 1;
791 }
792 return 0;
793 }
794
795 static __initdata struct irq_router_handler pirq_routers[] = {
796 { PCI_VENDOR_ID_INTEL, intel_router_probe },
797 { PCI_VENDOR_ID_AL, ali_router_probe },
798 { PCI_VENDOR_ID_ITE, ite_router_probe },
799 { PCI_VENDOR_ID_VIA, via_router_probe },
800 { PCI_VENDOR_ID_OPTI, opti_router_probe },
801 { PCI_VENDOR_ID_SI, sis_router_probe },
802 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
803 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
804 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
805 { PCI_VENDOR_ID_AMD, amd_router_probe },
806 { PCI_VENDOR_ID_PICOPOWER, pico_router_probe },
807 /* Someone with docs needs to add the ATI Radeon IGP */
808 { 0, NULL }
809 };
810 static struct irq_router pirq_router;
811 static struct pci_dev *pirq_router_dev;
812
813
814 /*
815 * FIXME: should we have an option to say "generic for
816 * chipset" ?
817 */
818
pirq_find_router(struct irq_router * r)819 static void __init pirq_find_router(struct irq_router *r)
820 {
821 struct irq_routing_table *rt = pirq_table;
822 struct irq_router_handler *h;
823
824 #ifdef CONFIG_PCI_BIOS
825 if (!rt->signature) {
826 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
827 r->set = pirq_bios_set;
828 r->name = "BIOS";
829 return;
830 }
831 #endif
832
833 /* Default unless a driver reloads it */
834 r->name = "default";
835 r->get = NULL;
836 r->set = NULL;
837
838 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n",
839 rt->rtr_vendor, rt->rtr_device);
840
841 pirq_router_dev = pci_get_bus_and_slot(rt->rtr_bus, rt->rtr_devfn);
842 if (!pirq_router_dev) {
843 DBG(KERN_DEBUG "PCI: Interrupt router not found at "
844 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
845 return;
846 }
847
848 for (h = pirq_routers; h->vendor; h++) {
849 /* First look for a router match */
850 if (rt->rtr_vendor == h->vendor &&
851 h->probe(r, pirq_router_dev, rt->rtr_device))
852 break;
853 /* Fall back to a device match */
854 if (pirq_router_dev->vendor == h->vendor &&
855 h->probe(r, pirq_router_dev, pirq_router_dev->device))
856 break;
857 }
858 dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n",
859 pirq_router.name,
860 pirq_router_dev->vendor, pirq_router_dev->device);
861
862 /* The device remains referenced for the kernel lifetime */
863 }
864
pirq_get_info(struct pci_dev * dev)865 static struct irq_info *pirq_get_info(struct pci_dev *dev)
866 {
867 struct irq_routing_table *rt = pirq_table;
868 int entries = (rt->size - sizeof(struct irq_routing_table)) /
869 sizeof(struct irq_info);
870 struct irq_info *info;
871
872 for (info = rt->slots; entries--; info++)
873 if (info->bus == dev->bus->number &&
874 PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
875 return info;
876 return NULL;
877 }
878
pcibios_lookup_irq(struct pci_dev * dev,int assign)879 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
880 {
881 u8 pin;
882 struct irq_info *info;
883 int i, pirq, newirq;
884 int irq = 0;
885 u32 mask;
886 struct irq_router *r = &pirq_router;
887 struct pci_dev *dev2 = NULL;
888 char *msg = NULL;
889
890 /* Find IRQ pin */
891 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
892 if (!pin) {
893 dev_dbg(&dev->dev, "no interrupt pin\n");
894 return 0;
895 }
896
897 if (io_apic_assign_pci_irqs)
898 return 0;
899
900 /* Find IRQ routing entry */
901
902 if (!pirq_table)
903 return 0;
904
905 info = pirq_get_info(dev);
906 if (!info) {
907 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n",
908 'A' + pin - 1);
909 return 0;
910 }
911 pirq = info->irq[pin - 1].link;
912 mask = info->irq[pin - 1].bitmap;
913 if (!pirq) {
914 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin - 1);
915 return 0;
916 }
917 dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x",
918 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs);
919 mask &= pcibios_irq_mask;
920
921 /* Work around broken HP Pavilion Notebooks which assign USB to
922 IRQ 9 even though it is actually wired to IRQ 11 */
923
924 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
925 dev->irq = 11;
926 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
927 r->set(pirq_router_dev, dev, pirq, 11);
928 }
929
930 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
931 if (acer_tm360_irqrouting && dev->irq == 11 &&
932 dev->vendor == PCI_VENDOR_ID_O2) {
933 pirq = 0x68;
934 mask = 0x400;
935 dev->irq = r->get(pirq_router_dev, dev, pirq);
936 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
937 }
938
939 /*
940 * Find the best IRQ to assign: use the one
941 * reported by the device if possible.
942 */
943 newirq = dev->irq;
944 if (newirq && !((1 << newirq) & mask)) {
945 if (pci_probe & PCI_USE_PIRQ_MASK)
946 newirq = 0;
947 else
948 dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask "
949 "%#x; try pci=usepirqmask\n", newirq, mask);
950 }
951 if (!newirq && assign) {
952 for (i = 0; i < 16; i++) {
953 if (!(mask & (1 << i)))
954 continue;
955 if (pirq_penalty[i] < pirq_penalty[newirq] &&
956 can_request_irq(i, IRQF_SHARED))
957 newirq = i;
958 }
959 }
960 dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin - 1, newirq);
961
962 /* Check if it is hardcoded */
963 if ((pirq & 0xf0) == 0xf0) {
964 irq = pirq & 0xf;
965 msg = "hardcoded";
966 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
967 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) {
968 msg = "found";
969 elcr_set_level_irq(irq);
970 } else if (newirq && r->set &&
971 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
972 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
973 elcr_set_level_irq(newirq);
974 msg = "assigned";
975 irq = newirq;
976 }
977 }
978
979 if (!irq) {
980 if (newirq && mask == (1 << newirq)) {
981 msg = "guessed";
982 irq = newirq;
983 } else {
984 dev_dbg(&dev->dev, "can't route interrupt\n");
985 return 0;
986 }
987 }
988 dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin - 1, irq);
989
990 /* Update IRQ for all devices with the same pirq value */
991 for_each_pci_dev(dev2) {
992 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
993 if (!pin)
994 continue;
995
996 info = pirq_get_info(dev2);
997 if (!info)
998 continue;
999 if (info->irq[pin - 1].link == pirq) {
1000 /*
1001 * We refuse to override the dev->irq
1002 * information. Give a warning!
1003 */
1004 if (dev2->irq && dev2->irq != irq && \
1005 (!(pci_probe & PCI_USE_PIRQ_MASK) || \
1006 ((1 << dev2->irq) & mask))) {
1007 #ifndef CONFIG_PCI_MSI
1008 dev_info(&dev2->dev, "IRQ routing conflict: "
1009 "have IRQ %d, want IRQ %d\n",
1010 dev2->irq, irq);
1011 #endif
1012 continue;
1013 }
1014 dev2->irq = irq;
1015 pirq_penalty[irq]++;
1016 if (dev != dev2)
1017 dev_info(&dev->dev, "sharing IRQ %d with %s\n",
1018 irq, pci_name(dev2));
1019 }
1020 }
1021 return 1;
1022 }
1023
pcibios_fixup_irqs(void)1024 void __init pcibios_fixup_irqs(void)
1025 {
1026 struct pci_dev *dev = NULL;
1027 u8 pin;
1028
1029 DBG(KERN_DEBUG "PCI: IRQ fixup\n");
1030 for_each_pci_dev(dev) {
1031 /*
1032 * If the BIOS has set an out of range IRQ number, just
1033 * ignore it. Also keep track of which IRQ's are
1034 * already in use.
1035 */
1036 if (dev->irq >= 16) {
1037 dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq);
1038 dev->irq = 0;
1039 }
1040 /*
1041 * If the IRQ is already assigned to a PCI device,
1042 * ignore its ISA use penalty
1043 */
1044 if (pirq_penalty[dev->irq] >= 100 &&
1045 pirq_penalty[dev->irq] < 100000)
1046 pirq_penalty[dev->irq] = 0;
1047 pirq_penalty[dev->irq]++;
1048 }
1049
1050 if (io_apic_assign_pci_irqs)
1051 return;
1052
1053 dev = NULL;
1054 for_each_pci_dev(dev) {
1055 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1056 if (!pin)
1057 continue;
1058
1059 /*
1060 * Still no IRQ? Try to lookup one...
1061 */
1062 if (!dev->irq)
1063 pcibios_lookup_irq(dev, 0);
1064 }
1065 }
1066
1067 /*
1068 * Work around broken HP Pavilion Notebooks which assign USB to
1069 * IRQ 9 even though it is actually wired to IRQ 11
1070 */
fix_broken_hp_bios_irq9(const struct dmi_system_id * d)1071 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d)
1072 {
1073 if (!broken_hp_bios_irq9) {
1074 broken_hp_bios_irq9 = 1;
1075 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1076 d->ident);
1077 }
1078 return 0;
1079 }
1080
1081 /*
1082 * Work around broken Acer TravelMate 360 Notebooks which assign
1083 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
1084 */
fix_acer_tm360_irqrouting(const struct dmi_system_id * d)1085 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d)
1086 {
1087 if (!acer_tm360_irqrouting) {
1088 acer_tm360_irqrouting = 1;
1089 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1090 d->ident);
1091 }
1092 return 0;
1093 }
1094
1095 static struct dmi_system_id __initdata pciirq_dmi_table[] = {
1096 {
1097 .callback = fix_broken_hp_bios_irq9,
1098 .ident = "HP Pavilion N5400 Series Laptop",
1099 .matches = {
1100 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1101 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
1102 DMI_MATCH(DMI_PRODUCT_VERSION,
1103 "HP Pavilion Notebook Model GE"),
1104 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
1105 },
1106 },
1107 {
1108 .callback = fix_acer_tm360_irqrouting,
1109 .ident = "Acer TravelMate 36x Laptop",
1110 .matches = {
1111 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1112 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
1113 },
1114 },
1115 { }
1116 };
1117
pcibios_irq_init(void)1118 void __init pcibios_irq_init(void)
1119 {
1120 struct irq_routing_table *rtable = NULL;
1121
1122 DBG(KERN_DEBUG "PCI: IRQ init\n");
1123
1124 if (raw_pci_ops == NULL)
1125 return;
1126
1127 dmi_check_system(pciirq_dmi_table);
1128
1129 pirq_table = pirq_find_routing_table();
1130
1131 #ifdef CONFIG_PCI_BIOS
1132 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) {
1133 pirq_table = pcibios_get_irq_routing_table();
1134 rtable = pirq_table;
1135 }
1136 #endif
1137 if (pirq_table) {
1138 pirq_peer_trick();
1139 pirq_find_router(&pirq_router);
1140 if (pirq_table->exclusive_irqs) {
1141 int i;
1142 for (i = 0; i < 16; i++)
1143 if (!(pirq_table->exclusive_irqs & (1 << i)))
1144 pirq_penalty[i] += 100;
1145 }
1146 /*
1147 * If we're using the I/O APIC, avoid using the PCI IRQ
1148 * routing table
1149 */
1150 if (io_apic_assign_pci_irqs) {
1151 kfree(rtable);
1152 pirq_table = NULL;
1153 }
1154 }
1155
1156 x86_init.pci.fixup_irqs();
1157
1158 if (io_apic_assign_pci_irqs && pci_routeirq) {
1159 struct pci_dev *dev = NULL;
1160 /*
1161 * PCI IRQ routing is set up by pci_enable_device(), but we
1162 * also do it here in case there are still broken drivers that
1163 * don't use pci_enable_device().
1164 */
1165 printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
1166 for_each_pci_dev(dev)
1167 pirq_enable_irq(dev);
1168 }
1169 }
1170
pirq_penalize_isa_irq(int irq,int active)1171 static void pirq_penalize_isa_irq(int irq, int active)
1172 {
1173 /*
1174 * If any ISAPnP device reports an IRQ in its list of possible
1175 * IRQ's, we try to avoid assigning it to PCI devices.
1176 */
1177 if (irq < 16) {
1178 if (active)
1179 pirq_penalty[irq] += 1000;
1180 else
1181 pirq_penalty[irq] += 100;
1182 }
1183 }
1184
pcibios_penalize_isa_irq(int irq,int active)1185 void pcibios_penalize_isa_irq(int irq, int active)
1186 {
1187 #ifdef CONFIG_ACPI
1188 if (!acpi_noirq)
1189 acpi_penalize_isa_irq(irq, active);
1190 else
1191 #endif
1192 pirq_penalize_isa_irq(irq, active);
1193 }
1194
pirq_enable_irq(struct pci_dev * dev)1195 static int pirq_enable_irq(struct pci_dev *dev)
1196 {
1197 u8 pin = 0;
1198
1199 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1200 if (pin && !pcibios_lookup_irq(dev, 1)) {
1201 char *msg = "";
1202
1203 if (!io_apic_assign_pci_irqs && dev->irq)
1204 return 0;
1205
1206 if (io_apic_assign_pci_irqs) {
1207 #ifdef CONFIG_X86_IO_APIC
1208 struct pci_dev *temp_dev;
1209 int irq;
1210
1211 if (dev->irq_managed && dev->irq > 0)
1212 return 0;
1213
1214 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number,
1215 PCI_SLOT(dev->devfn), pin - 1);
1216 /*
1217 * Busses behind bridges are typically not listed in the MP-table.
1218 * In this case we have to look up the IRQ based on the parent bus,
1219 * parent slot, and pin number. The SMP code detects such bridged
1220 * busses itself so we should get into this branch reliably.
1221 */
1222 temp_dev = dev;
1223 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1224 struct pci_dev *bridge = dev->bus->self;
1225
1226 pin = pci_swizzle_interrupt_pin(dev, pin);
1227 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1228 PCI_SLOT(bridge->devfn),
1229 pin - 1);
1230 if (irq >= 0)
1231 dev_warn(&dev->dev, "using bridge %s "
1232 "INT %c to get IRQ %d\n",
1233 pci_name(bridge), 'A' + pin - 1,
1234 irq);
1235 dev = bridge;
1236 }
1237 dev = temp_dev;
1238 if (irq >= 0) {
1239 dev->irq_managed = 1;
1240 dev->irq = irq;
1241 dev_info(&dev->dev, "PCI->APIC IRQ transform: "
1242 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq);
1243 return 0;
1244 } else
1245 msg = "; probably buggy MP table";
1246 #endif
1247 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1248 msg = "";
1249 else
1250 msg = "; please try using pci=biosirq";
1251
1252 /*
1253 * With IDE legacy devices the IRQ lookup failure is not
1254 * a problem..
1255 */
1256 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE &&
1257 !(dev->class & 0x5))
1258 return 0;
1259
1260 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n",
1261 'A' + pin - 1, msg);
1262 }
1263 return 0;
1264 }
1265
mp_should_keep_irq(struct device * dev)1266 bool mp_should_keep_irq(struct device *dev)
1267 {
1268 if (dev->power.is_prepared)
1269 return true;
1270 #ifdef CONFIG_PM
1271 if (dev->power.runtime_status == RPM_SUSPENDING)
1272 return true;
1273 #endif
1274
1275 return false;
1276 }
1277
pirq_disable_irq(struct pci_dev * dev)1278 static void pirq_disable_irq(struct pci_dev *dev)
1279 {
1280 if (io_apic_assign_pci_irqs && !mp_should_keep_irq(&dev->dev) &&
1281 dev->irq_managed && dev->irq) {
1282 mp_unmap_irq(dev->irq);
1283 dev->irq = 0;
1284 dev->irq_managed = 0;
1285 }
1286 }
1287