1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
27
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
32 #include "i915_drv.h"
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_mst_helper.h>
37 #include <drm/drm_rect.h>
38 #include <drm/drm_atomic.h>
39
40 /**
41 * _wait_for - magic (register) wait macro
42 *
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
47 */
48 #define _wait_for(COND, MS, W) ({ \
49 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
50 int ret__ = 0; \
51 while (!(COND)) { \
52 if (time_after(jiffies, timeout__)) { \
53 if (!(COND)) \
54 ret__ = -ETIMEDOUT; \
55 break; \
56 } \
57 if ((W) && drm_can_sleep()) { \
58 usleep_range((W)*1000, (W)*2000); \
59 } else { \
60 cpu_relax(); \
61 } \
62 } \
63 ret__; \
64 })
65
66 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
69 DIV_ROUND_UP((US), 1000), 0)
70
71 #define KHz(x) (1000 * (x))
72 #define MHz(x) KHz(1000 * (x))
73
74 /*
75 * Display related stuff
76 */
77
78 /* store information about an Ixxx DVO */
79 /* The i830->i865 use multiple DVOs with multiple i2cs */
80 /* the i915, i945 have a single sDVO i2c bus - which is different */
81 #define MAX_OUTPUTS 6
82 /* maximum connectors per crtcs in the mode set */
83
84 /* Maximum cursor sizes */
85 #define GEN2_CURSOR_WIDTH 64
86 #define GEN2_CURSOR_HEIGHT 64
87 #define MAX_CURSOR_WIDTH 256
88 #define MAX_CURSOR_HEIGHT 256
89
90 #define INTEL_I2C_BUS_DVO 1
91 #define INTEL_I2C_BUS_SDVO 2
92
93 /* these are outputs from the chip - integrated only
94 external chips are via DVO or SDVO output */
95 enum intel_output_type {
96 INTEL_OUTPUT_UNUSED = 0,
97 INTEL_OUTPUT_ANALOG = 1,
98 INTEL_OUTPUT_DVO = 2,
99 INTEL_OUTPUT_SDVO = 3,
100 INTEL_OUTPUT_LVDS = 4,
101 INTEL_OUTPUT_TVOUT = 5,
102 INTEL_OUTPUT_HDMI = 6,
103 INTEL_OUTPUT_DISPLAYPORT = 7,
104 INTEL_OUTPUT_EDP = 8,
105 INTEL_OUTPUT_DSI = 9,
106 INTEL_OUTPUT_UNKNOWN = 10,
107 INTEL_OUTPUT_DP_MST = 11,
108 };
109
110 #define INTEL_DVO_CHIP_NONE 0
111 #define INTEL_DVO_CHIP_LVDS 1
112 #define INTEL_DVO_CHIP_TMDS 2
113 #define INTEL_DVO_CHIP_TVOUT 4
114
115 #define INTEL_DSI_VIDEO_MODE 0
116 #define INTEL_DSI_COMMAND_MODE 1
117
118 struct intel_framebuffer {
119 struct drm_framebuffer base;
120 struct drm_i915_gem_object *obj;
121 };
122
123 struct intel_fbdev {
124 struct drm_fb_helper helper;
125 struct intel_framebuffer *fb;
126 struct list_head fbdev_list;
127 struct drm_display_mode *our_mode;
128 int preferred_bpp;
129 };
130
131 struct intel_encoder {
132 struct drm_encoder base;
133
134 enum intel_output_type type;
135 unsigned int cloneable;
136 void (*hot_plug)(struct intel_encoder *);
137 bool (*compute_config)(struct intel_encoder *,
138 struct intel_crtc_state *);
139 void (*pre_pll_enable)(struct intel_encoder *);
140 void (*pre_enable)(struct intel_encoder *);
141 void (*enable)(struct intel_encoder *);
142 void (*mode_set)(struct intel_encoder *intel_encoder);
143 void (*disable)(struct intel_encoder *);
144 void (*post_disable)(struct intel_encoder *);
145 void (*post_pll_disable)(struct intel_encoder *);
146 /* Read out the current hw state of this connector, returning true if
147 * the encoder is active. If the encoder is enabled it also set the pipe
148 * it is connected to in the pipe parameter. */
149 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
150 /* Reconstructs the equivalent mode flags for the current hardware
151 * state. This must be called _after_ display->get_pipe_config has
152 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
153 * be set correctly before calling this function. */
154 void (*get_config)(struct intel_encoder *,
155 struct intel_crtc_state *pipe_config);
156 /*
157 * Called during system suspend after all pending requests for the
158 * encoder are flushed (for example for DP AUX transactions) and
159 * device interrupts are disabled.
160 */
161 void (*suspend)(struct intel_encoder *);
162 int crtc_mask;
163 enum hpd_pin hpd_pin;
164 };
165
166 struct intel_panel {
167 struct drm_display_mode *fixed_mode;
168 struct drm_display_mode *downclock_mode;
169 int fitting_mode;
170
171 /* backlight */
172 struct {
173 bool present;
174 u32 level;
175 u32 min;
176 u32 max;
177 bool enabled;
178 bool combination_mode; /* gen 2/4 only */
179 bool active_low_pwm;
180
181 /* PWM chip */
182 bool util_pin_active_low; /* bxt+ */
183 u8 controller; /* bxt+ only */
184 struct pwm_device *pwm;
185
186 struct backlight_device *device;
187
188 /* Connector and platform specific backlight functions */
189 int (*setup)(struct intel_connector *connector, enum pipe pipe);
190 uint32_t (*get)(struct intel_connector *connector);
191 void (*set)(struct intel_connector *connector, uint32_t level);
192 void (*disable)(struct intel_connector *connector);
193 void (*enable)(struct intel_connector *connector);
194 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
195 uint32_t hz);
196 void (*power)(struct intel_connector *, bool enable);
197 } backlight;
198 };
199
200 struct intel_connector {
201 struct drm_connector base;
202 /*
203 * The fixed encoder this connector is connected to.
204 */
205 struct intel_encoder *encoder;
206
207 /* Reads out the current hw, returning true if the connector is enabled
208 * and active (i.e. dpms ON state). */
209 bool (*get_hw_state)(struct intel_connector *);
210
211 /*
212 * Removes all interfaces through which the connector is accessible
213 * - like sysfs, debugfs entries -, so that no new operations can be
214 * started on the connector. Also makes sure all currently pending
215 * operations finish before returing.
216 */
217 void (*unregister)(struct intel_connector *);
218
219 /* Panel info for eDP and LVDS */
220 struct intel_panel panel;
221
222 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
223 struct edid *edid;
224 struct edid *detect_edid;
225
226 /* since POLL and HPD connectors may use the same HPD line keep the native
227 state of connector->polled in case hotplug storm detection changes it */
228 u8 polled;
229
230 void *port; /* store this opaque as its illegal to dereference it */
231
232 struct intel_dp *mst_port;
233 };
234
235 typedef struct dpll {
236 /* given values */
237 int n;
238 int m1, m2;
239 int p1, p2;
240 /* derived values */
241 int dot;
242 int vco;
243 int m;
244 int p;
245 } intel_clock_t;
246
247 struct intel_atomic_state {
248 struct drm_atomic_state base;
249
250 unsigned int cdclk;
251 bool dpll_set;
252 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
253 };
254
255 struct intel_plane_state {
256 struct drm_plane_state base;
257 struct drm_rect src;
258 struct drm_rect dst;
259 struct drm_rect clip;
260 bool visible;
261
262 /*
263 * scaler_id
264 * = -1 : not using a scaler
265 * >= 0 : using a scalers
266 *
267 * plane requiring a scaler:
268 * - During check_plane, its bit is set in
269 * crtc_state->scaler_state.scaler_users by calling helper function
270 * update_scaler_plane.
271 * - scaler_id indicates the scaler it got assigned.
272 *
273 * plane doesn't require a scaler:
274 * - this can happen when scaling is no more required or plane simply
275 * got disabled.
276 * - During check_plane, corresponding bit is reset in
277 * crtc_state->scaler_state.scaler_users by calling helper function
278 * update_scaler_plane.
279 */
280 int scaler_id;
281
282 struct drm_intel_sprite_colorkey ckey;
283 };
284
285 struct intel_initial_plane_config {
286 struct intel_framebuffer *fb;
287 unsigned int tiling;
288 int size;
289 u32 base;
290 };
291
292 #define SKL_MIN_SRC_W 8
293 #define SKL_MAX_SRC_W 4096
294 #define SKL_MIN_SRC_H 8
295 #define SKL_MAX_SRC_H 4096
296 #define SKL_MIN_DST_W 8
297 #define SKL_MAX_DST_W 4096
298 #define SKL_MIN_DST_H 8
299 #define SKL_MAX_DST_H 4096
300
301 struct intel_scaler {
302 int in_use;
303 uint32_t mode;
304 };
305
306 struct intel_crtc_scaler_state {
307 #define SKL_NUM_SCALERS 2
308 struct intel_scaler scalers[SKL_NUM_SCALERS];
309
310 /*
311 * scaler_users: keeps track of users requesting scalers on this crtc.
312 *
313 * If a bit is set, a user is using a scaler.
314 * Here user can be a plane or crtc as defined below:
315 * bits 0-30 - plane (bit position is index from drm_plane_index)
316 * bit 31 - crtc
317 *
318 * Instead of creating a new index to cover planes and crtc, using
319 * existing drm_plane_index for planes which is well less than 31
320 * planes and bit 31 for crtc. This should be fine to cover all
321 * our platforms.
322 *
323 * intel_atomic_setup_scalers will setup available scalers to users
324 * requesting scalers. It will gracefully fail if request exceeds
325 * avilability.
326 */
327 #define SKL_CRTC_INDEX 31
328 unsigned scaler_users;
329
330 /* scaler used by crtc for panel fitting purpose */
331 int scaler_id;
332 };
333
334 /* drm_mode->private_flags */
335 #define I915_MODE_FLAG_INHERITED 1
336
337 struct intel_crtc_state {
338 struct drm_crtc_state base;
339
340 /**
341 * quirks - bitfield with hw state readout quirks
342 *
343 * For various reasons the hw state readout code might not be able to
344 * completely faithfully read out the current state. These cases are
345 * tracked with quirk flags so that fastboot and state checker can act
346 * accordingly.
347 */
348 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
349 unsigned long quirks;
350
351 bool update_pipe;
352
353 /* Pipe source size (ie. panel fitter input size)
354 * All planes will be positioned inside this space,
355 * and get clipped at the edges. */
356 int pipe_src_w, pipe_src_h;
357
358 /* Whether to set up the PCH/FDI. Note that we never allow sharing
359 * between pch encoders and cpu encoders. */
360 bool has_pch_encoder;
361
362 /* Are we sending infoframes on the attached port */
363 bool has_infoframe;
364
365 /* CPU Transcoder for the pipe. Currently this can only differ from the
366 * pipe on Haswell (where we have a special eDP transcoder). */
367 enum transcoder cpu_transcoder;
368
369 /*
370 * Use reduced/limited/broadcast rbg range, compressing from the full
371 * range fed into the crtcs.
372 */
373 bool limited_color_range;
374
375 /* DP has a bunch of special case unfortunately, so mark the pipe
376 * accordingly. */
377 bool has_dp_encoder;
378
379 /* Whether we should send NULL infoframes. Required for audio. */
380 bool has_hdmi_sink;
381
382 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
383 * has_dp_encoder is set. */
384 bool has_audio;
385
386 /*
387 * Enable dithering, used when the selected pipe bpp doesn't match the
388 * plane bpp.
389 */
390 bool dither;
391
392 /* Controls for the clock computation, to override various stages. */
393 bool clock_set;
394
395 /* SDVO TV has a bunch of special case. To make multifunction encoders
396 * work correctly, we need to track this at runtime.*/
397 bool sdvo_tv_clock;
398
399 /*
400 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
401 * required. This is set in the 2nd loop of calling encoder's
402 * ->compute_config if the first pick doesn't work out.
403 */
404 bool bw_constrained;
405
406 /* Settings for the intel dpll used on pretty much everything but
407 * haswell. */
408 struct dpll dpll;
409
410 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
411 enum intel_dpll_id shared_dpll;
412
413 /*
414 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
415 * - enum skl_dpll on SKL
416 */
417 uint32_t ddi_pll_sel;
418
419 /* Actual register state of the dpll, for shared dpll cross-checking. */
420 struct intel_dpll_hw_state dpll_hw_state;
421
422 int pipe_bpp;
423 struct intel_link_m_n dp_m_n;
424
425 /* m2_n2 for eDP downclock */
426 struct intel_link_m_n dp_m2_n2;
427 bool has_drrs;
428
429 /*
430 * Frequence the dpll for the port should run at. Differs from the
431 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
432 * already multiplied by pixel_multiplier.
433 */
434 int port_clock;
435
436 /* Used by SDVO (and if we ever fix it, HDMI). */
437 unsigned pixel_multiplier;
438
439 uint8_t lane_count;
440
441 /* Panel fitter controls for gen2-gen4 + VLV */
442 struct {
443 u32 control;
444 u32 pgm_ratios;
445 u32 lvds_border_bits;
446 } gmch_pfit;
447
448 /* Panel fitter placement and size for Ironlake+ */
449 struct {
450 u32 pos;
451 u32 size;
452 bool enabled;
453 bool force_thru;
454 } pch_pfit;
455
456 /* FDI configuration, only valid if has_pch_encoder is set. */
457 int fdi_lanes;
458 struct intel_link_m_n fdi_m_n;
459
460 bool ips_enabled;
461
462 bool double_wide;
463
464 bool dp_encoder_is_mst;
465 int pbn;
466
467 struct intel_crtc_scaler_state scaler_state;
468
469 /* w/a for waiting 2 vblanks during crtc enable */
470 enum pipe hsw_workaround_pipe;
471 };
472
473 struct vlv_wm_state {
474 struct vlv_pipe_wm wm[3];
475 struct vlv_sr_wm sr[3];
476 uint8_t num_active_planes;
477 uint8_t num_levels;
478 uint8_t level;
479 bool cxsr;
480 };
481
482 struct intel_pipe_wm {
483 struct intel_wm_level wm[5];
484 uint32_t linetime;
485 bool fbc_wm_enabled;
486 bool pipe_enabled;
487 bool sprites_enabled;
488 bool sprites_scaled;
489 };
490
491 struct intel_mmio_flip {
492 struct work_struct work;
493 struct drm_i915_private *i915;
494 struct drm_i915_gem_request *req;
495 struct intel_crtc *crtc;
496 };
497
498 struct skl_pipe_wm {
499 struct skl_wm_level wm[8];
500 struct skl_wm_level trans_wm;
501 uint32_t linetime;
502 };
503
504 /*
505 * Tracking of operations that need to be performed at the beginning/end of an
506 * atomic commit, outside the atomic section where interrupts are disabled.
507 * These are generally operations that grab mutexes or might otherwise sleep
508 * and thus can't be run with interrupts disabled.
509 */
510 struct intel_crtc_atomic_commit {
511 /* Sleepable operations to perform before commit */
512 bool wait_for_flips;
513 bool disable_fbc;
514 bool disable_ips;
515 bool disable_cxsr;
516 bool pre_disable_primary;
517 bool update_wm_pre, update_wm_post;
518 unsigned disabled_planes;
519
520 /* Sleepable operations to perform after commit */
521 unsigned fb_bits;
522 bool wait_vblank;
523 bool update_fbc;
524 bool post_enable_primary;
525 unsigned update_sprite_watermarks;
526 };
527
528 struct intel_crtc {
529 struct drm_crtc base;
530 enum pipe pipe;
531 enum plane plane;
532 u8 lut_r[256], lut_g[256], lut_b[256];
533 /*
534 * Whether the crtc and the connected output pipeline is active. Implies
535 * that crtc->enabled is set, i.e. the current mode configuration has
536 * some outputs connected to this crtc.
537 */
538 bool active;
539 unsigned long enabled_power_domains;
540 bool lowfreq_avail;
541 struct intel_overlay *overlay;
542 struct intel_unpin_work *unpin_work;
543
544 atomic_t unpin_work_count;
545
546 /* Display surface base address adjustement for pageflips. Note that on
547 * gen4+ this only adjusts up to a tile, offsets within a tile are
548 * handled in the hw itself (with the TILEOFF register). */
549 unsigned long dspaddr_offset;
550 int adjusted_x;
551 int adjusted_y;
552
553 uint32_t cursor_addr;
554 uint32_t cursor_cntl;
555 uint32_t cursor_size;
556 uint32_t cursor_base;
557
558 struct intel_crtc_state *config;
559
560 /* reset counter value when the last flip was submitted */
561 unsigned int reset_counter;
562
563 /* Access to these should be protected by dev_priv->irq_lock. */
564 bool cpu_fifo_underrun_disabled;
565 bool pch_fifo_underrun_disabled;
566
567 /* per-pipe watermark state */
568 struct {
569 /* watermarks currently being used */
570 struct intel_pipe_wm active;
571 /* SKL wm values currently in use */
572 struct skl_pipe_wm skl_active;
573 /* allow CxSR on this pipe */
574 bool cxsr_allowed;
575 } wm;
576
577 int scanline_offset;
578
579 struct {
580 unsigned start_vbl_count;
581 ktime_t start_vbl_time;
582 int min_vbl, max_vbl;
583 int scanline_start;
584 } debug;
585
586 struct intel_crtc_atomic_commit atomic;
587
588 /* scalers available on this crtc */
589 int num_scalers;
590
591 struct vlv_wm_state wm_state;
592 };
593
594 struct intel_plane_wm_parameters {
595 uint32_t horiz_pixels;
596 uint32_t vert_pixels;
597 /*
598 * For packed pixel formats:
599 * bytes_per_pixel - holds bytes per pixel
600 * For planar pixel formats:
601 * bytes_per_pixel - holds bytes per pixel for uv-plane
602 * y_bytes_per_pixel - holds bytes per pixel for y-plane
603 */
604 uint8_t bytes_per_pixel;
605 uint8_t y_bytes_per_pixel;
606 bool enabled;
607 bool scaled;
608 u64 tiling;
609 unsigned int rotation;
610 uint16_t fifo_size;
611 };
612
613 struct intel_plane {
614 struct drm_plane base;
615 int plane;
616 enum pipe pipe;
617 bool can_scale;
618 int max_downscale;
619 uint32_t frontbuffer_bit;
620
621 /* Since we need to change the watermarks before/after
622 * enabling/disabling the planes, we need to store the parameters here
623 * as the other pieces of the struct may not reflect the values we want
624 * for the watermark calculations. Currently only Haswell uses this.
625 */
626 struct intel_plane_wm_parameters wm;
627
628 /*
629 * NOTE: Do not place new plane state fields here (e.g., when adding
630 * new plane properties). New runtime state should now be placed in
631 * the intel_plane_state structure and accessed via drm_plane->state.
632 */
633
634 void (*update_plane)(struct drm_plane *plane,
635 struct drm_crtc *crtc,
636 struct drm_framebuffer *fb,
637 int crtc_x, int crtc_y,
638 unsigned int crtc_w, unsigned int crtc_h,
639 uint32_t x, uint32_t y,
640 uint32_t src_w, uint32_t src_h);
641 void (*disable_plane)(struct drm_plane *plane,
642 struct drm_crtc *crtc);
643 int (*check_plane)(struct drm_plane *plane,
644 struct intel_crtc_state *crtc_state,
645 struct intel_plane_state *state);
646 void (*commit_plane)(struct drm_plane *plane,
647 struct intel_plane_state *state);
648 };
649
650 struct intel_watermark_params {
651 unsigned long fifo_size;
652 unsigned long max_wm;
653 unsigned long default_wm;
654 unsigned long guard_size;
655 unsigned long cacheline_size;
656 };
657
658 struct cxsr_latency {
659 int is_desktop;
660 int is_ddr3;
661 unsigned long fsb_freq;
662 unsigned long mem_freq;
663 unsigned long display_sr;
664 unsigned long display_hpll_disable;
665 unsigned long cursor_sr;
666 unsigned long cursor_hpll_disable;
667 };
668
669 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
670 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
671 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
672 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
673 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
674 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
675 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
676 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
677 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
678
679 struct intel_hdmi {
680 u32 hdmi_reg;
681 int ddc_bus;
682 bool limited_color_range;
683 bool color_range_auto;
684 bool has_hdmi_sink;
685 bool has_audio;
686 enum hdmi_force_audio force_audio;
687 bool rgb_quant_range_selectable;
688 enum hdmi_picture_aspect aspect_ratio;
689 struct intel_connector *attached_connector;
690 void (*write_infoframe)(struct drm_encoder *encoder,
691 enum hdmi_infoframe_type type,
692 const void *frame, ssize_t len);
693 void (*set_infoframes)(struct drm_encoder *encoder,
694 bool enable,
695 const struct drm_display_mode *adjusted_mode);
696 bool (*infoframe_enabled)(struct drm_encoder *encoder);
697 };
698
699 struct intel_dp_mst_encoder;
700 #define DP_MAX_DOWNSTREAM_PORTS 0x10
701
702 /*
703 * enum link_m_n_set:
704 * When platform provides two set of M_N registers for dp, we can
705 * program them and switch between them incase of DRRS.
706 * But When only one such register is provided, we have to program the
707 * required divider value on that registers itself based on the DRRS state.
708 *
709 * M1_N1 : Program dp_m_n on M1_N1 registers
710 * dp_m2_n2 on M2_N2 registers (If supported)
711 *
712 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
713 * M2_N2 registers are not supported
714 */
715
716 enum link_m_n_set {
717 /* Sets the m1_n1 and m2_n2 */
718 M1_N1 = 0,
719 M2_N2
720 };
721
722 struct sink_crc {
723 bool started;
724 u8 last_crc[6];
725 int last_count;
726 };
727
728 struct intel_dp {
729 uint32_t output_reg;
730 uint32_t aux_ch_ctl_reg;
731 uint32_t DP;
732 int link_rate;
733 uint8_t lane_count;
734 bool has_audio;
735 enum hdmi_force_audio force_audio;
736 bool limited_color_range;
737 bool color_range_auto;
738 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
739 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
740 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
741 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
742 uint8_t num_sink_rates;
743 int sink_rates[DP_MAX_SUPPORTED_RATES];
744 struct sink_crc sink_crc;
745 struct drm_dp_aux aux;
746 uint8_t train_set[4];
747 int panel_power_up_delay;
748 int panel_power_down_delay;
749 int panel_power_cycle_delay;
750 int backlight_on_delay;
751 int backlight_off_delay;
752 struct delayed_work panel_vdd_work;
753 bool want_panel_vdd;
754 unsigned long last_power_cycle;
755 unsigned long last_power_on;
756 unsigned long last_backlight_off;
757
758 struct notifier_block edp_notifier;
759
760 /*
761 * Pipe whose power sequencer is currently locked into
762 * this port. Only relevant on VLV/CHV.
763 */
764 enum pipe pps_pipe;
765 struct edp_power_seq pps_delays;
766
767 bool can_mst; /* this port supports mst */
768 bool is_mst;
769 int active_mst_links;
770 /* connector directly attached - won't be use for modeset in mst world */
771 struct intel_connector *attached_connector;
772
773 /* mst connector list */
774 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
775 struct drm_dp_mst_topology_mgr mst_mgr;
776
777 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
778 /*
779 * This function returns the value we have to program the AUX_CTL
780 * register with to kick off an AUX transaction.
781 */
782 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
783 bool has_aux_irq,
784 int send_bytes,
785 uint32_t aux_clock_divider);
786
787 /* Displayport compliance testing */
788 unsigned long compliance_test_type;
789 unsigned long compliance_test_data;
790 bool compliance_test_active;
791 };
792
793 struct intel_digital_port {
794 struct intel_encoder base;
795 enum port port;
796 u32 saved_port_bits;
797 struct intel_dp dp;
798 struct intel_hdmi hdmi;
799 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
800 bool release_cl2_override;
801 };
802
803 struct intel_dp_mst_encoder {
804 struct intel_encoder base;
805 enum pipe pipe;
806 struct intel_digital_port *primary;
807 void *port; /* store this opaque as its illegal to dereference it */
808 };
809
810 static inline enum dpio_channel
vlv_dport_to_channel(struct intel_digital_port * dport)811 vlv_dport_to_channel(struct intel_digital_port *dport)
812 {
813 switch (dport->port) {
814 case PORT_B:
815 case PORT_D:
816 return DPIO_CH0;
817 case PORT_C:
818 return DPIO_CH1;
819 default:
820 BUG();
821 }
822 }
823
824 static inline enum dpio_phy
vlv_dport_to_phy(struct intel_digital_port * dport)825 vlv_dport_to_phy(struct intel_digital_port *dport)
826 {
827 switch (dport->port) {
828 case PORT_B:
829 case PORT_C:
830 return DPIO_PHY0;
831 case PORT_D:
832 return DPIO_PHY1;
833 default:
834 BUG();
835 }
836 }
837
838 static inline enum dpio_channel
vlv_pipe_to_channel(enum pipe pipe)839 vlv_pipe_to_channel(enum pipe pipe)
840 {
841 switch (pipe) {
842 case PIPE_A:
843 case PIPE_C:
844 return DPIO_CH0;
845 case PIPE_B:
846 return DPIO_CH1;
847 default:
848 BUG();
849 }
850 }
851
852 static inline struct drm_crtc *
intel_get_crtc_for_pipe(struct drm_device * dev,int pipe)853 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
854 {
855 struct drm_i915_private *dev_priv = dev->dev_private;
856 return dev_priv->pipe_to_crtc_mapping[pipe];
857 }
858
859 static inline struct drm_crtc *
intel_get_crtc_for_plane(struct drm_device * dev,int plane)860 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
861 {
862 struct drm_i915_private *dev_priv = dev->dev_private;
863 return dev_priv->plane_to_crtc_mapping[plane];
864 }
865
866 struct intel_unpin_work {
867 struct work_struct work;
868 struct drm_crtc *crtc;
869 struct drm_framebuffer *old_fb;
870 struct drm_i915_gem_object *pending_flip_obj;
871 struct drm_pending_vblank_event *event;
872 atomic_t pending;
873 #define INTEL_FLIP_INACTIVE 0
874 #define INTEL_FLIP_PENDING 1
875 #define INTEL_FLIP_COMPLETE 2
876 u32 flip_count;
877 u32 gtt_offset;
878 struct drm_i915_gem_request *flip_queued_req;
879 u32 flip_queued_vblank;
880 u32 flip_ready_vblank;
881 bool enable_stall_check;
882 };
883
884 struct intel_load_detect_pipe {
885 struct drm_framebuffer *release_fb;
886 bool load_detect_temp;
887 int dpms_mode;
888 };
889
890 static inline struct intel_encoder *
intel_attached_encoder(struct drm_connector * connector)891 intel_attached_encoder(struct drm_connector *connector)
892 {
893 return to_intel_connector(connector)->encoder;
894 }
895
896 static inline struct intel_digital_port *
enc_to_dig_port(struct drm_encoder * encoder)897 enc_to_dig_port(struct drm_encoder *encoder)
898 {
899 return container_of(encoder, struct intel_digital_port, base.base);
900 }
901
902 static inline struct intel_dp_mst_encoder *
enc_to_mst(struct drm_encoder * encoder)903 enc_to_mst(struct drm_encoder *encoder)
904 {
905 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
906 }
907
enc_to_intel_dp(struct drm_encoder * encoder)908 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
909 {
910 return &enc_to_dig_port(encoder)->dp;
911 }
912
913 static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp * intel_dp)914 dp_to_dig_port(struct intel_dp *intel_dp)
915 {
916 return container_of(intel_dp, struct intel_digital_port, dp);
917 }
918
919 static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi * intel_hdmi)920 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
921 {
922 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
923 }
924
925 /*
926 * Returns the number of planes for this pipe, ie the number of sprites + 1
927 * (primary plane). This doesn't count the cursor plane then.
928 */
intel_num_planes(struct intel_crtc * crtc)929 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
930 {
931 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
932 }
933
934 /* intel_fifo_underrun.c */
935 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
936 enum pipe pipe, bool enable);
937 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
938 enum transcoder pch_transcoder,
939 bool enable);
940 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
941 enum pipe pipe);
942 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
943 enum transcoder pch_transcoder);
944 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
945
946 /* i915_irq.c */
947 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
948 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
949 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
950 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
951 void gen6_reset_rps_interrupts(struct drm_device *dev);
952 void gen6_enable_rps_interrupts(struct drm_device *dev);
953 void gen6_disable_rps_interrupts(struct drm_device *dev);
954 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
955 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
956 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
intel_irqs_enabled(struct drm_i915_private * dev_priv)957 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
958 {
959 /*
960 * We only use drm_irq_uninstall() at unload and VT switch, so
961 * this is the only thing we need to check.
962 */
963 return dev_priv->pm.irqs_enabled;
964 }
965
966 int intel_get_crtc_scanline(struct intel_crtc *crtc);
967 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
968 unsigned int pipe_mask);
969
970 /* intel_crt.c */
971 void intel_crt_init(struct drm_device *dev);
972
973
974 /* intel_ddi.c */
975 void intel_prepare_ddi(struct drm_device *dev);
976 void hsw_fdi_link_train(struct drm_crtc *crtc);
977 void intel_ddi_init(struct drm_device *dev, enum port port);
978 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
979 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
980 void intel_ddi_pll_init(struct drm_device *dev);
981 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
982 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
983 enum transcoder cpu_transcoder);
984 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
985 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
986 bool intel_ddi_pll_select(struct intel_crtc *crtc,
987 struct intel_crtc_state *crtc_state);
988 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
989 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
990 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
991 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
992 void intel_ddi_get_config(struct intel_encoder *encoder,
993 struct intel_crtc_state *pipe_config);
994 struct intel_encoder *
995 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
996
997 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
998 void intel_ddi_clock_get(struct intel_encoder *encoder,
999 struct intel_crtc_state *pipe_config);
1000 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1001 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1002
1003 /* intel_frontbuffer.c */
1004 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1005 enum fb_op_origin origin);
1006 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1007 unsigned frontbuffer_bits);
1008 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1009 unsigned frontbuffer_bits);
1010 void intel_frontbuffer_flip(struct drm_device *dev,
1011 unsigned frontbuffer_bits);
1012 unsigned int intel_fb_align_height(struct drm_device *dev,
1013 unsigned int height,
1014 uint32_t pixel_format,
1015 uint64_t fb_format_modifier);
1016 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1017 enum fb_op_origin origin);
1018 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
1019 uint32_t pixel_format);
1020
1021 /* intel_audio.c */
1022 void intel_init_audio(struct drm_device *dev);
1023 void intel_audio_codec_enable(struct intel_encoder *encoder);
1024 void intel_audio_codec_disable(struct intel_encoder *encoder);
1025 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1026 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1027
1028 /* intel_display.c */
1029 extern const struct drm_plane_funcs intel_plane_funcs;
1030 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1031 int intel_pch_rawclk(struct drm_device *dev);
1032 int intel_hrawclk(struct drm_device *dev);
1033 void intel_mark_busy(struct drm_device *dev);
1034 void intel_mark_idle(struct drm_device *dev);
1035 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1036 int intel_display_suspend(struct drm_device *dev);
1037 void intel_encoder_destroy(struct drm_encoder *encoder);
1038 int intel_connector_init(struct intel_connector *);
1039 struct intel_connector *intel_connector_alloc(void);
1040 bool intel_connector_get_hw_state(struct intel_connector *connector);
1041 void intel_connector_attach_encoder(struct intel_connector *connector,
1042 struct intel_encoder *encoder);
1043 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1044 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1045 struct drm_crtc *crtc);
1046 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1047 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1048 struct drm_file *file_priv);
1049 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1050 enum pipe pipe);
1051 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1052 static inline void
intel_wait_for_vblank(struct drm_device * dev,int pipe)1053 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1054 {
1055 drm_wait_one_vblank(dev, pipe);
1056 }
1057 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1058 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1059 struct intel_digital_port *dport,
1060 unsigned int expected_mask);
1061 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1062 struct drm_display_mode *mode,
1063 struct intel_load_detect_pipe *old,
1064 struct drm_modeset_acquire_ctx *ctx);
1065 void intel_release_load_detect_pipe(struct drm_connector *connector,
1066 struct intel_load_detect_pipe *old,
1067 struct drm_modeset_acquire_ctx *ctx);
1068 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1069 struct drm_framebuffer *fb,
1070 const struct drm_plane_state *plane_state,
1071 struct intel_engine_cs *pipelined,
1072 struct drm_i915_gem_request **pipelined_request);
1073 struct drm_framebuffer *
1074 __intel_framebuffer_create(struct drm_device *dev,
1075 struct drm_mode_fb_cmd2 *mode_cmd,
1076 struct drm_i915_gem_object *obj);
1077 void intel_prepare_page_flip(struct drm_device *dev, int plane);
1078 void intel_finish_page_flip(struct drm_device *dev, int pipe);
1079 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1080 void intel_check_page_flip(struct drm_device *dev, int pipe);
1081 int intel_prepare_plane_fb(struct drm_plane *plane,
1082 const struct drm_plane_state *new_state);
1083 void intel_cleanup_plane_fb(struct drm_plane *plane,
1084 const struct drm_plane_state *old_state);
1085 int intel_plane_atomic_get_property(struct drm_plane *plane,
1086 const struct drm_plane_state *state,
1087 struct drm_property *property,
1088 uint64_t *val);
1089 int intel_plane_atomic_set_property(struct drm_plane *plane,
1090 struct drm_plane_state *state,
1091 struct drm_property *property,
1092 uint64_t val);
1093 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1094 struct drm_plane_state *plane_state);
1095
1096 unsigned int
1097 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1098 uint64_t fb_format_modifier, unsigned int plane);
1099
1100 static inline bool
intel_rotation_90_or_270(unsigned int rotation)1101 intel_rotation_90_or_270(unsigned int rotation)
1102 {
1103 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1104 }
1105
1106 void intel_create_rotation_property(struct drm_device *dev,
1107 struct intel_plane *plane);
1108
1109 /* shared dpll functions */
1110 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1111 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1112 struct intel_shared_dpll *pll,
1113 bool state);
1114 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1115 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1116 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1117 struct intel_crtc_state *state);
1118
1119 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1120 const struct dpll *dpll);
1121 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1122
1123 /* modesetting asserts */
1124 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1125 enum pipe pipe);
1126 void assert_pll(struct drm_i915_private *dev_priv,
1127 enum pipe pipe, bool state);
1128 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1129 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1130 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1131 enum pipe pipe, bool state);
1132 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1133 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1134 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1135 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1136 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1137 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
1138 int *x, int *y,
1139 unsigned int tiling_mode,
1140 unsigned int bpp,
1141 unsigned int pitch);
1142 void intel_prepare_reset(struct drm_device *dev);
1143 void intel_finish_reset(struct drm_device *dev);
1144 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1145 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1146 void broxton_init_cdclk(struct drm_device *dev);
1147 void broxton_uninit_cdclk(struct drm_device *dev);
1148 void broxton_ddi_phy_init(struct drm_device *dev);
1149 void broxton_ddi_phy_uninit(struct drm_device *dev);
1150 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1151 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1152 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1153 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1154 void intel_dp_get_m_n(struct intel_crtc *crtc,
1155 struct intel_crtc_state *pipe_config);
1156 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1157 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1158 void
1159 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1160 int dotclock);
1161 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1162 intel_clock_t *best_clock);
1163 int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1164
1165 bool intel_crtc_active(struct drm_crtc *crtc);
1166 void hsw_enable_ips(struct intel_crtc *crtc);
1167 void hsw_disable_ips(struct intel_crtc *crtc);
1168 enum intel_display_power_domain
1169 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1170 enum intel_display_power_domain
1171 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1172 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1173 struct intel_crtc_state *pipe_config);
1174 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1175 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1176
1177 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1178 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1179
1180 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1181 struct drm_i915_gem_object *obj,
1182 unsigned int plane);
1183
1184 u32 skl_plane_ctl_format(uint32_t pixel_format);
1185 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1186 u32 skl_plane_ctl_rotation(unsigned int rotation);
1187
1188 /* intel_csr.c */
1189 void intel_csr_ucode_init(struct drm_device *dev);
1190 enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1191 void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1192 enum csr_state state);
1193 void intel_csr_load_program(struct drm_device *dev);
1194 void intel_csr_ucode_fini(struct drm_device *dev);
1195 void assert_csr_loaded(struct drm_i915_private *dev_priv);
1196
1197 /* intel_dp.c */
1198 bool intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1199 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1200 struct intel_connector *intel_connector);
1201 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1202 const struct intel_crtc_state *pipe_config);
1203 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1204 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1205 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1206 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1207 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1208 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1209 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1210 bool intel_dp_compute_config(struct intel_encoder *encoder,
1211 struct intel_crtc_state *pipe_config);
1212 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1213 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1214 bool long_hpd);
1215 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1216 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1217 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1218 void intel_edp_panel_on(struct intel_dp *intel_dp);
1219 void intel_edp_panel_off(struct intel_dp *intel_dp);
1220 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1221 void intel_dp_mst_suspend(struct drm_device *dev);
1222 void intel_dp_mst_resume(struct drm_device *dev);
1223 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1224 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1225 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1226 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1227 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1228 void intel_plane_destroy(struct drm_plane *plane);
1229 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1230 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1231 void intel_edp_drrs_invalidate(struct drm_device *dev,
1232 unsigned frontbuffer_bits);
1233 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1234 void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
1235
1236 /* intel_dp_mst.c */
1237 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1238 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1239 /* intel_dsi.c */
1240 void intel_dsi_init(struct drm_device *dev);
1241
1242
1243 /* intel_dvo.c */
1244 void intel_dvo_init(struct drm_device *dev);
1245
1246
1247 /* legacy fbdev emulation in intel_fbdev.c */
1248 #ifdef CONFIG_DRM_FBDEV_EMULATION
1249 extern int intel_fbdev_init(struct drm_device *dev);
1250 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1251 extern void intel_fbdev_fini(struct drm_device *dev);
1252 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1253 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1254 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1255 #else
intel_fbdev_init(struct drm_device * dev)1256 static inline int intel_fbdev_init(struct drm_device *dev)
1257 {
1258 return 0;
1259 }
1260
intel_fbdev_initial_config(void * data,async_cookie_t cookie)1261 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1262 {
1263 }
1264
intel_fbdev_fini(struct drm_device * dev)1265 static inline void intel_fbdev_fini(struct drm_device *dev)
1266 {
1267 }
1268
intel_fbdev_set_suspend(struct drm_device * dev,int state,bool synchronous)1269 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1270 {
1271 }
1272
intel_fbdev_restore_mode(struct drm_device * dev)1273 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1274 {
1275 }
1276 #endif
1277
1278 /* intel_fbc.c */
1279 bool intel_fbc_enabled(struct drm_i915_private *dev_priv);
1280 void intel_fbc_update(struct drm_i915_private *dev_priv);
1281 void intel_fbc_init(struct drm_i915_private *dev_priv);
1282 void intel_fbc_disable(struct drm_i915_private *dev_priv);
1283 void intel_fbc_disable_crtc(struct intel_crtc *crtc);
1284 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1285 unsigned int frontbuffer_bits,
1286 enum fb_op_origin origin);
1287 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1288 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1289 const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
1290 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1291
1292 /* intel_hdmi.c */
1293 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1294 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1295 struct intel_connector *intel_connector);
1296 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1297 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1298 struct intel_crtc_state *pipe_config);
1299
1300
1301 /* intel_lvds.c */
1302 void intel_lvds_init(struct drm_device *dev);
1303 bool intel_is_dual_link_lvds(struct drm_device *dev);
1304
1305
1306 /* intel_modes.c */
1307 int intel_connector_update_modes(struct drm_connector *connector,
1308 struct edid *edid);
1309 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1310 void intel_attach_force_audio_property(struct drm_connector *connector);
1311 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1312 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1313
1314
1315 /* intel_overlay.c */
1316 void intel_setup_overlay(struct drm_device *dev);
1317 void intel_cleanup_overlay(struct drm_device *dev);
1318 int intel_overlay_switch_off(struct intel_overlay *overlay);
1319 int intel_overlay_put_image(struct drm_device *dev, void *data,
1320 struct drm_file *file_priv);
1321 int intel_overlay_attrs(struct drm_device *dev, void *data,
1322 struct drm_file *file_priv);
1323 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1324
1325
1326 /* intel_panel.c */
1327 int intel_panel_init(struct intel_panel *panel,
1328 struct drm_display_mode *fixed_mode,
1329 struct drm_display_mode *downclock_mode);
1330 void intel_panel_fini(struct intel_panel *panel);
1331 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1332 struct drm_display_mode *adjusted_mode);
1333 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1334 struct intel_crtc_state *pipe_config,
1335 int fitting_mode);
1336 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1337 struct intel_crtc_state *pipe_config,
1338 int fitting_mode);
1339 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1340 u32 level, u32 max);
1341 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1342 void intel_panel_enable_backlight(struct intel_connector *connector);
1343 void intel_panel_disable_backlight(struct intel_connector *connector);
1344 void intel_panel_destroy_backlight(struct drm_connector *connector);
1345 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1346 extern struct drm_display_mode *intel_find_panel_downclock(
1347 struct drm_device *dev,
1348 struct drm_display_mode *fixed_mode,
1349 struct drm_connector *connector);
1350 void intel_backlight_register(struct drm_device *dev);
1351 void intel_backlight_unregister(struct drm_device *dev);
1352
1353
1354 /* intel_psr.c */
1355 void intel_psr_enable(struct intel_dp *intel_dp);
1356 void intel_psr_disable(struct intel_dp *intel_dp);
1357 void intel_psr_invalidate(struct drm_device *dev,
1358 unsigned frontbuffer_bits);
1359 void intel_psr_flush(struct drm_device *dev,
1360 unsigned frontbuffer_bits,
1361 enum fb_op_origin origin);
1362 void intel_psr_init(struct drm_device *dev);
1363 void intel_psr_single_frame_update(struct drm_device *dev,
1364 unsigned frontbuffer_bits);
1365
1366 /* intel_runtime_pm.c */
1367 int intel_power_domains_init(struct drm_i915_private *);
1368 void intel_power_domains_fini(struct drm_i915_private *);
1369 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1370 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1371
1372 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1373 enum intel_display_power_domain domain);
1374 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1375 enum intel_display_power_domain domain);
1376 void intel_display_power_get(struct drm_i915_private *dev_priv,
1377 enum intel_display_power_domain domain);
1378 void intel_display_power_put(struct drm_i915_private *dev_priv,
1379 enum intel_display_power_domain domain);
1380 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1381 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1382 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1383
1384 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1385
1386 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1387 bool override, unsigned int mask);
1388 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1389 enum dpio_channel ch, bool override);
1390
1391
1392 /* intel_pm.c */
1393 void intel_init_clock_gating(struct drm_device *dev);
1394 void intel_suspend_hw(struct drm_device *dev);
1395 int ilk_wm_max_level(const struct drm_device *dev);
1396 void intel_update_watermarks(struct drm_crtc *crtc);
1397 void intel_update_sprite_watermarks(struct drm_plane *plane,
1398 struct drm_crtc *crtc,
1399 uint32_t sprite_width,
1400 uint32_t sprite_height,
1401 int pixel_size,
1402 bool enabled, bool scaled);
1403 void intel_init_pm(struct drm_device *dev);
1404 void intel_pm_setup(struct drm_device *dev);
1405 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1406 void intel_gpu_ips_teardown(void);
1407 void intel_init_gt_powersave(struct drm_device *dev);
1408 void intel_cleanup_gt_powersave(struct drm_device *dev);
1409 void intel_enable_gt_powersave(struct drm_device *dev);
1410 void intel_disable_gt_powersave(struct drm_device *dev);
1411 void intel_suspend_gt_powersave(struct drm_device *dev);
1412 void intel_reset_gt_powersave(struct drm_device *dev);
1413 bool i915_rc6_ctx_wa_check(struct drm_i915_private *i915);
1414 void i915_rc6_ctx_wa_suspend(struct drm_i915_private *i915);
1415 void i915_rc6_ctx_wa_resume(struct drm_i915_private *i915);
1416 void gen6_update_ring_freq(struct drm_device *dev);
1417 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1418 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1419 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1420 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1421 struct intel_rps_client *rps,
1422 unsigned long submitted);
1423 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1424 struct drm_i915_gem_request *req);
1425 void vlv_wm_get_hw_state(struct drm_device *dev);
1426 void ilk_wm_get_hw_state(struct drm_device *dev);
1427 void skl_wm_get_hw_state(struct drm_device *dev);
1428 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1429 struct skl_ddb_allocation *ddb /* out */);
1430 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1431
1432 /* intel_sdvo.c */
1433 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1434
1435
1436 /* intel_sprite.c */
1437 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1438 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1439 struct drm_file *file_priv);
1440 void intel_pipe_update_start(struct intel_crtc *crtc);
1441 void intel_pipe_update_end(struct intel_crtc *crtc);
1442
1443 /* intel_tv.c */
1444 void intel_tv_init(struct drm_device *dev);
1445
1446 /* intel_atomic.c */
1447 int intel_connector_atomic_get_property(struct drm_connector *connector,
1448 const struct drm_connector_state *state,
1449 struct drm_property *property,
1450 uint64_t *val);
1451 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1452 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1453 struct drm_crtc_state *state);
1454 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1455 void intel_atomic_state_clear(struct drm_atomic_state *);
1456 struct intel_shared_dpll_config *
1457 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1458
1459 static inline struct intel_crtc_state *
intel_atomic_get_crtc_state(struct drm_atomic_state * state,struct intel_crtc * crtc)1460 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1461 struct intel_crtc *crtc)
1462 {
1463 struct drm_crtc_state *crtc_state;
1464 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1465 if (IS_ERR(crtc_state))
1466 return ERR_CAST(crtc_state);
1467
1468 return to_intel_crtc_state(crtc_state);
1469 }
1470 int intel_atomic_setup_scalers(struct drm_device *dev,
1471 struct intel_crtc *intel_crtc,
1472 struct intel_crtc_state *crtc_state);
1473
1474 /* intel_atomic_plane.c */
1475 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1476 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1477 void intel_plane_destroy_state(struct drm_plane *plane,
1478 struct drm_plane_state *state);
1479 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1480
1481 #endif /* __INTEL_DRV_H__ */
1482