1 /*
2 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #ifndef __DSI_PLL_H__
15 #define __DSI_PLL_H__
16
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19
20 #include "dsi.h"
21
22 #define NUM_DSI_CLOCKS_MAX 6
23 #define MAX_DSI_PLL_EN_SEQS 10
24
25 struct msm_dsi_pll {
26 enum msm_dsi_phy_type type;
27
28 struct clk_hw clk_hw;
29 bool pll_on;
30 bool state_saved;
31
32 unsigned long min_rate;
33 unsigned long max_rate;
34 u32 en_seq_cnt;
35
36 int (*enable_seqs[MAX_DSI_PLL_EN_SEQS])(struct msm_dsi_pll *pll);
37 void (*disable_seq)(struct msm_dsi_pll *pll);
38 int (*get_provider)(struct msm_dsi_pll *pll,
39 struct clk **byte_clk_provider,
40 struct clk **pixel_clk_provider);
41 void (*destroy)(struct msm_dsi_pll *pll);
42 void (*save_state)(struct msm_dsi_pll *pll);
43 int (*restore_state)(struct msm_dsi_pll *pll);
44 };
45
46 #define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw)
47
pll_write(void __iomem * reg,u32 data)48 static inline void pll_write(void __iomem *reg, u32 data)
49 {
50 msm_writel(data, reg);
51 }
52
pll_read(const void __iomem * reg)53 static inline u32 pll_read(const void __iomem *reg)
54 {
55 return msm_readl(reg);
56 }
57
pll_write_udelay(void __iomem * reg,u32 data,u32 delay_us)58 static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us)
59 {
60 pll_write(reg, data);
61 udelay(delay_us);
62 }
63
pll_write_ndelay(void __iomem * reg,u32 data,u32 delay_ns)64 static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns)
65 {
66 pll_write((reg), data);
67 ndelay(delay_ns);
68 }
69
70 /*
71 * DSI PLL Helper functions
72 */
73
74 /* clock callbacks */
75 long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
76 unsigned long rate, unsigned long *parent_rate);
77 int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw);
78 void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
79 /* misc */
80 void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
81 struct clk **clks, u32 num_clks);
82
83 /*
84 * Initialization for Each PLL Type
85 */
86 #ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
87 struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
88 enum msm_dsi_phy_type type, int id);
89 #else
msm_dsi_pll_28nm_init(struct platform_device * pdev,enum msm_dsi_phy_type type,int id)90 static inline struct msm_dsi_pll *msm_dsi_pll_28nm_init(
91 struct platform_device *pdev, enum msm_dsi_phy_type type, int id)
92 {
93 return ERR_PTR(-ENODEV);
94 }
95 #endif
96
97 #endif /* __DSI_PLL_H__ */
98
99