1 /*
2 * PowerNV setup code.
3 *
4 * Copyright 2011 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #undef DEBUG
13
14 #include <linux/cpu.h>
15 #include <linux/errno.h>
16 #include <linux/sched.h>
17 #include <linux/kernel.h>
18 #include <linux/tty.h>
19 #include <linux/reboot.h>
20 #include <linux/init.h>
21 #include <linux/console.h>
22 #include <linux/delay.h>
23 #include <linux/irq.h>
24 #include <linux/seq_file.h>
25 #include <linux/of.h>
26 #include <linux/of_fdt.h>
27 #include <linux/interrupt.h>
28 #include <linux/bug.h>
29 #include <linux/pci.h>
30 #include <linux/cpufreq.h>
31
32 #include <asm/machdep.h>
33 #include <asm/firmware.h>
34 #include <asm/xics.h>
35 #include <asm/opal.h>
36 #include <asm/kexec.h>
37 #include <asm/smp.h>
38 #include <asm/tm.h>
39 #include <asm/setup.h>
40 #include <asm/security_features.h>
41
42 #include "powernv.h"
43
44
fw_feature_is(const char * state,const char * name,struct device_node * fw_features)45 static bool fw_feature_is(const char *state, const char *name,
46 struct device_node *fw_features)
47 {
48 struct device_node *np;
49 bool rc = false;
50
51 np = of_get_child_by_name(fw_features, name);
52 if (np) {
53 rc = of_property_read_bool(np, state);
54 of_node_put(np);
55 }
56
57 return rc;
58 }
59
init_fw_feat_flags(struct device_node * np)60 static void init_fw_feat_flags(struct device_node *np)
61 {
62 if (fw_feature_is("enabled", "inst-spec-barrier-ori31,31,0", np))
63 security_ftr_set(SEC_FTR_SPEC_BAR_ORI31);
64
65 if (fw_feature_is("enabled", "fw-bcctrl-serialized", np))
66 security_ftr_set(SEC_FTR_BCCTRL_SERIALISED);
67
68 if (fw_feature_is("enabled", "inst-l1d-flush-ori30,30,0", np))
69 security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30);
70
71 if (fw_feature_is("enabled", "inst-l1d-flush-trig2", np))
72 security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2);
73
74 if (fw_feature_is("enabled", "fw-l1d-thread-split", np))
75 security_ftr_set(SEC_FTR_L1D_THREAD_PRIV);
76
77 if (fw_feature_is("enabled", "fw-count-cache-disabled", np))
78 security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED);
79
80 if (fw_feature_is("enabled", "fw-count-cache-flush-bcctr2,0,0", np))
81 security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST);
82
83 if (fw_feature_is("enabled", "needs-count-cache-flush-on-context-switch", np))
84 security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE);
85
86 /*
87 * The features below are enabled by default, so we instead look to see
88 * if firmware has *disabled* them, and clear them if so.
89 */
90 if (fw_feature_is("disabled", "speculation-policy-favor-security", np))
91 security_ftr_clear(SEC_FTR_FAVOUR_SECURITY);
92
93 if (fw_feature_is("disabled", "needs-l1d-flush-msr-pr-0-to-1", np))
94 security_ftr_clear(SEC_FTR_L1D_FLUSH_PR);
95
96 if (fw_feature_is("disabled", "needs-l1d-flush-msr-hv-1-to-0", np))
97 security_ftr_clear(SEC_FTR_L1D_FLUSH_HV);
98
99 if (fw_feature_is("disabled", "needs-spec-barrier-for-bound-checks", np))
100 security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR);
101 }
102
pnv_setup_rfi_flush(void)103 static void pnv_setup_rfi_flush(void)
104 {
105 struct device_node *np, *fw_features;
106 enum l1d_flush_type type;
107 bool enable;
108
109 /* Default to fallback in case fw-features are not available */
110 type = L1D_FLUSH_FALLBACK;
111
112 np = of_find_node_by_name(NULL, "ibm,opal");
113 fw_features = of_get_child_by_name(np, "fw-features");
114 of_node_put(np);
115
116 if (fw_features) {
117 init_fw_feat_flags(fw_features);
118 of_node_put(fw_features);
119
120 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2))
121 type = L1D_FLUSH_MTTRIG;
122
123 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30))
124 type = L1D_FLUSH_ORI;
125 }
126
127 /*
128 * 4.4 doesn't support Power9 bare metal, so we don't need to flush
129 * here - the flushes fix a P9 specific vulnerability.
130 */
131 security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY);
132 security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS);
133
134 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \
135 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) || \
136 security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV));
137
138 setup_rfi_flush(type, enable);
139 setup_count_cache_flush();
140
141 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
142 security_ftr_enabled(SEC_FTR_L1D_FLUSH_ENTRY);
143 setup_entry_flush(enable);
144
145 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
146 security_ftr_enabled(SEC_FTR_L1D_FLUSH_UACCESS);
147 setup_uaccess_flush(enable);
148 }
149
pnv_setup_arch(void)150 static void __init pnv_setup_arch(void)
151 {
152 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
153
154 pnv_setup_rfi_flush();
155 setup_stf_barrier();
156
157 /* Initialize SMP */
158 pnv_smp_init();
159
160 /* Setup PCI */
161 pnv_pci_init();
162
163 /* Setup RTC and NVRAM callbacks */
164 if (firmware_has_feature(FW_FEATURE_OPAL))
165 opal_nvram_init();
166
167 /* Enable NAP mode */
168 powersave_nap = 1;
169
170 /* XXX PMCS */
171 }
172
pnv_init_early(void)173 static void __init pnv_init_early(void)
174 {
175 /*
176 * Initialize the LPC bus now so that legacy serial
177 * ports can be found on it
178 */
179 opal_lpc_init();
180
181 #ifdef CONFIG_HVC_OPAL
182 if (firmware_has_feature(FW_FEATURE_OPAL))
183 hvc_opal_init_early();
184 else
185 #endif
186 add_preferred_console("hvc", 0, NULL);
187 }
188
pnv_init_IRQ(void)189 static void __init pnv_init_IRQ(void)
190 {
191 xics_init();
192
193 WARN_ON(!ppc_md.get_irq);
194 }
195
pnv_show_cpuinfo(struct seq_file * m)196 static void pnv_show_cpuinfo(struct seq_file *m)
197 {
198 struct device_node *root;
199 const char *model = "";
200
201 root = of_find_node_by_path("/");
202 if (root)
203 model = of_get_property(root, "model", NULL);
204 seq_printf(m, "machine\t\t: PowerNV %s\n", model);
205 if (firmware_has_feature(FW_FEATURE_OPAL))
206 seq_printf(m, "firmware\t: OPAL\n");
207 else
208 seq_printf(m, "firmware\t: BML\n");
209 of_node_put(root);
210 }
211
pnv_prepare_going_down(void)212 static void pnv_prepare_going_down(void)
213 {
214 /*
215 * Disable all notifiers from OPAL, we can't
216 * service interrupts anymore anyway
217 */
218 opal_event_shutdown();
219
220 /* Soft disable interrupts */
221 local_irq_disable();
222
223 /*
224 * Return secondary CPUs to firwmare if a flash update
225 * is pending otherwise we will get all sort of error
226 * messages about CPU being stuck etc.. This will also
227 * have the side effect of hard disabling interrupts so
228 * past this point, the kernel is effectively dead.
229 */
230 opal_flash_term_callback();
231 }
232
pnv_restart(char * cmd)233 static void __noreturn pnv_restart(char *cmd)
234 {
235 long rc = OPAL_BUSY;
236
237 pnv_prepare_going_down();
238
239 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
240 rc = opal_cec_reboot();
241 if (rc == OPAL_BUSY_EVENT)
242 opal_poll_events(NULL);
243 else
244 mdelay(10);
245 }
246 for (;;)
247 opal_poll_events(NULL);
248 }
249
pnv_power_off(void)250 static void __noreturn pnv_power_off(void)
251 {
252 long rc = OPAL_BUSY;
253
254 pnv_prepare_going_down();
255
256 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
257 rc = opal_cec_power_down(0);
258 if (rc == OPAL_BUSY_EVENT)
259 opal_poll_events(NULL);
260 else
261 mdelay(10);
262 }
263 for (;;)
264 opal_poll_events(NULL);
265 }
266
pnv_halt(void)267 static void __noreturn pnv_halt(void)
268 {
269 pnv_power_off();
270 }
271
pnv_progress(char * s,unsigned short hex)272 static void pnv_progress(char *s, unsigned short hex)
273 {
274 }
275
pnv_shutdown(void)276 static void pnv_shutdown(void)
277 {
278 /* Let the PCI code clear up IODA tables */
279 pnv_pci_shutdown();
280
281 /*
282 * Stop OPAL activity: Unregister all OPAL interrupts so they
283 * don't fire up while we kexec and make sure all potentially
284 * DMA'ing ops are complete (such as dump retrieval).
285 */
286 opal_shutdown();
287 }
288
289 #ifdef CONFIG_KEXEC
pnv_kexec_wait_secondaries_down(void)290 static void pnv_kexec_wait_secondaries_down(void)
291 {
292 int my_cpu, i, notified = -1;
293
294 my_cpu = get_cpu();
295
296 for_each_online_cpu(i) {
297 uint8_t status;
298 int64_t rc, timeout = 1000;
299
300 if (i == my_cpu)
301 continue;
302
303 for (;;) {
304 rc = opal_query_cpu_status(get_hard_smp_processor_id(i),
305 &status);
306 if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED)
307 break;
308 barrier();
309 if (i != notified) {
310 printk(KERN_INFO "kexec: waiting for cpu %d "
311 "(physical %d) to enter OPAL\n",
312 i, paca[i].hw_cpu_id);
313 notified = i;
314 }
315
316 /*
317 * On crash secondaries might be unreachable or hung,
318 * so timeout if we've waited too long
319 * */
320 mdelay(1);
321 if (timeout-- == 0) {
322 printk(KERN_ERR "kexec: timed out waiting for "
323 "cpu %d (physical %d) to enter OPAL\n",
324 i, paca[i].hw_cpu_id);
325 break;
326 }
327 }
328 }
329 }
330
pnv_kexec_cpu_down(int crash_shutdown,int secondary)331 static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
332 {
333 xics_kexec_teardown_cpu(secondary);
334
335 /* On OPAL, we return all CPUs to firmware */
336
337 if (!firmware_has_feature(FW_FEATURE_OPAL))
338 return;
339
340 if (secondary) {
341 /* Return secondary CPUs to firmware on OPAL v3 */
342 mb();
343 get_paca()->kexec_state = KEXEC_STATE_REAL_MODE;
344 mb();
345
346 /* Return the CPU to OPAL */
347 opal_return_cpu();
348 } else {
349 /* Primary waits for the secondaries to have reached OPAL */
350 pnv_kexec_wait_secondaries_down();
351
352 /*
353 * We might be running as little-endian - now that interrupts
354 * are disabled, reset the HILE bit to big-endian so we don't
355 * take interrupts in the wrong endian later
356 */
357 opal_reinit_cpus(OPAL_REINIT_CPUS_HILE_BE);
358 }
359 }
360 #endif /* CONFIG_KEXEC */
361
362 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
pnv_memory_block_size(void)363 static unsigned long pnv_memory_block_size(void)
364 {
365 return 256UL * 1024 * 1024;
366 }
367 #endif
368
pnv_setup_machdep_opal(void)369 static void __init pnv_setup_machdep_opal(void)
370 {
371 ppc_md.get_boot_time = opal_get_boot_time;
372 ppc_md.restart = pnv_restart;
373 pm_power_off = pnv_power_off;
374 ppc_md.halt = pnv_halt;
375 ppc_md.machine_check_exception = opal_machine_check;
376 ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;
377 ppc_md.hmi_exception_early = opal_hmi_exception_early;
378 ppc_md.handle_hmi_exception = opal_handle_hmi_exception;
379 }
380
pnv_probe(void)381 static int __init pnv_probe(void)
382 {
383 unsigned long root = of_get_flat_dt_root();
384
385 if (!of_flat_dt_is_compatible(root, "ibm,powernv"))
386 return 0;
387
388 hpte_init_native();
389
390 if (firmware_has_feature(FW_FEATURE_OPAL))
391 pnv_setup_machdep_opal();
392
393 pr_debug("PowerNV detected !\n");
394
395 return 1;
396 }
397
398 /*
399 * Returns the cpu frequency for 'cpu' in Hz. This is used by
400 * /proc/cpuinfo
401 */
pnv_get_proc_freq(unsigned int cpu)402 static unsigned long pnv_get_proc_freq(unsigned int cpu)
403 {
404 unsigned long ret_freq;
405
406 ret_freq = cpufreq_get(cpu) * 1000ul;
407
408 /*
409 * If the backend cpufreq driver does not exist,
410 * then fallback to old way of reporting the clockrate.
411 */
412 if (!ret_freq)
413 ret_freq = ppc_proc_freq;
414 return ret_freq;
415 }
416
define_machine(powernv)417 define_machine(powernv) {
418 .name = "PowerNV",
419 .probe = pnv_probe,
420 .init_early = pnv_init_early,
421 .setup_arch = pnv_setup_arch,
422 .init_IRQ = pnv_init_IRQ,
423 .show_cpuinfo = pnv_show_cpuinfo,
424 .get_proc_freq = pnv_get_proc_freq,
425 .progress = pnv_progress,
426 .machine_shutdown = pnv_shutdown,
427 .power_save = power7_idle,
428 .calibrate_decr = generic_calibrate_decr,
429 #ifdef CONFIG_KEXEC
430 .kexec_cpu_down = pnv_kexec_cpu_down,
431 #endif
432 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
433 .memory_block_size = pnv_memory_block_size,
434 #endif
435 };
436