1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/cpu-features.h>
24 #include <asm/cpu-type.h>
25 #include <asm/fpu.h>
26 #include <asm/mipsregs.h>
27 #include <asm/mipsmtregs.h>
28 #include <asm/msa.h>
29 #include <asm/watch.h>
30 #include <asm/elf.h>
31 #include <asm/pgtable-bits.h>
32 #include <asm/spram.h>
33 #include <asm/uaccess.h>
34
35 /* Hardware capabilities */
36 unsigned int elf_hwcap __read_mostly;
37
38 /*
39 * Get the FPU Implementation/Revision.
40 */
cpu_get_fpu_id(void)41 static inline unsigned long cpu_get_fpu_id(void)
42 {
43 unsigned long tmp, fpu_id;
44
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
48 write_c0_status(tmp);
49 return fpu_id;
50 }
51
52 /*
53 * Check if the CPU has an external FPU.
54 */
__cpu_has_fpu(void)55 static inline int __cpu_has_fpu(void)
56 {
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
58 }
59
cpu_get_msa_id(void)60 static inline unsigned long cpu_get_msa_id(void)
61 {
62 unsigned long status, msa_id;
63
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
66 enable_msa();
67 msa_id = read_msa_ir();
68 disable_msa();
69 write_c0_status(status);
70 return msa_id;
71 }
72
73 /*
74 * Determine the FCSR mask for FPU hardware.
75 */
cpu_set_fpu_fcsr_mask(struct cpuinfo_mips * c)76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
77 {
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
79
80 fcsr = c->fpu_csr31;
81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
82
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
85
86 fcsr0 = fcsr & mask;
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
89
90 fcsr1 = fcsr | ~mask;
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
93
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
95
96 write_c0_status(sr);
97
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
99 }
100
101 /*
102 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
103 * supported by FPU hardware.
104 */
cpu_set_fpu_2008(struct cpuinfo_mips * c)105 static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
106 {
107 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
108 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
109 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
110 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
111
112 sr = read_c0_status();
113 __enable_fpu(FPU_AS_IS);
114
115 fir = read_32bit_cp1_register(CP1_REVISION);
116 if (fir & MIPS_FPIR_HAS2008) {
117 fcsr = read_32bit_cp1_register(CP1_STATUS);
118
119 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
120 write_32bit_cp1_register(CP1_STATUS, fcsr0);
121 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
122
123 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
124 write_32bit_cp1_register(CP1_STATUS, fcsr1);
125 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
126
127 write_32bit_cp1_register(CP1_STATUS, fcsr);
128
129 if (!(fcsr0 & FPU_CSR_NAN2008))
130 c->options |= MIPS_CPU_NAN_LEGACY;
131 if (fcsr1 & FPU_CSR_NAN2008)
132 c->options |= MIPS_CPU_NAN_2008;
133
134 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
135 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
136 else
137 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
138
139 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
140 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
141 else
142 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
143 } else {
144 c->options |= MIPS_CPU_NAN_LEGACY;
145 }
146
147 write_c0_status(sr);
148 } else {
149 c->options |= MIPS_CPU_NAN_LEGACY;
150 }
151 }
152
153 /*
154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
155 * ABS.fmt/NEG.fmt execution mode.
156 */
157 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
158
159 /*
160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
161 * to support by the FPU emulator according to the IEEE 754 conformance
162 * mode selected. Note that "relaxed" straps the emulator so that it
163 * allows 2008-NaN binaries even for legacy processors.
164 */
cpu_set_nofpu_2008(struct cpuinfo_mips * c)165 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
166 {
167 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
168 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
169 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
170
171 switch (ieee754) {
172 case STRICT:
173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
175 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
176 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
177 } else {
178 c->options |= MIPS_CPU_NAN_LEGACY;
179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
180 }
181 break;
182 case LEGACY:
183 c->options |= MIPS_CPU_NAN_LEGACY;
184 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
185 break;
186 case STD2008:
187 c->options |= MIPS_CPU_NAN_2008;
188 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
189 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
190 break;
191 case RELAXED:
192 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
193 break;
194 }
195 }
196
197 /*
198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
199 * according to the "ieee754=" parameter.
200 */
cpu_set_nan_2008(struct cpuinfo_mips * c)201 static void cpu_set_nan_2008(struct cpuinfo_mips *c)
202 {
203 switch (ieee754) {
204 case STRICT:
205 mips_use_nan_legacy = !!cpu_has_nan_legacy;
206 mips_use_nan_2008 = !!cpu_has_nan_2008;
207 break;
208 case LEGACY:
209 mips_use_nan_legacy = !!cpu_has_nan_legacy;
210 mips_use_nan_2008 = !cpu_has_nan_legacy;
211 break;
212 case STD2008:
213 mips_use_nan_legacy = !cpu_has_nan_2008;
214 mips_use_nan_2008 = !!cpu_has_nan_2008;
215 break;
216 case RELAXED:
217 mips_use_nan_legacy = true;
218 mips_use_nan_2008 = true;
219 break;
220 }
221 }
222
223 /*
224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
225 * settings:
226 *
227 * strict: accept binaries that request a NaN encoding supported by the FPU
228 * legacy: only accept legacy-NaN binaries
229 * 2008: only accept 2008-NaN binaries
230 * relaxed: accept any binaries regardless of whether supported by the FPU
231 */
ieee754_setup(char * s)232 static int __init ieee754_setup(char *s)
233 {
234 if (!s)
235 return -1;
236 else if (!strcmp(s, "strict"))
237 ieee754 = STRICT;
238 else if (!strcmp(s, "legacy"))
239 ieee754 = LEGACY;
240 else if (!strcmp(s, "2008"))
241 ieee754 = STD2008;
242 else if (!strcmp(s, "relaxed"))
243 ieee754 = RELAXED;
244 else
245 return -1;
246
247 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
248 cpu_set_nofpu_2008(&boot_cpu_data);
249 cpu_set_nan_2008(&boot_cpu_data);
250
251 return 0;
252 }
253
254 early_param("ieee754", ieee754_setup);
255
256 /*
257 * Set the FIR feature flags for the FPU emulator.
258 */
cpu_set_nofpu_id(struct cpuinfo_mips * c)259 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
260 {
261 u32 value;
262
263 value = 0;
264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
266 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
267 value |= MIPS_FPIR_D | MIPS_FPIR_S;
268 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
269 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
270 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
271 if (c->options & MIPS_CPU_NAN_2008)
272 value |= MIPS_FPIR_HAS2008;
273 c->fpu_id = value;
274 }
275
276 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
277 static unsigned int mips_nofpu_msk31;
278
279 /*
280 * Set options for FPU hardware.
281 */
cpu_set_fpu_opts(struct cpuinfo_mips * c)282 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
283 {
284 c->fpu_id = cpu_get_fpu_id();
285 mips_nofpu_msk31 = c->fpu_msk31;
286
287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
289 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
290 if (c->fpu_id & MIPS_FPIR_3D)
291 c->ases |= MIPS_ASE_MIPS3D;
292 if (c->fpu_id & MIPS_FPIR_FREP)
293 c->options |= MIPS_CPU_FRE;
294 }
295
296 cpu_set_fpu_fcsr_mask(c);
297 cpu_set_fpu_2008(c);
298 cpu_set_nan_2008(c);
299 }
300
301 /*
302 * Set options for the FPU emulator.
303 */
cpu_set_nofpu_opts(struct cpuinfo_mips * c)304 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
305 {
306 c->options &= ~MIPS_CPU_FPU;
307 c->fpu_msk31 = mips_nofpu_msk31;
308
309 cpu_set_nofpu_2008(c);
310 cpu_set_nan_2008(c);
311 cpu_set_nofpu_id(c);
312 }
313
314 static int mips_fpu_disabled;
315
fpu_disable(char * s)316 static int __init fpu_disable(char *s)
317 {
318 cpu_set_nofpu_opts(&boot_cpu_data);
319 mips_fpu_disabled = 1;
320
321 return 1;
322 }
323
324 __setup("nofpu", fpu_disable);
325
326 int mips_dsp_disabled;
327
dsp_disable(char * s)328 static int __init dsp_disable(char *s)
329 {
330 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
331 mips_dsp_disabled = 1;
332
333 return 1;
334 }
335
336 __setup("nodsp", dsp_disable);
337
338 static int mips_htw_disabled;
339
htw_disable(char * s)340 static int __init htw_disable(char *s)
341 {
342 mips_htw_disabled = 1;
343 cpu_data[0].options &= ~MIPS_CPU_HTW;
344 write_c0_pwctl(read_c0_pwctl() &
345 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
346
347 return 1;
348 }
349
350 __setup("nohtw", htw_disable);
351
352 static int mips_ftlb_disabled;
353 static int mips_has_ftlb_configured;
354
355 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
356
ftlb_disable(char * s)357 static int __init ftlb_disable(char *s)
358 {
359 unsigned int config4, mmuextdef;
360
361 /*
362 * If the core hasn't done any FTLB configuration, there is nothing
363 * for us to do here.
364 */
365 if (!mips_has_ftlb_configured)
366 return 1;
367
368 /* Disable it in the boot cpu */
369 if (set_ftlb_enable(&cpu_data[0], 0)) {
370 pr_warn("Can't turn FTLB off\n");
371 return 1;
372 }
373
374 back_to_back_c0_hazard();
375
376 config4 = read_c0_config4();
377
378 /* Check that FTLB has been disabled */
379 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
380 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
381 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
382 /* This should never happen */
383 pr_warn("FTLB could not be disabled!\n");
384 return 1;
385 }
386
387 mips_ftlb_disabled = 1;
388 mips_has_ftlb_configured = 0;
389
390 /*
391 * noftlb is mainly used for debug purposes so print
392 * an informative message instead of using pr_debug()
393 */
394 pr_info("FTLB has been disabled\n");
395
396 /*
397 * Some of these bits are duplicated in the decode_config4.
398 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
399 * once FTLB has been disabled so undo what decode_config4 did.
400 */
401 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
402 cpu_data[0].tlbsizeftlbsets;
403 cpu_data[0].tlbsizeftlbsets = 0;
404 cpu_data[0].tlbsizeftlbways = 0;
405
406 return 1;
407 }
408
409 __setup("noftlb", ftlb_disable);
410
411
check_errata(void)412 static inline void check_errata(void)
413 {
414 struct cpuinfo_mips *c = ¤t_cpu_data;
415
416 switch (current_cpu_type()) {
417 case CPU_34K:
418 /*
419 * Erratum "RPS May Cause Incorrect Instruction Execution"
420 * This code only handles VPE0, any SMP/RTOS code
421 * making use of VPE1 will be responsable for that VPE.
422 */
423 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
424 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
425 break;
426 default:
427 break;
428 }
429 }
430
check_bugs32(void)431 void __init check_bugs32(void)
432 {
433 check_errata();
434 }
435
436 /*
437 * Probe whether cpu has config register by trying to play with
438 * alternate cache bit and see whether it matters.
439 * It's used by cpu_probe to distinguish between R3000A and R3081.
440 */
cpu_has_confreg(void)441 static inline int cpu_has_confreg(void)
442 {
443 #ifdef CONFIG_CPU_R3000
444 extern unsigned long r3k_cache_size(unsigned long);
445 unsigned long size1, size2;
446 unsigned long cfg = read_c0_conf();
447
448 size1 = r3k_cache_size(ST0_ISC);
449 write_c0_conf(cfg ^ R30XX_CONF_AC);
450 size2 = r3k_cache_size(ST0_ISC);
451 write_c0_conf(cfg);
452 return size1 != size2;
453 #else
454 return 0;
455 #endif
456 }
457
set_elf_platform(int cpu,const char * plat)458 static inline void set_elf_platform(int cpu, const char *plat)
459 {
460 if (cpu == 0)
461 __elf_platform = plat;
462 }
463
cpu_probe_vmbits(struct cpuinfo_mips * c)464 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
465 {
466 #ifdef __NEED_VMBITS_PROBE
467 write_c0_entryhi(0x3fffffffffffe000ULL);
468 back_to_back_c0_hazard();
469 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
470 #endif
471 }
472
set_isa(struct cpuinfo_mips * c,unsigned int isa)473 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
474 {
475 switch (isa) {
476 case MIPS_CPU_ISA_M64R2:
477 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
478 case MIPS_CPU_ISA_M64R1:
479 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
480 case MIPS_CPU_ISA_V:
481 c->isa_level |= MIPS_CPU_ISA_V;
482 case MIPS_CPU_ISA_IV:
483 c->isa_level |= MIPS_CPU_ISA_IV;
484 case MIPS_CPU_ISA_III:
485 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
486 break;
487
488 /* R6 incompatible with everything else */
489 case MIPS_CPU_ISA_M64R6:
490 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
491 case MIPS_CPU_ISA_M32R6:
492 c->isa_level |= MIPS_CPU_ISA_M32R6;
493 /* Break here so we don't add incompatible ISAs */
494 break;
495 case MIPS_CPU_ISA_M32R2:
496 c->isa_level |= MIPS_CPU_ISA_M32R2;
497 case MIPS_CPU_ISA_M32R1:
498 c->isa_level |= MIPS_CPU_ISA_M32R1;
499 case MIPS_CPU_ISA_II:
500 c->isa_level |= MIPS_CPU_ISA_II;
501 break;
502 }
503 }
504
505 static char unknown_isa[] = KERN_ERR \
506 "Unsupported ISA type, c0.config0: %d.";
507
calculate_ftlb_probability(struct cpuinfo_mips * c)508 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
509 {
510
511 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
512
513 /*
514 * 0 = All TLBWR instructions go to FTLB
515 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
516 * FTLB and 1 goes to the VTLB.
517 * 2 = 7:1: As above with 7:1 ratio.
518 * 3 = 3:1: As above with 3:1 ratio.
519 *
520 * Use the linear midpoint as the probability threshold.
521 */
522 if (probability >= 12)
523 return 1;
524 else if (probability >= 6)
525 return 2;
526 else
527 /*
528 * So FTLB is less than 4 times bigger than VTLB.
529 * A 3:1 ratio can still be useful though.
530 */
531 return 3;
532 }
533
set_ftlb_enable(struct cpuinfo_mips * c,int enable)534 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
535 {
536 unsigned int config;
537
538 /* It's implementation dependent how the FTLB can be enabled */
539 switch (c->cputype) {
540 case CPU_PROAPTIV:
541 case CPU_P5600:
542 /* proAptiv & related cores use Config6 to enable the FTLB */
543 config = read_c0_config6();
544 /* Clear the old probability value */
545 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
546 if (enable)
547 /* Enable FTLB */
548 write_c0_config6(config |
549 (calculate_ftlb_probability(c)
550 << MIPS_CONF6_FTLBP_SHIFT)
551 | MIPS_CONF6_FTLBEN);
552 else
553 /* Disable FTLB */
554 write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
555 break;
556 case CPU_I6400:
557 /* I6400 & related cores use Config7 to configure FTLB */
558 config = read_c0_config7();
559 /* Clear the old probability value */
560 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
561 write_c0_config7(config | (calculate_ftlb_probability(c)
562 << MIPS_CONF7_FTLBP_SHIFT));
563 break;
564 default:
565 return 1;
566 }
567
568 return 0;
569 }
570
decode_config0(struct cpuinfo_mips * c)571 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
572 {
573 unsigned int config0;
574 int isa, mt;
575
576 config0 = read_c0_config();
577
578 /*
579 * Look for Standard TLB or Dual VTLB and FTLB
580 */
581 mt = config0 & MIPS_CONF_MT;
582 if (mt == MIPS_CONF_MT_TLB)
583 c->options |= MIPS_CPU_TLB;
584 else if (mt == MIPS_CONF_MT_FTLB)
585 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
586
587 isa = (config0 & MIPS_CONF_AT) >> 13;
588 switch (isa) {
589 case 0:
590 switch ((config0 & MIPS_CONF_AR) >> 10) {
591 case 0:
592 set_isa(c, MIPS_CPU_ISA_M32R1);
593 break;
594 case 1:
595 set_isa(c, MIPS_CPU_ISA_M32R2);
596 break;
597 case 2:
598 set_isa(c, MIPS_CPU_ISA_M32R6);
599 break;
600 default:
601 goto unknown;
602 }
603 break;
604 case 2:
605 switch ((config0 & MIPS_CONF_AR) >> 10) {
606 case 0:
607 set_isa(c, MIPS_CPU_ISA_M64R1);
608 break;
609 case 1:
610 set_isa(c, MIPS_CPU_ISA_M64R2);
611 break;
612 case 2:
613 set_isa(c, MIPS_CPU_ISA_M64R6);
614 break;
615 default:
616 goto unknown;
617 }
618 break;
619 default:
620 goto unknown;
621 }
622
623 return config0 & MIPS_CONF_M;
624
625 unknown:
626 panic(unknown_isa, config0);
627 }
628
decode_config1(struct cpuinfo_mips * c)629 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
630 {
631 unsigned int config1;
632
633 config1 = read_c0_config1();
634
635 if (config1 & MIPS_CONF1_MD)
636 c->ases |= MIPS_ASE_MDMX;
637 if (config1 & MIPS_CONF1_WR)
638 c->options |= MIPS_CPU_WATCH;
639 if (config1 & MIPS_CONF1_CA)
640 c->ases |= MIPS_ASE_MIPS16;
641 if (config1 & MIPS_CONF1_EP)
642 c->options |= MIPS_CPU_EJTAG;
643 if (config1 & MIPS_CONF1_FP) {
644 c->options |= MIPS_CPU_FPU;
645 c->options |= MIPS_CPU_32FPR;
646 }
647 if (cpu_has_tlb) {
648 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
649 c->tlbsizevtlb = c->tlbsize;
650 c->tlbsizeftlbsets = 0;
651 }
652
653 return config1 & MIPS_CONF_M;
654 }
655
decode_config2(struct cpuinfo_mips * c)656 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
657 {
658 unsigned int config2;
659
660 config2 = read_c0_config2();
661
662 if (config2 & MIPS_CONF2_SL)
663 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
664
665 return config2 & MIPS_CONF_M;
666 }
667
decode_config3(struct cpuinfo_mips * c)668 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
669 {
670 unsigned int config3;
671
672 config3 = read_c0_config3();
673
674 if (config3 & MIPS_CONF3_SM) {
675 c->ases |= MIPS_ASE_SMARTMIPS;
676 c->options |= MIPS_CPU_RIXI;
677 }
678 if (config3 & MIPS_CONF3_RXI)
679 c->options |= MIPS_CPU_RIXI;
680 if (config3 & MIPS_CONF3_DSP)
681 c->ases |= MIPS_ASE_DSP;
682 if (config3 & MIPS_CONF3_DSP2P)
683 c->ases |= MIPS_ASE_DSP2P;
684 if (config3 & MIPS_CONF3_VINT)
685 c->options |= MIPS_CPU_VINT;
686 if (config3 & MIPS_CONF3_VEIC)
687 c->options |= MIPS_CPU_VEIC;
688 if (config3 & MIPS_CONF3_MT)
689 c->ases |= MIPS_ASE_MIPSMT;
690 if (config3 & MIPS_CONF3_ULRI)
691 c->options |= MIPS_CPU_ULRI;
692 if (config3 & MIPS_CONF3_ISA)
693 c->options |= MIPS_CPU_MICROMIPS;
694 if (config3 & MIPS_CONF3_VZ)
695 c->ases |= MIPS_ASE_VZ;
696 if (config3 & MIPS_CONF3_SC)
697 c->options |= MIPS_CPU_SEGMENTS;
698 if (config3 & MIPS_CONF3_MSA)
699 c->ases |= MIPS_ASE_MSA;
700 if (config3 & MIPS_CONF3_PW) {
701 c->htw_seq = 0;
702 c->options |= MIPS_CPU_HTW;
703 }
704 if (config3 & MIPS_CONF3_CDMM)
705 c->options |= MIPS_CPU_CDMM;
706 if (config3 & MIPS_CONF3_SP)
707 c->options |= MIPS_CPU_SP;
708
709 return config3 & MIPS_CONF_M;
710 }
711
decode_config4(struct cpuinfo_mips * c)712 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
713 {
714 unsigned int config4;
715 unsigned int newcf4;
716 unsigned int mmuextdef;
717 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
718
719 config4 = read_c0_config4();
720
721 if (cpu_has_tlb) {
722 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
723 c->options |= MIPS_CPU_TLBINV;
724
725 /*
726 * R6 has dropped the MMUExtDef field from config4.
727 * On R6 the fields always describe the FTLB, and only if it is
728 * present according to Config.MT.
729 */
730 if (!cpu_has_mips_r6)
731 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
732 else if (cpu_has_ftlb)
733 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
734 else
735 mmuextdef = 0;
736
737 switch (mmuextdef) {
738 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
739 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
740 c->tlbsizevtlb = c->tlbsize;
741 break;
742 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
743 c->tlbsizevtlb +=
744 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
745 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
746 c->tlbsize = c->tlbsizevtlb;
747 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
748 /* fall through */
749 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
750 if (mips_ftlb_disabled)
751 break;
752 newcf4 = (config4 & ~ftlb_page) |
753 (page_size_ftlb(mmuextdef) <<
754 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
755 write_c0_config4(newcf4);
756 back_to_back_c0_hazard();
757 config4 = read_c0_config4();
758 if (config4 != newcf4) {
759 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
760 PAGE_SIZE, config4);
761 /* Switch FTLB off */
762 set_ftlb_enable(c, 0);
763 break;
764 }
765 c->tlbsizeftlbsets = 1 <<
766 ((config4 & MIPS_CONF4_FTLBSETS) >>
767 MIPS_CONF4_FTLBSETS_SHIFT);
768 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
769 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
770 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
771 mips_has_ftlb_configured = 1;
772 break;
773 }
774 }
775
776 c->kscratch_mask = (config4 >> 16) & 0xff;
777
778 return config4 & MIPS_CONF_M;
779 }
780
decode_config5(struct cpuinfo_mips * c)781 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
782 {
783 unsigned int config5;
784
785 config5 = read_c0_config5();
786 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
787 write_c0_config5(config5);
788
789 if (config5 & MIPS_CONF5_EVA)
790 c->options |= MIPS_CPU_EVA;
791 if (config5 & MIPS_CONF5_MRP)
792 c->options |= MIPS_CPU_MAAR;
793 if (config5 & MIPS_CONF5_LLB)
794 c->options |= MIPS_CPU_RW_LLB;
795 #ifdef CONFIG_XPA
796 if (config5 & MIPS_CONF5_MVH)
797 c->options |= MIPS_CPU_XPA;
798 #endif
799 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
800 c->options |= MIPS_CPU_VP;
801
802 return config5 & MIPS_CONF_M;
803 }
804
decode_configs(struct cpuinfo_mips * c)805 static void decode_configs(struct cpuinfo_mips *c)
806 {
807 int ok;
808
809 /* MIPS32 or MIPS64 compliant CPU. */
810 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
811 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
812
813 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
814
815 /* Enable FTLB if present and not disabled */
816 set_ftlb_enable(c, !mips_ftlb_disabled);
817
818 ok = decode_config0(c); /* Read Config registers. */
819 BUG_ON(!ok); /* Arch spec violation! */
820 if (ok)
821 ok = decode_config1(c);
822 if (ok)
823 ok = decode_config2(c);
824 if (ok)
825 ok = decode_config3(c);
826 if (ok)
827 ok = decode_config4(c);
828 if (ok)
829 ok = decode_config5(c);
830
831 mips_probe_watch_registers(c);
832
833 if (cpu_has_rixi) {
834 /* Enable the RIXI exceptions */
835 set_c0_pagegrain(PG_IEC);
836 back_to_back_c0_hazard();
837 /* Verify the IEC bit is set */
838 if (read_c0_pagegrain() & PG_IEC)
839 c->options |= MIPS_CPU_RIXIEX;
840 }
841
842 #ifndef CONFIG_MIPS_CPS
843 if (cpu_has_mips_r2_r6) {
844 c->core = get_ebase_cpunum();
845 if (cpu_has_mipsmt)
846 c->core >>= fls(core_nvpes()) - 1;
847 }
848 #endif
849 }
850
851 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
852 | MIPS_CPU_COUNTER)
853
cpu_probe_legacy(struct cpuinfo_mips * c,unsigned int cpu)854 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
855 {
856 switch (c->processor_id & PRID_IMP_MASK) {
857 case PRID_IMP_R2000:
858 c->cputype = CPU_R2000;
859 __cpu_name[cpu] = "R2000";
860 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
861 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
862 MIPS_CPU_NOFPUEX;
863 if (__cpu_has_fpu())
864 c->options |= MIPS_CPU_FPU;
865 c->tlbsize = 64;
866 break;
867 case PRID_IMP_R3000:
868 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
869 if (cpu_has_confreg()) {
870 c->cputype = CPU_R3081E;
871 __cpu_name[cpu] = "R3081";
872 } else {
873 c->cputype = CPU_R3000A;
874 __cpu_name[cpu] = "R3000A";
875 }
876 } else {
877 c->cputype = CPU_R3000;
878 __cpu_name[cpu] = "R3000";
879 }
880 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
881 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
882 MIPS_CPU_NOFPUEX;
883 if (__cpu_has_fpu())
884 c->options |= MIPS_CPU_FPU;
885 c->tlbsize = 64;
886 break;
887 case PRID_IMP_R4000:
888 if (read_c0_config() & CONF_SC) {
889 if ((c->processor_id & PRID_REV_MASK) >=
890 PRID_REV_R4400) {
891 c->cputype = CPU_R4400PC;
892 __cpu_name[cpu] = "R4400PC";
893 } else {
894 c->cputype = CPU_R4000PC;
895 __cpu_name[cpu] = "R4000PC";
896 }
897 } else {
898 int cca = read_c0_config() & CONF_CM_CMASK;
899 int mc;
900
901 /*
902 * SC and MC versions can't be reliably told apart,
903 * but only the latter support coherent caching
904 * modes so assume the firmware has set the KSEG0
905 * coherency attribute reasonably (if uncached, we
906 * assume SC).
907 */
908 switch (cca) {
909 case CONF_CM_CACHABLE_CE:
910 case CONF_CM_CACHABLE_COW:
911 case CONF_CM_CACHABLE_CUW:
912 mc = 1;
913 break;
914 default:
915 mc = 0;
916 break;
917 }
918 if ((c->processor_id & PRID_REV_MASK) >=
919 PRID_REV_R4400) {
920 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
921 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
922 } else {
923 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
924 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
925 }
926 }
927
928 set_isa(c, MIPS_CPU_ISA_III);
929 c->fpu_msk31 |= FPU_CSR_CONDX;
930 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
931 MIPS_CPU_WATCH | MIPS_CPU_VCE |
932 MIPS_CPU_LLSC;
933 c->tlbsize = 48;
934 break;
935 case PRID_IMP_VR41XX:
936 set_isa(c, MIPS_CPU_ISA_III);
937 c->fpu_msk31 |= FPU_CSR_CONDX;
938 c->options = R4K_OPTS;
939 c->tlbsize = 32;
940 switch (c->processor_id & 0xf0) {
941 case PRID_REV_VR4111:
942 c->cputype = CPU_VR4111;
943 __cpu_name[cpu] = "NEC VR4111";
944 break;
945 case PRID_REV_VR4121:
946 c->cputype = CPU_VR4121;
947 __cpu_name[cpu] = "NEC VR4121";
948 break;
949 case PRID_REV_VR4122:
950 if ((c->processor_id & 0xf) < 0x3) {
951 c->cputype = CPU_VR4122;
952 __cpu_name[cpu] = "NEC VR4122";
953 } else {
954 c->cputype = CPU_VR4181A;
955 __cpu_name[cpu] = "NEC VR4181A";
956 }
957 break;
958 case PRID_REV_VR4130:
959 if ((c->processor_id & 0xf) < 0x4) {
960 c->cputype = CPU_VR4131;
961 __cpu_name[cpu] = "NEC VR4131";
962 } else {
963 c->cputype = CPU_VR4133;
964 c->options |= MIPS_CPU_LLSC;
965 __cpu_name[cpu] = "NEC VR4133";
966 }
967 break;
968 default:
969 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
970 c->cputype = CPU_VR41XX;
971 __cpu_name[cpu] = "NEC Vr41xx";
972 break;
973 }
974 break;
975 case PRID_IMP_R4300:
976 c->cputype = CPU_R4300;
977 __cpu_name[cpu] = "R4300";
978 set_isa(c, MIPS_CPU_ISA_III);
979 c->fpu_msk31 |= FPU_CSR_CONDX;
980 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
981 MIPS_CPU_LLSC;
982 c->tlbsize = 32;
983 break;
984 case PRID_IMP_R4600:
985 c->cputype = CPU_R4600;
986 __cpu_name[cpu] = "R4600";
987 set_isa(c, MIPS_CPU_ISA_III);
988 c->fpu_msk31 |= FPU_CSR_CONDX;
989 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
990 MIPS_CPU_LLSC;
991 c->tlbsize = 48;
992 break;
993 #if 0
994 case PRID_IMP_R4650:
995 /*
996 * This processor doesn't have an MMU, so it's not
997 * "real easy" to run Linux on it. It is left purely
998 * for documentation. Commented out because it shares
999 * it's c0_prid id number with the TX3900.
1000 */
1001 c->cputype = CPU_R4650;
1002 __cpu_name[cpu] = "R4650";
1003 set_isa(c, MIPS_CPU_ISA_III);
1004 c->fpu_msk31 |= FPU_CSR_CONDX;
1005 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1006 c->tlbsize = 48;
1007 break;
1008 #endif
1009 case PRID_IMP_TX39:
1010 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1011 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1012
1013 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1014 c->cputype = CPU_TX3927;
1015 __cpu_name[cpu] = "TX3927";
1016 c->tlbsize = 64;
1017 } else {
1018 switch (c->processor_id & PRID_REV_MASK) {
1019 case PRID_REV_TX3912:
1020 c->cputype = CPU_TX3912;
1021 __cpu_name[cpu] = "TX3912";
1022 c->tlbsize = 32;
1023 break;
1024 case PRID_REV_TX3922:
1025 c->cputype = CPU_TX3922;
1026 __cpu_name[cpu] = "TX3922";
1027 c->tlbsize = 64;
1028 break;
1029 }
1030 }
1031 break;
1032 case PRID_IMP_R4700:
1033 c->cputype = CPU_R4700;
1034 __cpu_name[cpu] = "R4700";
1035 set_isa(c, MIPS_CPU_ISA_III);
1036 c->fpu_msk31 |= FPU_CSR_CONDX;
1037 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1038 MIPS_CPU_LLSC;
1039 c->tlbsize = 48;
1040 break;
1041 case PRID_IMP_TX49:
1042 c->cputype = CPU_TX49XX;
1043 __cpu_name[cpu] = "R49XX";
1044 set_isa(c, MIPS_CPU_ISA_III);
1045 c->fpu_msk31 |= FPU_CSR_CONDX;
1046 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1047 if (!(c->processor_id & 0x08))
1048 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1049 c->tlbsize = 48;
1050 break;
1051 case PRID_IMP_R5000:
1052 c->cputype = CPU_R5000;
1053 __cpu_name[cpu] = "R5000";
1054 set_isa(c, MIPS_CPU_ISA_IV);
1055 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1056 MIPS_CPU_LLSC;
1057 c->tlbsize = 48;
1058 break;
1059 case PRID_IMP_R5432:
1060 c->cputype = CPU_R5432;
1061 __cpu_name[cpu] = "R5432";
1062 set_isa(c, MIPS_CPU_ISA_IV);
1063 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1064 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1065 c->tlbsize = 48;
1066 break;
1067 case PRID_IMP_R5500:
1068 c->cputype = CPU_R5500;
1069 __cpu_name[cpu] = "R5500";
1070 set_isa(c, MIPS_CPU_ISA_IV);
1071 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1072 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1073 c->tlbsize = 48;
1074 break;
1075 case PRID_IMP_NEVADA:
1076 c->cputype = CPU_NEVADA;
1077 __cpu_name[cpu] = "Nevada";
1078 set_isa(c, MIPS_CPU_ISA_IV);
1079 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1080 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1081 c->tlbsize = 48;
1082 break;
1083 case PRID_IMP_R6000:
1084 c->cputype = CPU_R6000;
1085 __cpu_name[cpu] = "R6000";
1086 set_isa(c, MIPS_CPU_ISA_II);
1087 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1088 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
1089 MIPS_CPU_LLSC;
1090 c->tlbsize = 32;
1091 break;
1092 case PRID_IMP_R6000A:
1093 c->cputype = CPU_R6000A;
1094 __cpu_name[cpu] = "R6000A";
1095 set_isa(c, MIPS_CPU_ISA_II);
1096 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1097 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
1098 MIPS_CPU_LLSC;
1099 c->tlbsize = 32;
1100 break;
1101 case PRID_IMP_RM7000:
1102 c->cputype = CPU_RM7000;
1103 __cpu_name[cpu] = "RM7000";
1104 set_isa(c, MIPS_CPU_ISA_IV);
1105 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1106 MIPS_CPU_LLSC;
1107 /*
1108 * Undocumented RM7000: Bit 29 in the info register of
1109 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1110 * entries.
1111 *
1112 * 29 1 => 64 entry JTLB
1113 * 0 => 48 entry JTLB
1114 */
1115 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1116 break;
1117 case PRID_IMP_R8000:
1118 c->cputype = CPU_R8000;
1119 __cpu_name[cpu] = "RM8000";
1120 set_isa(c, MIPS_CPU_ISA_IV);
1121 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1122 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1123 MIPS_CPU_LLSC;
1124 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1125 break;
1126 case PRID_IMP_R10000:
1127 c->cputype = CPU_R10000;
1128 __cpu_name[cpu] = "R10000";
1129 set_isa(c, MIPS_CPU_ISA_IV);
1130 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1131 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1132 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1133 MIPS_CPU_LLSC;
1134 c->tlbsize = 64;
1135 break;
1136 case PRID_IMP_R12000:
1137 c->cputype = CPU_R12000;
1138 __cpu_name[cpu] = "R12000";
1139 set_isa(c, MIPS_CPU_ISA_IV);
1140 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1141 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1142 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1143 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1144 c->tlbsize = 64;
1145 break;
1146 case PRID_IMP_R14000:
1147 if (((c->processor_id >> 4) & 0x0f) > 2) {
1148 c->cputype = CPU_R16000;
1149 __cpu_name[cpu] = "R16000";
1150 } else {
1151 c->cputype = CPU_R14000;
1152 __cpu_name[cpu] = "R14000";
1153 }
1154 set_isa(c, MIPS_CPU_ISA_IV);
1155 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1156 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1157 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1158 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1159 c->tlbsize = 64;
1160 break;
1161 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1162 switch (c->processor_id & PRID_REV_MASK) {
1163 case PRID_REV_LOONGSON2E:
1164 c->cputype = CPU_LOONGSON2;
1165 __cpu_name[cpu] = "ICT Loongson-2";
1166 set_elf_platform(cpu, "loongson2e");
1167 set_isa(c, MIPS_CPU_ISA_III);
1168 c->fpu_msk31 |= FPU_CSR_CONDX;
1169 break;
1170 case PRID_REV_LOONGSON2F:
1171 c->cputype = CPU_LOONGSON2;
1172 __cpu_name[cpu] = "ICT Loongson-2";
1173 set_elf_platform(cpu, "loongson2f");
1174 set_isa(c, MIPS_CPU_ISA_III);
1175 c->fpu_msk31 |= FPU_CSR_CONDX;
1176 break;
1177 case PRID_REV_LOONGSON3A:
1178 c->cputype = CPU_LOONGSON3;
1179 __cpu_name[cpu] = "ICT Loongson-3";
1180 set_elf_platform(cpu, "loongson3a");
1181 set_isa(c, MIPS_CPU_ISA_M64R1);
1182 break;
1183 case PRID_REV_LOONGSON3B_R1:
1184 case PRID_REV_LOONGSON3B_R2:
1185 c->cputype = CPU_LOONGSON3;
1186 __cpu_name[cpu] = "ICT Loongson-3";
1187 set_elf_platform(cpu, "loongson3b");
1188 set_isa(c, MIPS_CPU_ISA_M64R1);
1189 break;
1190 }
1191
1192 c->options = R4K_OPTS |
1193 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1194 MIPS_CPU_32FPR;
1195 c->tlbsize = 64;
1196 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1197 break;
1198 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1199 decode_configs(c);
1200
1201 c->cputype = CPU_LOONGSON1;
1202
1203 switch (c->processor_id & PRID_REV_MASK) {
1204 case PRID_REV_LOONGSON1B:
1205 __cpu_name[cpu] = "Loongson 1B";
1206 break;
1207 }
1208
1209 break;
1210 }
1211 }
1212
cpu_probe_mips(struct cpuinfo_mips * c,unsigned int cpu)1213 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1214 {
1215 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1216 switch (c->processor_id & PRID_IMP_MASK) {
1217 case PRID_IMP_QEMU_GENERIC:
1218 c->writecombine = _CACHE_UNCACHED;
1219 c->cputype = CPU_QEMU_GENERIC;
1220 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1221 break;
1222 case PRID_IMP_4KC:
1223 c->cputype = CPU_4KC;
1224 c->writecombine = _CACHE_UNCACHED;
1225 __cpu_name[cpu] = "MIPS 4Kc";
1226 break;
1227 case PRID_IMP_4KEC:
1228 case PRID_IMP_4KECR2:
1229 c->cputype = CPU_4KEC;
1230 c->writecombine = _CACHE_UNCACHED;
1231 __cpu_name[cpu] = "MIPS 4KEc";
1232 break;
1233 case PRID_IMP_4KSC:
1234 case PRID_IMP_4KSD:
1235 c->cputype = CPU_4KSC;
1236 c->writecombine = _CACHE_UNCACHED;
1237 __cpu_name[cpu] = "MIPS 4KSc";
1238 break;
1239 case PRID_IMP_5KC:
1240 c->cputype = CPU_5KC;
1241 c->writecombine = _CACHE_UNCACHED;
1242 __cpu_name[cpu] = "MIPS 5Kc";
1243 break;
1244 case PRID_IMP_5KE:
1245 c->cputype = CPU_5KE;
1246 c->writecombine = _CACHE_UNCACHED;
1247 __cpu_name[cpu] = "MIPS 5KE";
1248 break;
1249 case PRID_IMP_20KC:
1250 c->cputype = CPU_20KC;
1251 c->writecombine = _CACHE_UNCACHED;
1252 __cpu_name[cpu] = "MIPS 20Kc";
1253 break;
1254 case PRID_IMP_24K:
1255 c->cputype = CPU_24K;
1256 c->writecombine = _CACHE_UNCACHED;
1257 __cpu_name[cpu] = "MIPS 24Kc";
1258 break;
1259 case PRID_IMP_24KE:
1260 c->cputype = CPU_24K;
1261 c->writecombine = _CACHE_UNCACHED;
1262 __cpu_name[cpu] = "MIPS 24KEc";
1263 break;
1264 case PRID_IMP_25KF:
1265 c->cputype = CPU_25KF;
1266 c->writecombine = _CACHE_UNCACHED;
1267 __cpu_name[cpu] = "MIPS 25Kc";
1268 break;
1269 case PRID_IMP_34K:
1270 c->cputype = CPU_34K;
1271 c->writecombine = _CACHE_UNCACHED;
1272 __cpu_name[cpu] = "MIPS 34Kc";
1273 break;
1274 case PRID_IMP_74K:
1275 c->cputype = CPU_74K;
1276 c->writecombine = _CACHE_UNCACHED;
1277 __cpu_name[cpu] = "MIPS 74Kc";
1278 break;
1279 case PRID_IMP_M14KC:
1280 c->cputype = CPU_M14KC;
1281 c->writecombine = _CACHE_UNCACHED;
1282 __cpu_name[cpu] = "MIPS M14Kc";
1283 break;
1284 case PRID_IMP_M14KEC:
1285 c->cputype = CPU_M14KEC;
1286 c->writecombine = _CACHE_UNCACHED;
1287 __cpu_name[cpu] = "MIPS M14KEc";
1288 break;
1289 case PRID_IMP_1004K:
1290 c->cputype = CPU_1004K;
1291 c->writecombine = _CACHE_UNCACHED;
1292 __cpu_name[cpu] = "MIPS 1004Kc";
1293 break;
1294 case PRID_IMP_1074K:
1295 c->cputype = CPU_1074K;
1296 c->writecombine = _CACHE_UNCACHED;
1297 __cpu_name[cpu] = "MIPS 1074Kc";
1298 break;
1299 case PRID_IMP_INTERAPTIV_UP:
1300 c->cputype = CPU_INTERAPTIV;
1301 __cpu_name[cpu] = "MIPS interAptiv";
1302 break;
1303 case PRID_IMP_INTERAPTIV_MP:
1304 c->cputype = CPU_INTERAPTIV;
1305 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1306 break;
1307 case PRID_IMP_PROAPTIV_UP:
1308 c->cputype = CPU_PROAPTIV;
1309 __cpu_name[cpu] = "MIPS proAptiv";
1310 break;
1311 case PRID_IMP_PROAPTIV_MP:
1312 c->cputype = CPU_PROAPTIV;
1313 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1314 break;
1315 case PRID_IMP_P5600:
1316 c->cputype = CPU_P5600;
1317 __cpu_name[cpu] = "MIPS P5600";
1318 break;
1319 case PRID_IMP_I6400:
1320 c->cputype = CPU_I6400;
1321 __cpu_name[cpu] = "MIPS I6400";
1322 break;
1323 case PRID_IMP_M5150:
1324 c->cputype = CPU_M5150;
1325 __cpu_name[cpu] = "MIPS M5150";
1326 break;
1327 }
1328
1329 decode_configs(c);
1330
1331 spram_config();
1332 }
1333
cpu_probe_alchemy(struct cpuinfo_mips * c,unsigned int cpu)1334 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1335 {
1336 decode_configs(c);
1337 switch (c->processor_id & PRID_IMP_MASK) {
1338 case PRID_IMP_AU1_REV1:
1339 case PRID_IMP_AU1_REV2:
1340 c->cputype = CPU_ALCHEMY;
1341 switch ((c->processor_id >> 24) & 0xff) {
1342 case 0:
1343 __cpu_name[cpu] = "Au1000";
1344 break;
1345 case 1:
1346 __cpu_name[cpu] = "Au1500";
1347 break;
1348 case 2:
1349 __cpu_name[cpu] = "Au1100";
1350 break;
1351 case 3:
1352 __cpu_name[cpu] = "Au1550";
1353 break;
1354 case 4:
1355 __cpu_name[cpu] = "Au1200";
1356 if ((c->processor_id & PRID_REV_MASK) == 2)
1357 __cpu_name[cpu] = "Au1250";
1358 break;
1359 case 5:
1360 __cpu_name[cpu] = "Au1210";
1361 break;
1362 default:
1363 __cpu_name[cpu] = "Au1xxx";
1364 break;
1365 }
1366 break;
1367 }
1368 }
1369
cpu_probe_sibyte(struct cpuinfo_mips * c,unsigned int cpu)1370 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1371 {
1372 decode_configs(c);
1373
1374 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1375 switch (c->processor_id & PRID_IMP_MASK) {
1376 case PRID_IMP_SB1:
1377 c->cputype = CPU_SB1;
1378 __cpu_name[cpu] = "SiByte SB1";
1379 /* FPU in pass1 is known to have issues. */
1380 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1381 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1382 break;
1383 case PRID_IMP_SB1A:
1384 c->cputype = CPU_SB1A;
1385 __cpu_name[cpu] = "SiByte SB1A";
1386 break;
1387 }
1388 }
1389
cpu_probe_sandcraft(struct cpuinfo_mips * c,unsigned int cpu)1390 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1391 {
1392 decode_configs(c);
1393 switch (c->processor_id & PRID_IMP_MASK) {
1394 case PRID_IMP_SR71000:
1395 c->cputype = CPU_SR71000;
1396 __cpu_name[cpu] = "Sandcraft SR71000";
1397 c->scache.ways = 8;
1398 c->tlbsize = 64;
1399 break;
1400 }
1401 }
1402
cpu_probe_nxp(struct cpuinfo_mips * c,unsigned int cpu)1403 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1404 {
1405 decode_configs(c);
1406 switch (c->processor_id & PRID_IMP_MASK) {
1407 case PRID_IMP_PR4450:
1408 c->cputype = CPU_PR4450;
1409 __cpu_name[cpu] = "Philips PR4450";
1410 set_isa(c, MIPS_CPU_ISA_M32R1);
1411 break;
1412 }
1413 }
1414
cpu_probe_broadcom(struct cpuinfo_mips * c,unsigned int cpu)1415 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1416 {
1417 decode_configs(c);
1418 switch (c->processor_id & PRID_IMP_MASK) {
1419 case PRID_IMP_BMIPS32_REV4:
1420 case PRID_IMP_BMIPS32_REV8:
1421 c->cputype = CPU_BMIPS32;
1422 __cpu_name[cpu] = "Broadcom BMIPS32";
1423 set_elf_platform(cpu, "bmips32");
1424 break;
1425 case PRID_IMP_BMIPS3300:
1426 case PRID_IMP_BMIPS3300_ALT:
1427 case PRID_IMP_BMIPS3300_BUG:
1428 c->cputype = CPU_BMIPS3300;
1429 __cpu_name[cpu] = "Broadcom BMIPS3300";
1430 set_elf_platform(cpu, "bmips3300");
1431 break;
1432 case PRID_IMP_BMIPS43XX: {
1433 int rev = c->processor_id & PRID_REV_MASK;
1434
1435 if (rev >= PRID_REV_BMIPS4380_LO &&
1436 rev <= PRID_REV_BMIPS4380_HI) {
1437 c->cputype = CPU_BMIPS4380;
1438 __cpu_name[cpu] = "Broadcom BMIPS4380";
1439 set_elf_platform(cpu, "bmips4380");
1440 } else {
1441 c->cputype = CPU_BMIPS4350;
1442 __cpu_name[cpu] = "Broadcom BMIPS4350";
1443 set_elf_platform(cpu, "bmips4350");
1444 }
1445 break;
1446 }
1447 case PRID_IMP_BMIPS5000:
1448 case PRID_IMP_BMIPS5200:
1449 c->cputype = CPU_BMIPS5000;
1450 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1451 __cpu_name[cpu] = "Broadcom BMIPS5200";
1452 else
1453 __cpu_name[cpu] = "Broadcom BMIPS5000";
1454 set_elf_platform(cpu, "bmips5000");
1455 c->options |= MIPS_CPU_ULRI;
1456 break;
1457 }
1458 }
1459
cpu_probe_cavium(struct cpuinfo_mips * c,unsigned int cpu)1460 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1461 {
1462 decode_configs(c);
1463 switch (c->processor_id & PRID_IMP_MASK) {
1464 case PRID_IMP_CAVIUM_CN38XX:
1465 case PRID_IMP_CAVIUM_CN31XX:
1466 case PRID_IMP_CAVIUM_CN30XX:
1467 c->cputype = CPU_CAVIUM_OCTEON;
1468 __cpu_name[cpu] = "Cavium Octeon";
1469 goto platform;
1470 case PRID_IMP_CAVIUM_CN58XX:
1471 case PRID_IMP_CAVIUM_CN56XX:
1472 case PRID_IMP_CAVIUM_CN50XX:
1473 case PRID_IMP_CAVIUM_CN52XX:
1474 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1475 __cpu_name[cpu] = "Cavium Octeon+";
1476 platform:
1477 set_elf_platform(cpu, "octeon");
1478 break;
1479 case PRID_IMP_CAVIUM_CN61XX:
1480 case PRID_IMP_CAVIUM_CN63XX:
1481 case PRID_IMP_CAVIUM_CN66XX:
1482 case PRID_IMP_CAVIUM_CN68XX:
1483 case PRID_IMP_CAVIUM_CNF71XX:
1484 c->cputype = CPU_CAVIUM_OCTEON2;
1485 __cpu_name[cpu] = "Cavium Octeon II";
1486 set_elf_platform(cpu, "octeon2");
1487 break;
1488 case PRID_IMP_CAVIUM_CN70XX:
1489 case PRID_IMP_CAVIUM_CN78XX:
1490 c->cputype = CPU_CAVIUM_OCTEON3;
1491 __cpu_name[cpu] = "Cavium Octeon III";
1492 set_elf_platform(cpu, "octeon3");
1493 break;
1494 default:
1495 printk(KERN_INFO "Unknown Octeon chip!\n");
1496 c->cputype = CPU_UNKNOWN;
1497 break;
1498 }
1499 }
1500
cpu_probe_ingenic(struct cpuinfo_mips * c,unsigned int cpu)1501 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1502 {
1503 decode_configs(c);
1504 /* JZRISC does not implement the CP0 counter. */
1505 c->options &= ~MIPS_CPU_COUNTER;
1506 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1507 switch (c->processor_id & PRID_IMP_MASK) {
1508 case PRID_IMP_JZRISC:
1509 c->cputype = CPU_JZRISC;
1510 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1511 __cpu_name[cpu] = "Ingenic JZRISC";
1512 break;
1513 default:
1514 panic("Unknown Ingenic Processor ID!");
1515 break;
1516 }
1517 }
1518
cpu_probe_netlogic(struct cpuinfo_mips * c,int cpu)1519 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1520 {
1521 decode_configs(c);
1522
1523 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1524 c->cputype = CPU_ALCHEMY;
1525 __cpu_name[cpu] = "Au1300";
1526 /* following stuff is not for Alchemy */
1527 return;
1528 }
1529
1530 c->options = (MIPS_CPU_TLB |
1531 MIPS_CPU_4KEX |
1532 MIPS_CPU_COUNTER |
1533 MIPS_CPU_DIVEC |
1534 MIPS_CPU_WATCH |
1535 MIPS_CPU_EJTAG |
1536 MIPS_CPU_LLSC);
1537
1538 switch (c->processor_id & PRID_IMP_MASK) {
1539 case PRID_IMP_NETLOGIC_XLP2XX:
1540 case PRID_IMP_NETLOGIC_XLP9XX:
1541 case PRID_IMP_NETLOGIC_XLP5XX:
1542 c->cputype = CPU_XLP;
1543 __cpu_name[cpu] = "Broadcom XLPII";
1544 break;
1545
1546 case PRID_IMP_NETLOGIC_XLP8XX:
1547 case PRID_IMP_NETLOGIC_XLP3XX:
1548 c->cputype = CPU_XLP;
1549 __cpu_name[cpu] = "Netlogic XLP";
1550 break;
1551
1552 case PRID_IMP_NETLOGIC_XLR732:
1553 case PRID_IMP_NETLOGIC_XLR716:
1554 case PRID_IMP_NETLOGIC_XLR532:
1555 case PRID_IMP_NETLOGIC_XLR308:
1556 case PRID_IMP_NETLOGIC_XLR532C:
1557 case PRID_IMP_NETLOGIC_XLR516C:
1558 case PRID_IMP_NETLOGIC_XLR508C:
1559 case PRID_IMP_NETLOGIC_XLR308C:
1560 c->cputype = CPU_XLR;
1561 __cpu_name[cpu] = "Netlogic XLR";
1562 break;
1563
1564 case PRID_IMP_NETLOGIC_XLS608:
1565 case PRID_IMP_NETLOGIC_XLS408:
1566 case PRID_IMP_NETLOGIC_XLS404:
1567 case PRID_IMP_NETLOGIC_XLS208:
1568 case PRID_IMP_NETLOGIC_XLS204:
1569 case PRID_IMP_NETLOGIC_XLS108:
1570 case PRID_IMP_NETLOGIC_XLS104:
1571 case PRID_IMP_NETLOGIC_XLS616B:
1572 case PRID_IMP_NETLOGIC_XLS608B:
1573 case PRID_IMP_NETLOGIC_XLS416B:
1574 case PRID_IMP_NETLOGIC_XLS412B:
1575 case PRID_IMP_NETLOGIC_XLS408B:
1576 case PRID_IMP_NETLOGIC_XLS404B:
1577 c->cputype = CPU_XLR;
1578 __cpu_name[cpu] = "Netlogic XLS";
1579 break;
1580
1581 default:
1582 pr_info("Unknown Netlogic chip id [%02x]!\n",
1583 c->processor_id);
1584 c->cputype = CPU_XLR;
1585 break;
1586 }
1587
1588 if (c->cputype == CPU_XLP) {
1589 set_isa(c, MIPS_CPU_ISA_M64R2);
1590 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1591 /* This will be updated again after all threads are woken up */
1592 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1593 } else {
1594 set_isa(c, MIPS_CPU_ISA_M64R1);
1595 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1596 }
1597 c->kscratch_mask = 0xf;
1598 }
1599
1600 #ifdef CONFIG_64BIT
1601 /* For use by uaccess.h */
1602 u64 __ua_limit;
1603 EXPORT_SYMBOL(__ua_limit);
1604 #endif
1605
1606 const char *__cpu_name[NR_CPUS];
1607 const char *__elf_platform;
1608
cpu_probe(void)1609 void cpu_probe(void)
1610 {
1611 struct cpuinfo_mips *c = ¤t_cpu_data;
1612 unsigned int cpu = smp_processor_id();
1613
1614 c->processor_id = PRID_IMP_UNKNOWN;
1615 c->fpu_id = FPIR_IMP_NONE;
1616 c->cputype = CPU_UNKNOWN;
1617 c->writecombine = _CACHE_UNCACHED;
1618
1619 c->fpu_csr31 = FPU_CSR_RN;
1620 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1621
1622 c->processor_id = read_c0_prid();
1623 switch (c->processor_id & PRID_COMP_MASK) {
1624 case PRID_COMP_LEGACY:
1625 cpu_probe_legacy(c, cpu);
1626 break;
1627 case PRID_COMP_MIPS:
1628 cpu_probe_mips(c, cpu);
1629 break;
1630 case PRID_COMP_ALCHEMY:
1631 cpu_probe_alchemy(c, cpu);
1632 break;
1633 case PRID_COMP_SIBYTE:
1634 cpu_probe_sibyte(c, cpu);
1635 break;
1636 case PRID_COMP_BROADCOM:
1637 cpu_probe_broadcom(c, cpu);
1638 break;
1639 case PRID_COMP_SANDCRAFT:
1640 cpu_probe_sandcraft(c, cpu);
1641 break;
1642 case PRID_COMP_NXP:
1643 cpu_probe_nxp(c, cpu);
1644 break;
1645 case PRID_COMP_CAVIUM:
1646 cpu_probe_cavium(c, cpu);
1647 break;
1648 case PRID_COMP_INGENIC_D0:
1649 case PRID_COMP_INGENIC_D1:
1650 case PRID_COMP_INGENIC_E1:
1651 cpu_probe_ingenic(c, cpu);
1652 break;
1653 case PRID_COMP_NETLOGIC:
1654 cpu_probe_netlogic(c, cpu);
1655 break;
1656 }
1657
1658 BUG_ON(!__cpu_name[cpu]);
1659 BUG_ON(c->cputype == CPU_UNKNOWN);
1660
1661 /*
1662 * Platform code can force the cpu type to optimize code
1663 * generation. In that case be sure the cpu type is correctly
1664 * manually setup otherwise it could trigger some nasty bugs.
1665 */
1666 BUG_ON(current_cpu_type() != c->cputype);
1667
1668 if (mips_fpu_disabled)
1669 c->options &= ~MIPS_CPU_FPU;
1670
1671 if (mips_dsp_disabled)
1672 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1673
1674 if (mips_htw_disabled) {
1675 c->options &= ~MIPS_CPU_HTW;
1676 write_c0_pwctl(read_c0_pwctl() &
1677 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1678 }
1679
1680 if (c->options & MIPS_CPU_FPU)
1681 cpu_set_fpu_opts(c);
1682 else
1683 cpu_set_nofpu_opts(c);
1684
1685 if (cpu_has_bp_ghist)
1686 write_c0_r10k_diag(read_c0_r10k_diag() |
1687 R10K_DIAG_E_GHIST);
1688
1689 if (cpu_has_mips_r2_r6) {
1690 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1691 /* R2 has Performance Counter Interrupt indicator */
1692 c->options |= MIPS_CPU_PCI;
1693 }
1694 else
1695 c->srsets = 1;
1696
1697 if (cpu_has_mips_r6)
1698 elf_hwcap |= HWCAP_MIPS_R6;
1699
1700 if (cpu_has_msa) {
1701 c->msa_id = cpu_get_msa_id();
1702 WARN(c->msa_id & MSA_IR_WRPF,
1703 "Vector register partitioning unimplemented!");
1704 elf_hwcap |= HWCAP_MIPS_MSA;
1705 }
1706
1707 cpu_probe_vmbits(c);
1708
1709 #ifdef CONFIG_64BIT
1710 if (cpu == 0)
1711 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1712 #endif
1713 }
1714
cpu_report(void)1715 void cpu_report(void)
1716 {
1717 struct cpuinfo_mips *c = ¤t_cpu_data;
1718
1719 pr_info("CPU%d revision is: %08x (%s)\n",
1720 smp_processor_id(), c->processor_id, cpu_name_string());
1721 if (c->options & MIPS_CPU_FPU)
1722 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1723 if (cpu_has_msa)
1724 pr_info("MSA revision is: %08x\n", c->msa_id);
1725 }
1726