1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8 #include <linux/delay.h>
9 #include <linux/pci.h>
10 #include <linux/ratelimit.h>
11 #include <linux/vmalloc.h>
12 #include <scsi/scsi_tcq.h>
13 #include <asm/unaligned.h>
14
15 #define MASK(n) ((1ULL<<(n))-1)
16 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
17 ((addr >> 25) & 0x3ff))
18 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
19 ((addr >> 25) & 0x3ff))
20 #define MS_WIN(addr) (addr & 0x0ffc0000)
21 #define QLA82XX_PCI_MN_2M (0)
22 #define QLA82XX_PCI_MS_2M (0x80000)
23 #define QLA82XX_PCI_OCM0_2M (0xc0000)
24 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
25 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
26 #define BLOCK_PROTECT_BITS 0x0F
27
28 /* CRB window related */
29 #define CRB_BLK(off) ((off >> 20) & 0x3f)
30 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
31 #define CRB_WINDOW_2M (0x130060)
32 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
33 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
34 ((off) & 0xf0000))
35 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
36 #define CRB_INDIRECT_2M (0x1e0000UL)
37
38 #define MAX_CRB_XFORM 60
39 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
40 static int qla82xx_crb_table_initialized;
41
42 #define qla82xx_crb_addr_transform(name) \
43 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
44 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
45
qla82xx_crb_addr_transform_setup(void)46 static void qla82xx_crb_addr_transform_setup(void)
47 {
48 qla82xx_crb_addr_transform(XDMA);
49 qla82xx_crb_addr_transform(TIMR);
50 qla82xx_crb_addr_transform(SRE);
51 qla82xx_crb_addr_transform(SQN3);
52 qla82xx_crb_addr_transform(SQN2);
53 qla82xx_crb_addr_transform(SQN1);
54 qla82xx_crb_addr_transform(SQN0);
55 qla82xx_crb_addr_transform(SQS3);
56 qla82xx_crb_addr_transform(SQS2);
57 qla82xx_crb_addr_transform(SQS1);
58 qla82xx_crb_addr_transform(SQS0);
59 qla82xx_crb_addr_transform(RPMX7);
60 qla82xx_crb_addr_transform(RPMX6);
61 qla82xx_crb_addr_transform(RPMX5);
62 qla82xx_crb_addr_transform(RPMX4);
63 qla82xx_crb_addr_transform(RPMX3);
64 qla82xx_crb_addr_transform(RPMX2);
65 qla82xx_crb_addr_transform(RPMX1);
66 qla82xx_crb_addr_transform(RPMX0);
67 qla82xx_crb_addr_transform(ROMUSB);
68 qla82xx_crb_addr_transform(SN);
69 qla82xx_crb_addr_transform(QMN);
70 qla82xx_crb_addr_transform(QMS);
71 qla82xx_crb_addr_transform(PGNI);
72 qla82xx_crb_addr_transform(PGND);
73 qla82xx_crb_addr_transform(PGN3);
74 qla82xx_crb_addr_transform(PGN2);
75 qla82xx_crb_addr_transform(PGN1);
76 qla82xx_crb_addr_transform(PGN0);
77 qla82xx_crb_addr_transform(PGSI);
78 qla82xx_crb_addr_transform(PGSD);
79 qla82xx_crb_addr_transform(PGS3);
80 qla82xx_crb_addr_transform(PGS2);
81 qla82xx_crb_addr_transform(PGS1);
82 qla82xx_crb_addr_transform(PGS0);
83 qla82xx_crb_addr_transform(PS);
84 qla82xx_crb_addr_transform(PH);
85 qla82xx_crb_addr_transform(NIU);
86 qla82xx_crb_addr_transform(I2Q);
87 qla82xx_crb_addr_transform(EG);
88 qla82xx_crb_addr_transform(MN);
89 qla82xx_crb_addr_transform(MS);
90 qla82xx_crb_addr_transform(CAS2);
91 qla82xx_crb_addr_transform(CAS1);
92 qla82xx_crb_addr_transform(CAS0);
93 qla82xx_crb_addr_transform(CAM);
94 qla82xx_crb_addr_transform(C2C1);
95 qla82xx_crb_addr_transform(C2C0);
96 qla82xx_crb_addr_transform(SMB);
97 qla82xx_crb_addr_transform(OCM0);
98 /*
99 * Used only in P3 just define it for P2 also.
100 */
101 qla82xx_crb_addr_transform(I2C0);
102
103 qla82xx_crb_table_initialized = 1;
104 }
105
106 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
107 {{{0, 0, 0, 0} } },
108 {{{1, 0x0100000, 0x0102000, 0x120000},
109 {1, 0x0110000, 0x0120000, 0x130000},
110 {1, 0x0120000, 0x0122000, 0x124000},
111 {1, 0x0130000, 0x0132000, 0x126000},
112 {1, 0x0140000, 0x0142000, 0x128000},
113 {1, 0x0150000, 0x0152000, 0x12a000},
114 {1, 0x0160000, 0x0170000, 0x110000},
115 {1, 0x0170000, 0x0172000, 0x12e000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {1, 0x01e0000, 0x01e0800, 0x122000},
123 {0, 0x0000000, 0x0000000, 0x000000} } } ,
124 {{{1, 0x0200000, 0x0210000, 0x180000} } },
125 {{{0, 0, 0, 0} } },
126 {{{1, 0x0400000, 0x0401000, 0x169000} } },
127 {{{1, 0x0500000, 0x0510000, 0x140000} } },
128 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
129 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
130 {{{1, 0x0800000, 0x0802000, 0x170000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {1, 0x08f0000, 0x08f2000, 0x172000} } },
146 {{{1, 0x0900000, 0x0902000, 0x174000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {1, 0x09f0000, 0x09f2000, 0x176000} } },
162 {{{0, 0x0a00000, 0x0a02000, 0x178000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
178 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
194 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
195 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
196 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
197 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
198 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
199 {{{1, 0x1100000, 0x1101000, 0x160000} } },
200 {{{1, 0x1200000, 0x1201000, 0x161000} } },
201 {{{1, 0x1300000, 0x1301000, 0x162000} } },
202 {{{1, 0x1400000, 0x1401000, 0x163000} } },
203 {{{1, 0x1500000, 0x1501000, 0x165000} } },
204 {{{1, 0x1600000, 0x1601000, 0x166000} } },
205 {{{0, 0, 0, 0} } },
206 {{{0, 0, 0, 0} } },
207 {{{0, 0, 0, 0} } },
208 {{{0, 0, 0, 0} } },
209 {{{0, 0, 0, 0} } },
210 {{{0, 0, 0, 0} } },
211 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
212 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
213 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
214 {{{0} } },
215 {{{1, 0x2100000, 0x2102000, 0x120000},
216 {1, 0x2110000, 0x2120000, 0x130000},
217 {1, 0x2120000, 0x2122000, 0x124000},
218 {1, 0x2130000, 0x2132000, 0x126000},
219 {1, 0x2140000, 0x2142000, 0x128000},
220 {1, 0x2150000, 0x2152000, 0x12a000},
221 {1, 0x2160000, 0x2170000, 0x110000},
222 {1, 0x2170000, 0x2172000, 0x12e000},
223 {0, 0x0000000, 0x0000000, 0x000000},
224 {0, 0x0000000, 0x0000000, 0x000000},
225 {0, 0x0000000, 0x0000000, 0x000000},
226 {0, 0x0000000, 0x0000000, 0x000000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000},
230 {0, 0x0000000, 0x0000000, 0x000000} } },
231 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
232 {{{0} } },
233 {{{0} } },
234 {{{0} } },
235 {{{0} } },
236 {{{0} } },
237 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
238 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
239 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
240 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
241 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
242 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
243 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
244 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
245 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
246 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
247 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
248 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
249 {{{0} } },
250 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
251 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
252 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
253 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
254 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
255 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
256 {{{0} } },
257 {{{0} } },
258 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
259 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
260 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
261 };
262
263 /*
264 * top 12 bits of crb internal address (hub, agent)
265 */
266 static unsigned qla82xx_crb_hub_agt[64] = {
267 0,
268 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
269 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
270 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
271 0,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
294 0,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
296 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
297 0,
298 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
299 0,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
301 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
302 0,
303 0,
304 0,
305 0,
306 0,
307 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
308 0,
309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
318 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
319 0,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
323 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
324 0,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
327 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
328 0,
329 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
330 0,
331 };
332
333 /* Device states */
334 static char *q_dev_state[] = {
335 "Unknown",
336 "Cold",
337 "Initializing",
338 "Ready",
339 "Need Reset",
340 "Need Quiescent",
341 "Failed",
342 "Quiescent",
343 };
344
qdev_state(uint32_t dev_state)345 char *qdev_state(uint32_t dev_state)
346 {
347 return q_dev_state[dev_state];
348 }
349
350 /*
351 * In: 'off_in' is offset from CRB space in 128M pci map
352 * Out: 'off_out' is 2M pci map addr
353 * side effect: lock crb window
354 */
355 static void
qla82xx_pci_set_crbwindow_2M(struct qla_hw_data * ha,ulong off_in,void __iomem ** off_out)356 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in,
357 void __iomem **off_out)
358 {
359 u32 win_read;
360 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
361
362 ha->crb_win = CRB_HI(off_in);
363 writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase);
364
365 /* Read back value to make sure write has gone through before trying
366 * to use it.
367 */
368 win_read = RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
369 if (win_read != ha->crb_win) {
370 ql_dbg(ql_dbg_p3p, vha, 0xb000,
371 "%s: Written crbwin (0x%x) "
372 "!= Read crbwin (0x%x), off=0x%lx.\n",
373 __func__, ha->crb_win, win_read, off_in);
374 }
375 *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
376 }
377
378 static inline unsigned long
qla82xx_pci_set_crbwindow(struct qla_hw_data * ha,u64 off)379 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
380 {
381 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
382 /* See if we are currently pointing to the region we want to use next */
383 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) {
384 /* No need to change window. PCIX and PCIEregs are in both
385 * regs are in both windows.
386 */
387 return off;
388 }
389
390 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) {
391 /* We are in first CRB window */
392 if (ha->curr_window != 0)
393 WARN_ON(1);
394 return off;
395 }
396
397 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) {
398 /* We are in second CRB window */
399 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST;
400
401 if (ha->curr_window != 1)
402 return off;
403
404 /* We are in the QM or direct access
405 * register region - do nothing
406 */
407 if ((off >= QLA82XX_PCI_DIRECT_CRB) &&
408 (off < QLA82XX_PCI_CAMQM_MAX))
409 return off;
410 }
411 /* strange address given */
412 ql_dbg(ql_dbg_p3p, vha, 0xb001,
413 "%s: Warning: unm_nic_pci_set_crbwindow "
414 "called with an unknown address(%llx).\n",
415 QLA2XXX_DRIVER_NAME, off);
416 return off;
417 }
418
419 static int
qla82xx_pci_get_crb_addr_2M(struct qla_hw_data * ha,ulong off_in,void __iomem ** off_out)420 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in,
421 void __iomem **off_out)
422 {
423 struct crb_128M_2M_sub_block_map *m;
424
425 if (off_in >= QLA82XX_CRB_MAX)
426 return -1;
427
428 if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) {
429 *off_out = (off_in - QLA82XX_PCI_CAMQM) +
430 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
431 return 0;
432 }
433
434 if (off_in < QLA82XX_PCI_CRBSPACE)
435 return -1;
436
437 off_in -= QLA82XX_PCI_CRBSPACE;
438
439 /* Try direct map */
440 m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)];
441
442 if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) {
443 *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase;
444 return 0;
445 }
446 /* Not in direct map, use crb window */
447 *off_out = (void __iomem *)off_in;
448 return 1;
449 }
450
451 #define CRB_WIN_LOCK_TIMEOUT 100000000
qla82xx_crb_win_lock(struct qla_hw_data * ha)452 static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
453 {
454 int done = 0, timeout = 0;
455
456 while (!done) {
457 /* acquire semaphore3 from PCI HW block */
458 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
459 if (done == 1)
460 break;
461 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
462 return -1;
463 timeout++;
464 }
465 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
466 return 0;
467 }
468
469 int
qla82xx_wr_32(struct qla_hw_data * ha,ulong off_in,u32 data)470 qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data)
471 {
472 void __iomem *off;
473 unsigned long flags = 0;
474 int rv;
475
476 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
477
478 BUG_ON(rv == -1);
479
480 if (rv == 1) {
481 #ifndef __CHECKER__
482 write_lock_irqsave(&ha->hw_lock, flags);
483 #endif
484 qla82xx_crb_win_lock(ha);
485 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
486 }
487
488 writel(data, (void __iomem *)off);
489
490 if (rv == 1) {
491 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
492 #ifndef __CHECKER__
493 write_unlock_irqrestore(&ha->hw_lock, flags);
494 #endif
495 }
496 return 0;
497 }
498
499 int
qla82xx_rd_32(struct qla_hw_data * ha,ulong off_in)500 qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in)
501 {
502 void __iomem *off;
503 unsigned long flags = 0;
504 int rv;
505 u32 data;
506
507 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
508
509 BUG_ON(rv == -1);
510
511 if (rv == 1) {
512 #ifndef __CHECKER__
513 write_lock_irqsave(&ha->hw_lock, flags);
514 #endif
515 qla82xx_crb_win_lock(ha);
516 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
517 }
518 data = RD_REG_DWORD(off);
519
520 if (rv == 1) {
521 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
522 #ifndef __CHECKER__
523 write_unlock_irqrestore(&ha->hw_lock, flags);
524 #endif
525 }
526 return data;
527 }
528
529 #define IDC_LOCK_TIMEOUT 100000000
qla82xx_idc_lock(struct qla_hw_data * ha)530 int qla82xx_idc_lock(struct qla_hw_data *ha)
531 {
532 int i;
533 int done = 0, timeout = 0;
534
535 while (!done) {
536 /* acquire semaphore5 from PCI HW block */
537 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
538 if (done == 1)
539 break;
540 if (timeout >= IDC_LOCK_TIMEOUT)
541 return -1;
542
543 timeout++;
544
545 /* Yield CPU */
546 if (!in_interrupt())
547 schedule();
548 else {
549 for (i = 0; i < 20; i++)
550 cpu_relax();
551 }
552 }
553
554 return 0;
555 }
556
qla82xx_idc_unlock(struct qla_hw_data * ha)557 void qla82xx_idc_unlock(struct qla_hw_data *ha)
558 {
559 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
560 }
561
562 /*
563 * check memory access boundary.
564 * used by test agent. support ddr access only for now
565 */
566 static unsigned long
qla82xx_pci_mem_bound_check(struct qla_hw_data * ha,unsigned long long addr,int size)567 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
568 unsigned long long addr, int size)
569 {
570 if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
571 QLA82XX_ADDR_DDR_NET_MAX) ||
572 !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET,
573 QLA82XX_ADDR_DDR_NET_MAX) ||
574 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
575 return 0;
576 else
577 return 1;
578 }
579
580 static int qla82xx_pci_set_window_warning_count;
581
582 static unsigned long
qla82xx_pci_set_window(struct qla_hw_data * ha,unsigned long long addr)583 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
584 {
585 int window;
586 u32 win_read;
587 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
588
589 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
590 QLA82XX_ADDR_DDR_NET_MAX)) {
591 /* DDR network side */
592 window = MN_WIN(addr);
593 ha->ddr_mn_window = window;
594 qla82xx_wr_32(ha,
595 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
596 win_read = qla82xx_rd_32(ha,
597 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
598 if ((win_read << 17) != window) {
599 ql_dbg(ql_dbg_p3p, vha, 0xb003,
600 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
601 __func__, window, win_read);
602 }
603 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
604 } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
605 QLA82XX_ADDR_OCM0_MAX)) {
606 unsigned int temp1;
607 if ((addr & 0x00ff800) == 0xff800) {
608 ql_log(ql_log_warn, vha, 0xb004,
609 "%s: QM access not handled.\n", __func__);
610 addr = -1UL;
611 }
612 window = OCM_WIN(addr);
613 ha->ddr_mn_window = window;
614 qla82xx_wr_32(ha,
615 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
616 win_read = qla82xx_rd_32(ha,
617 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
618 temp1 = ((window & 0x1FF) << 7) |
619 ((window & 0x0FFFE0000) >> 17);
620 if (win_read != temp1) {
621 ql_log(ql_log_warn, vha, 0xb005,
622 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
623 __func__, temp1, win_read);
624 }
625 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
626
627 } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET,
628 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
629 /* QDR network side */
630 window = MS_WIN(addr);
631 ha->qdr_sn_window = window;
632 qla82xx_wr_32(ha,
633 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
634 win_read = qla82xx_rd_32(ha,
635 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
636 if (win_read != window) {
637 ql_log(ql_log_warn, vha, 0xb006,
638 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
639 __func__, window, win_read);
640 }
641 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
642 } else {
643 /*
644 * peg gdb frequently accesses memory that doesn't exist,
645 * this limits the chit chat so debugging isn't slowed down.
646 */
647 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
648 (qla82xx_pci_set_window_warning_count%64 == 0)) {
649 ql_log(ql_log_warn, vha, 0xb007,
650 "%s: Warning:%s Unknown address range!.\n",
651 __func__, QLA2XXX_DRIVER_NAME);
652 }
653 addr = -1UL;
654 }
655 return addr;
656 }
657
658 /* check if address is in the same windows as the previous access */
qla82xx_pci_is_same_window(struct qla_hw_data * ha,unsigned long long addr)659 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
660 unsigned long long addr)
661 {
662 int window;
663 unsigned long long qdr_max;
664
665 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
666
667 /* DDR network side */
668 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
669 QLA82XX_ADDR_DDR_NET_MAX))
670 BUG();
671 else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
672 QLA82XX_ADDR_OCM0_MAX))
673 return 1;
674 else if (addr_in_range(addr, QLA82XX_ADDR_OCM1,
675 QLA82XX_ADDR_OCM1_MAX))
676 return 1;
677 else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
678 /* QDR network side */
679 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
680 if (ha->qdr_sn_window == window)
681 return 1;
682 }
683 return 0;
684 }
685
qla82xx_pci_mem_read_direct(struct qla_hw_data * ha,u64 off,void * data,int size)686 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
687 u64 off, void *data, int size)
688 {
689 unsigned long flags;
690 void __iomem *addr = NULL;
691 int ret = 0;
692 u64 start;
693 uint8_t __iomem *mem_ptr = NULL;
694 unsigned long mem_base;
695 unsigned long mem_page;
696 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
697
698 write_lock_irqsave(&ha->hw_lock, flags);
699
700 /*
701 * If attempting to access unknown address or straddle hw windows,
702 * do not access.
703 */
704 start = qla82xx_pci_set_window(ha, off);
705 if ((start == -1UL) ||
706 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
707 write_unlock_irqrestore(&ha->hw_lock, flags);
708 ql_log(ql_log_fatal, vha, 0xb008,
709 "%s out of bound pci memory "
710 "access, offset is 0x%llx.\n",
711 QLA2XXX_DRIVER_NAME, off);
712 return -1;
713 }
714
715 write_unlock_irqrestore(&ha->hw_lock, flags);
716 mem_base = pci_resource_start(ha->pdev, 0);
717 mem_page = start & PAGE_MASK;
718 /* Map two pages whenever user tries to access addresses in two
719 * consecutive pages.
720 */
721 if (mem_page != ((start + size - 1) & PAGE_MASK))
722 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
723 else
724 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
725 if (mem_ptr == NULL) {
726 *(u8 *)data = 0;
727 return -1;
728 }
729 addr = mem_ptr;
730 addr += start & (PAGE_SIZE - 1);
731 write_lock_irqsave(&ha->hw_lock, flags);
732
733 switch (size) {
734 case 1:
735 *(u8 *)data = readb(addr);
736 break;
737 case 2:
738 *(u16 *)data = readw(addr);
739 break;
740 case 4:
741 *(u32 *)data = readl(addr);
742 break;
743 case 8:
744 *(u64 *)data = readq(addr);
745 break;
746 default:
747 ret = -1;
748 break;
749 }
750 write_unlock_irqrestore(&ha->hw_lock, flags);
751
752 if (mem_ptr)
753 iounmap(mem_ptr);
754 return ret;
755 }
756
757 static int
qla82xx_pci_mem_write_direct(struct qla_hw_data * ha,u64 off,void * data,int size)758 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
759 u64 off, void *data, int size)
760 {
761 unsigned long flags;
762 void __iomem *addr = NULL;
763 int ret = 0;
764 u64 start;
765 uint8_t __iomem *mem_ptr = NULL;
766 unsigned long mem_base;
767 unsigned long mem_page;
768 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
769
770 write_lock_irqsave(&ha->hw_lock, flags);
771
772 /*
773 * If attempting to access unknown address or straddle hw windows,
774 * do not access.
775 */
776 start = qla82xx_pci_set_window(ha, off);
777 if ((start == -1UL) ||
778 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
779 write_unlock_irqrestore(&ha->hw_lock, flags);
780 ql_log(ql_log_fatal, vha, 0xb009,
781 "%s out of bount memory "
782 "access, offset is 0x%llx.\n",
783 QLA2XXX_DRIVER_NAME, off);
784 return -1;
785 }
786
787 write_unlock_irqrestore(&ha->hw_lock, flags);
788 mem_base = pci_resource_start(ha->pdev, 0);
789 mem_page = start & PAGE_MASK;
790 /* Map two pages whenever user tries to access addresses in two
791 * consecutive pages.
792 */
793 if (mem_page != ((start + size - 1) & PAGE_MASK))
794 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
795 else
796 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
797 if (mem_ptr == NULL)
798 return -1;
799
800 addr = mem_ptr;
801 addr += start & (PAGE_SIZE - 1);
802 write_lock_irqsave(&ha->hw_lock, flags);
803
804 switch (size) {
805 case 1:
806 writeb(*(u8 *)data, addr);
807 break;
808 case 2:
809 writew(*(u16 *)data, addr);
810 break;
811 case 4:
812 writel(*(u32 *)data, addr);
813 break;
814 case 8:
815 writeq(*(u64 *)data, addr);
816 break;
817 default:
818 ret = -1;
819 break;
820 }
821 write_unlock_irqrestore(&ha->hw_lock, flags);
822 if (mem_ptr)
823 iounmap(mem_ptr);
824 return ret;
825 }
826
827 #define MTU_FUDGE_FACTOR 100
828 static unsigned long
qla82xx_decode_crb_addr(unsigned long addr)829 qla82xx_decode_crb_addr(unsigned long addr)
830 {
831 int i;
832 unsigned long base_addr, offset, pci_base;
833
834 if (!qla82xx_crb_table_initialized)
835 qla82xx_crb_addr_transform_setup();
836
837 pci_base = ADDR_ERROR;
838 base_addr = addr & 0xfff00000;
839 offset = addr & 0x000fffff;
840
841 for (i = 0; i < MAX_CRB_XFORM; i++) {
842 if (crb_addr_xform[i] == base_addr) {
843 pci_base = i << 20;
844 break;
845 }
846 }
847 if (pci_base == ADDR_ERROR)
848 return pci_base;
849 return pci_base + offset;
850 }
851
852 static long rom_max_timeout = 100;
853 static long qla82xx_rom_lock_timeout = 100;
854
855 static int
qla82xx_rom_lock(struct qla_hw_data * ha)856 qla82xx_rom_lock(struct qla_hw_data *ha)
857 {
858 int done = 0, timeout = 0;
859 uint32_t lock_owner = 0;
860 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
861
862 while (!done) {
863 /* acquire semaphore2 from PCI HW block */
864 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
865 if (done == 1)
866 break;
867 if (timeout >= qla82xx_rom_lock_timeout) {
868 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
869 ql_dbg(ql_dbg_p3p, vha, 0xb157,
870 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
871 __func__, ha->portnum, lock_owner);
872 return -1;
873 }
874 timeout++;
875 }
876 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum);
877 return 0;
878 }
879
880 static void
qla82xx_rom_unlock(struct qla_hw_data * ha)881 qla82xx_rom_unlock(struct qla_hw_data *ha)
882 {
883 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff);
884 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
885 }
886
887 static int
qla82xx_wait_rom_busy(struct qla_hw_data * ha)888 qla82xx_wait_rom_busy(struct qla_hw_data *ha)
889 {
890 long timeout = 0;
891 long done = 0 ;
892 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
893
894 while (done == 0) {
895 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
896 done &= 4;
897 timeout++;
898 if (timeout >= rom_max_timeout) {
899 ql_dbg(ql_dbg_p3p, vha, 0xb00a,
900 "%s: Timeout reached waiting for rom busy.\n",
901 QLA2XXX_DRIVER_NAME);
902 return -1;
903 }
904 }
905 return 0;
906 }
907
908 static int
qla82xx_wait_rom_done(struct qla_hw_data * ha)909 qla82xx_wait_rom_done(struct qla_hw_data *ha)
910 {
911 long timeout = 0;
912 long done = 0 ;
913 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
914
915 while (done == 0) {
916 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
917 done &= 2;
918 timeout++;
919 if (timeout >= rom_max_timeout) {
920 ql_dbg(ql_dbg_p3p, vha, 0xb00b,
921 "%s: Timeout reached waiting for rom done.\n",
922 QLA2XXX_DRIVER_NAME);
923 return -1;
924 }
925 }
926 return 0;
927 }
928
929 static int
qla82xx_md_rw_32(struct qla_hw_data * ha,uint32_t off,u32 data,uint8_t flag)930 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
931 {
932 uint32_t off_value, rval = 0;
933
934 WRT_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000);
935
936 /* Read back value to make sure write has gone through */
937 RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
938 off_value = (off & 0x0000FFFF);
939
940 if (flag)
941 WRT_REG_DWORD(off_value + CRB_INDIRECT_2M + ha->nx_pcibase,
942 data);
943 else
944 rval = RD_REG_DWORD(off_value + CRB_INDIRECT_2M +
945 ha->nx_pcibase);
946
947 return rval;
948 }
949
950 static int
qla82xx_do_rom_fast_read(struct qla_hw_data * ha,int addr,int * valp)951 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
952 {
953 /* Dword reads to flash. */
954 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
955 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
956 (addr & 0x0000FFFF), 0, 0);
957
958 return 0;
959 }
960
961 static int
qla82xx_rom_fast_read(struct qla_hw_data * ha,int addr,int * valp)962 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
963 {
964 int ret, loops = 0;
965 uint32_t lock_owner = 0;
966 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
967
968 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
969 udelay(100);
970 schedule();
971 loops++;
972 }
973 if (loops >= 50000) {
974 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
975 ql_log(ql_log_fatal, vha, 0x00b9,
976 "Failed to acquire SEM2 lock, Lock Owner %u.\n",
977 lock_owner);
978 return -1;
979 }
980 ret = qla82xx_do_rom_fast_read(ha, addr, valp);
981 qla82xx_rom_unlock(ha);
982 return ret;
983 }
984
985 static int
qla82xx_read_status_reg(struct qla_hw_data * ha,uint32_t * val)986 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
987 {
988 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
989 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
990 qla82xx_wait_rom_busy(ha);
991 if (qla82xx_wait_rom_done(ha)) {
992 ql_log(ql_log_warn, vha, 0xb00c,
993 "Error waiting for rom done.\n");
994 return -1;
995 }
996 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
997 return 0;
998 }
999
1000 static int
qla82xx_flash_wait_write_finish(struct qla_hw_data * ha)1001 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
1002 {
1003 long timeout = 0;
1004 uint32_t done = 1 ;
1005 uint32_t val;
1006 int ret = 0;
1007 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1008
1009 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1010 while ((done != 0) && (ret == 0)) {
1011 ret = qla82xx_read_status_reg(ha, &val);
1012 done = val & 1;
1013 timeout++;
1014 udelay(10);
1015 cond_resched();
1016 if (timeout >= 50000) {
1017 ql_log(ql_log_warn, vha, 0xb00d,
1018 "Timeout reached waiting for write finish.\n");
1019 return -1;
1020 }
1021 }
1022 return ret;
1023 }
1024
1025 static int
qla82xx_flash_set_write_enable(struct qla_hw_data * ha)1026 qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
1027 {
1028 uint32_t val;
1029 qla82xx_wait_rom_busy(ha);
1030 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1031 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
1032 qla82xx_wait_rom_busy(ha);
1033 if (qla82xx_wait_rom_done(ha))
1034 return -1;
1035 if (qla82xx_read_status_reg(ha, &val) != 0)
1036 return -1;
1037 if ((val & 2) != 2)
1038 return -1;
1039 return 0;
1040 }
1041
1042 static int
qla82xx_write_status_reg(struct qla_hw_data * ha,uint32_t val)1043 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1044 {
1045 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1046 if (qla82xx_flash_set_write_enable(ha))
1047 return -1;
1048 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1049 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1050 if (qla82xx_wait_rom_done(ha)) {
1051 ql_log(ql_log_warn, vha, 0xb00e,
1052 "Error waiting for rom done.\n");
1053 return -1;
1054 }
1055 return qla82xx_flash_wait_write_finish(ha);
1056 }
1057
1058 static int
qla82xx_write_disable_flash(struct qla_hw_data * ha)1059 qla82xx_write_disable_flash(struct qla_hw_data *ha)
1060 {
1061 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1062 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1063 if (qla82xx_wait_rom_done(ha)) {
1064 ql_log(ql_log_warn, vha, 0xb00f,
1065 "Error waiting for rom done.\n");
1066 return -1;
1067 }
1068 return 0;
1069 }
1070
1071 static int
ql82xx_rom_lock_d(struct qla_hw_data * ha)1072 ql82xx_rom_lock_d(struct qla_hw_data *ha)
1073 {
1074 int loops = 0;
1075 uint32_t lock_owner = 0;
1076 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1077
1078 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1079 udelay(100);
1080 cond_resched();
1081 loops++;
1082 }
1083 if (loops >= 50000) {
1084 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
1085 ql_log(ql_log_warn, vha, 0xb010,
1086 "ROM lock failed, Lock Owner %u.\n", lock_owner);
1087 return -1;
1088 }
1089 return 0;
1090 }
1091
1092 static int
qla82xx_write_flash_dword(struct qla_hw_data * ha,uint32_t flashaddr,uint32_t data)1093 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1094 uint32_t data)
1095 {
1096 int ret = 0;
1097 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1098
1099 ret = ql82xx_rom_lock_d(ha);
1100 if (ret < 0) {
1101 ql_log(ql_log_warn, vha, 0xb011,
1102 "ROM lock failed.\n");
1103 return ret;
1104 }
1105
1106 ret = qla82xx_flash_set_write_enable(ha);
1107 if (ret < 0)
1108 goto done_write;
1109
1110 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1111 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1112 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1113 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1114 qla82xx_wait_rom_busy(ha);
1115 if (qla82xx_wait_rom_done(ha)) {
1116 ql_log(ql_log_warn, vha, 0xb012,
1117 "Error waiting for rom done.\n");
1118 ret = -1;
1119 goto done_write;
1120 }
1121
1122 ret = qla82xx_flash_wait_write_finish(ha);
1123
1124 done_write:
1125 qla82xx_rom_unlock(ha);
1126 return ret;
1127 }
1128
1129 /* This routine does CRB initialize sequence
1130 * to put the ISP into operational state
1131 */
1132 static int
qla82xx_pinit_from_rom(scsi_qla_host_t * vha)1133 qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
1134 {
1135 int addr, val;
1136 int i ;
1137 struct crb_addr_pair *buf;
1138 unsigned long off;
1139 unsigned offset, n;
1140 struct qla_hw_data *ha = vha->hw;
1141
1142 struct crb_addr_pair {
1143 long addr;
1144 long data;
1145 };
1146
1147 /* Halt all the individual PEGs and other blocks of the ISP */
1148 qla82xx_rom_lock(ha);
1149
1150 /* disable all I2Q */
1151 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
1152 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
1153 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1154 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1155 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1156 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1157
1158 /* disable all niu interrupts */
1159 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1160 /* disable xge rx/tx */
1161 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1162 /* disable xg1 rx/tx */
1163 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1164 /* disable sideband mac */
1165 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1166 /* disable ap0 mac */
1167 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1168 /* disable ap1 mac */
1169 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1170
1171 /* halt sre */
1172 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1173 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1174
1175 /* halt epg */
1176 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1177
1178 /* halt timers */
1179 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1180 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1181 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1182 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1183 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1184 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1185
1186 /* halt pegs */
1187 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1188 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1189 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1190 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1191 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1192 msleep(20);
1193
1194 /* big hammer */
1195 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1196 /* don't reset CAM block on reset */
1197 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1198 else
1199 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1200 qla82xx_rom_unlock(ha);
1201
1202 /* Read the signature value from the flash.
1203 * Offset 0: Contain signature (0xcafecafe)
1204 * Offset 4: Offset and number of addr/value pairs
1205 * that present in CRB initialize sequence
1206 */
1207 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1208 qla82xx_rom_fast_read(ha, 4, &n) != 0) {
1209 ql_log(ql_log_fatal, vha, 0x006e,
1210 "Error Reading crb_init area: n: %08x.\n", n);
1211 return -1;
1212 }
1213
1214 /* Offset in flash = lower 16 bits
1215 * Number of entries = upper 16 bits
1216 */
1217 offset = n & 0xffffU;
1218 n = (n >> 16) & 0xffffU;
1219
1220 /* number of addr/value pair should not exceed 1024 entries */
1221 if (n >= 1024) {
1222 ql_log(ql_log_fatal, vha, 0x0071,
1223 "Card flash not initialized:n=0x%x.\n", n);
1224 return -1;
1225 }
1226
1227 ql_log(ql_log_info, vha, 0x0072,
1228 "%d CRB init values found in ROM.\n", n);
1229
1230 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1231 if (buf == NULL) {
1232 ql_log(ql_log_fatal, vha, 0x010c,
1233 "Unable to allocate memory.\n");
1234 return -1;
1235 }
1236
1237 for (i = 0; i < n; i++) {
1238 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1239 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1240 kfree(buf);
1241 return -1;
1242 }
1243
1244 buf[i].addr = addr;
1245 buf[i].data = val;
1246 }
1247
1248 for (i = 0; i < n; i++) {
1249 /* Translate internal CRB initialization
1250 * address to PCI bus address
1251 */
1252 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1253 QLA82XX_PCI_CRBSPACE;
1254 /* Not all CRB addr/value pair to be written,
1255 * some of them are skipped
1256 */
1257
1258 /* skipping cold reboot MAGIC */
1259 if (off == QLA82XX_CAM_RAM(0x1fc))
1260 continue;
1261
1262 /* do not reset PCI */
1263 if (off == (ROMUSB_GLB + 0xbc))
1264 continue;
1265
1266 /* skip core clock, so that firmware can increase the clock */
1267 if (off == (ROMUSB_GLB + 0xc8))
1268 continue;
1269
1270 /* skip the function enable register */
1271 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1272 continue;
1273
1274 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1275 continue;
1276
1277 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1278 continue;
1279
1280 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1281 continue;
1282
1283 if (off == ADDR_ERROR) {
1284 ql_log(ql_log_fatal, vha, 0x0116,
1285 "Unknown addr: 0x%08lx.\n", buf[i].addr);
1286 continue;
1287 }
1288
1289 qla82xx_wr_32(ha, off, buf[i].data);
1290
1291 /* ISP requires much bigger delay to settle down,
1292 * else crb_window returns 0xffffffff
1293 */
1294 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1295 msleep(1000);
1296
1297 /* ISP requires millisec delay between
1298 * successive CRB register updation
1299 */
1300 msleep(1);
1301 }
1302
1303 kfree(buf);
1304
1305 /* Resetting the data and instruction cache */
1306 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1307 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1308 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1309
1310 /* Clear all protocol processing engines */
1311 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1312 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1313 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1314 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1315 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1316 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1317 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1318 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1319 return 0;
1320 }
1321
1322 static int
qla82xx_pci_mem_write_2M(struct qla_hw_data * ha,u64 off,void * data,int size)1323 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1324 u64 off, void *data, int size)
1325 {
1326 int i, j, ret = 0, loop, sz[2], off0;
1327 int scale, shift_amount, startword;
1328 uint32_t temp;
1329 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1330
1331 /*
1332 * If not MN, go check for MS or invalid.
1333 */
1334 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1335 mem_crb = QLA82XX_CRB_QDR_NET;
1336 else {
1337 mem_crb = QLA82XX_CRB_DDR_NET;
1338 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1339 return qla82xx_pci_mem_write_direct(ha,
1340 off, data, size);
1341 }
1342
1343 off0 = off & 0x7;
1344 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1345 sz[1] = size - sz[0];
1346
1347 off8 = off & 0xfffffff0;
1348 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1349 shift_amount = 4;
1350 scale = 2;
1351 startword = (off & 0xf)/8;
1352
1353 for (i = 0; i < loop; i++) {
1354 if (qla82xx_pci_mem_read_2M(ha, off8 +
1355 (i << shift_amount), &word[i * scale], 8))
1356 return -1;
1357 }
1358
1359 switch (size) {
1360 case 1:
1361 tmpw = *((uint8_t *)data);
1362 break;
1363 case 2:
1364 tmpw = *((uint16_t *)data);
1365 break;
1366 case 4:
1367 tmpw = *((uint32_t *)data);
1368 break;
1369 case 8:
1370 default:
1371 tmpw = *((uint64_t *)data);
1372 break;
1373 }
1374
1375 if (sz[0] == 8) {
1376 word[startword] = tmpw;
1377 } else {
1378 word[startword] &=
1379 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1380 word[startword] |= tmpw << (off0 * 8);
1381 }
1382 if (sz[1] != 0) {
1383 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1384 word[startword+1] |= tmpw >> (sz[0] * 8);
1385 }
1386
1387 for (i = 0; i < loop; i++) {
1388 temp = off8 + (i << shift_amount);
1389 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1390 temp = 0;
1391 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1392 temp = word[i * scale] & 0xffffffff;
1393 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1394 temp = (word[i * scale] >> 32) & 0xffffffff;
1395 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1396 temp = word[i*scale + 1] & 0xffffffff;
1397 qla82xx_wr_32(ha, mem_crb +
1398 MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1399 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1400 qla82xx_wr_32(ha, mem_crb +
1401 MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1402
1403 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1404 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1405 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1406 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1407
1408 for (j = 0; j < MAX_CTL_CHECK; j++) {
1409 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1410 if ((temp & MIU_TA_CTL_BUSY) == 0)
1411 break;
1412 }
1413
1414 if (j >= MAX_CTL_CHECK) {
1415 if (printk_ratelimit())
1416 dev_err(&ha->pdev->dev,
1417 "failed to write through agent.\n");
1418 ret = -1;
1419 break;
1420 }
1421 }
1422
1423 return ret;
1424 }
1425
1426 static int
qla82xx_fw_load_from_flash(struct qla_hw_data * ha)1427 qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1428 {
1429 int i;
1430 long size = 0;
1431 long flashaddr = ha->flt_region_bootload << 2;
1432 long memaddr = BOOTLD_START;
1433 u64 data;
1434 u32 high, low;
1435 size = (IMAGE_START - BOOTLD_START) / 8;
1436
1437 for (i = 0; i < size; i++) {
1438 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1439 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1440 return -1;
1441 }
1442 data = ((u64)high << 32) | low ;
1443 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1444 flashaddr += 8;
1445 memaddr += 8;
1446
1447 if (i % 0x1000 == 0)
1448 msleep(1);
1449 }
1450 udelay(100);
1451 read_lock(&ha->hw_lock);
1452 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1453 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1454 read_unlock(&ha->hw_lock);
1455 return 0;
1456 }
1457
1458 int
qla82xx_pci_mem_read_2M(struct qla_hw_data * ha,u64 off,void * data,int size)1459 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1460 u64 off, void *data, int size)
1461 {
1462 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1463 int shift_amount;
1464 uint32_t temp;
1465 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1466
1467 /*
1468 * If not MN, go check for MS or invalid.
1469 */
1470
1471 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1472 mem_crb = QLA82XX_CRB_QDR_NET;
1473 else {
1474 mem_crb = QLA82XX_CRB_DDR_NET;
1475 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1476 return qla82xx_pci_mem_read_direct(ha,
1477 off, data, size);
1478 }
1479
1480 off8 = off & 0xfffffff0;
1481 off0[0] = off & 0xf;
1482 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1483 shift_amount = 4;
1484 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1485 off0[1] = 0;
1486 sz[1] = size - sz[0];
1487
1488 for (i = 0; i < loop; i++) {
1489 temp = off8 + (i << shift_amount);
1490 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1491 temp = 0;
1492 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1493 temp = MIU_TA_CTL_ENABLE;
1494 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1495 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1496 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1497
1498 for (j = 0; j < MAX_CTL_CHECK; j++) {
1499 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1500 if ((temp & MIU_TA_CTL_BUSY) == 0)
1501 break;
1502 }
1503
1504 if (j >= MAX_CTL_CHECK) {
1505 if (printk_ratelimit())
1506 dev_err(&ha->pdev->dev,
1507 "failed to read through agent.\n");
1508 break;
1509 }
1510
1511 start = off0[i] >> 2;
1512 end = (off0[i] + sz[i] - 1) >> 2;
1513 for (k = start; k <= end; k++) {
1514 temp = qla82xx_rd_32(ha,
1515 mem_crb + MIU_TEST_AGT_RDDATA(k));
1516 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1517 }
1518 }
1519
1520 if (j >= MAX_CTL_CHECK)
1521 return -1;
1522
1523 if ((off0[0] & 7) == 0) {
1524 val = word[0];
1525 } else {
1526 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1527 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1528 }
1529
1530 switch (size) {
1531 case 1:
1532 *(uint8_t *)data = val;
1533 break;
1534 case 2:
1535 *(uint16_t *)data = val;
1536 break;
1537 case 4:
1538 *(uint32_t *)data = val;
1539 break;
1540 case 8:
1541 *(uint64_t *)data = val;
1542 break;
1543 }
1544 return 0;
1545 }
1546
1547
1548 static struct qla82xx_uri_table_desc *
qla82xx_get_table_desc(const u8 * unirom,int section)1549 qla82xx_get_table_desc(const u8 *unirom, int section)
1550 {
1551 uint32_t i;
1552 struct qla82xx_uri_table_desc *directory =
1553 (struct qla82xx_uri_table_desc *)&unirom[0];
1554 __le32 offset;
1555 __le32 tab_type;
1556 __le32 entries = cpu_to_le32(directory->num_entries);
1557
1558 for (i = 0; i < entries; i++) {
1559 offset = cpu_to_le32(directory->findex) +
1560 (i * cpu_to_le32(directory->entry_size));
1561 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8));
1562
1563 if (tab_type == section)
1564 return (struct qla82xx_uri_table_desc *)&unirom[offset];
1565 }
1566
1567 return NULL;
1568 }
1569
1570 static struct qla82xx_uri_data_desc *
qla82xx_get_data_desc(struct qla_hw_data * ha,u32 section,u32 idx_offset)1571 qla82xx_get_data_desc(struct qla_hw_data *ha,
1572 u32 section, u32 idx_offset)
1573 {
1574 const u8 *unirom = ha->hablob->fw->data;
1575 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset));
1576 struct qla82xx_uri_table_desc *tab_desc = NULL;
1577 __le32 offset;
1578
1579 tab_desc = qla82xx_get_table_desc(unirom, section);
1580 if (!tab_desc)
1581 return NULL;
1582
1583 offset = cpu_to_le32(tab_desc->findex) +
1584 (cpu_to_le32(tab_desc->entry_size) * idx);
1585
1586 return (struct qla82xx_uri_data_desc *)&unirom[offset];
1587 }
1588
1589 static u8 *
qla82xx_get_bootld_offset(struct qla_hw_data * ha)1590 qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1591 {
1592 u32 offset = BOOTLD_START;
1593 struct qla82xx_uri_data_desc *uri_desc = NULL;
1594
1595 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1596 uri_desc = qla82xx_get_data_desc(ha,
1597 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1598 if (uri_desc)
1599 offset = cpu_to_le32(uri_desc->findex);
1600 }
1601
1602 return (u8 *)&ha->hablob->fw->data[offset];
1603 }
1604
qla82xx_get_fw_size(struct qla_hw_data * ha)1605 static u32 qla82xx_get_fw_size(struct qla_hw_data *ha)
1606 {
1607 struct qla82xx_uri_data_desc *uri_desc = NULL;
1608
1609 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1610 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1611 QLA82XX_URI_FIRMWARE_IDX_OFF);
1612 if (uri_desc)
1613 return cpu_to_le32(uri_desc->size);
1614 }
1615
1616 return get_unaligned_le32(&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1617 }
1618
1619 static u8 *
qla82xx_get_fw_offs(struct qla_hw_data * ha)1620 qla82xx_get_fw_offs(struct qla_hw_data *ha)
1621 {
1622 u32 offset = IMAGE_START;
1623 struct qla82xx_uri_data_desc *uri_desc = NULL;
1624
1625 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1626 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1627 QLA82XX_URI_FIRMWARE_IDX_OFF);
1628 if (uri_desc)
1629 offset = cpu_to_le32(uri_desc->findex);
1630 }
1631
1632 return (u8 *)&ha->hablob->fw->data[offset];
1633 }
1634
1635 /* PCI related functions */
qla82xx_pci_region_offset(struct pci_dev * pdev,int region)1636 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1637 {
1638 unsigned long val = 0;
1639 u32 control;
1640
1641 switch (region) {
1642 case 0:
1643 val = 0;
1644 break;
1645 case 1:
1646 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1647 val = control + QLA82XX_MSIX_TBL_SPACE;
1648 break;
1649 }
1650 return val;
1651 }
1652
1653
1654 int
qla82xx_iospace_config(struct qla_hw_data * ha)1655 qla82xx_iospace_config(struct qla_hw_data *ha)
1656 {
1657 uint32_t len = 0;
1658
1659 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
1660 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c,
1661 "Failed to reserver selected regions.\n");
1662 goto iospace_error_exit;
1663 }
1664
1665 /* Use MMIO operations for all accesses. */
1666 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1667 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d,
1668 "Region #0 not an MMIO resource, aborting.\n");
1669 goto iospace_error_exit;
1670 }
1671
1672 len = pci_resource_len(ha->pdev, 0);
1673 ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len);
1674 if (!ha->nx_pcibase) {
1675 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
1676 "Cannot remap pcibase MMIO, aborting.\n");
1677 goto iospace_error_exit;
1678 }
1679
1680 /* Mapping of IO base pointer */
1681 if (IS_QLA8044(ha)) {
1682 ha->iobase = ha->nx_pcibase;
1683 } else if (IS_QLA82XX(ha)) {
1684 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11);
1685 }
1686
1687 if (!ql2xdbwr) {
1688 ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) +
1689 (ha->pdev->devfn << 12)), 4);
1690 if (!ha->nxdb_wr_ptr) {
1691 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
1692 "Cannot remap MMIO, aborting.\n");
1693 goto iospace_error_exit;
1694 }
1695
1696 /* Mapping of IO base pointer,
1697 * door bell read and write pointer
1698 */
1699 ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) +
1700 (ha->pdev->devfn * 8);
1701 } else {
1702 ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ?
1703 QLA82XX_CAMRAM_DB1 :
1704 QLA82XX_CAMRAM_DB2);
1705 }
1706
1707 ha->max_req_queues = ha->max_rsp_queues = 1;
1708 ha->msix_count = ha->max_rsp_queues + 1;
1709 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
1710 "nx_pci_base=%p iobase=%p "
1711 "max_req_queues=%d msix_count=%d.\n",
1712 ha->nx_pcibase, ha->iobase,
1713 ha->max_req_queues, ha->msix_count);
1714 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
1715 "nx_pci_base=%p iobase=%p "
1716 "max_req_queues=%d msix_count=%d.\n",
1717 ha->nx_pcibase, ha->iobase,
1718 ha->max_req_queues, ha->msix_count);
1719 return 0;
1720
1721 iospace_error_exit:
1722 return -ENOMEM;
1723 }
1724
1725 /* GS related functions */
1726
1727 /* Initialization related functions */
1728
1729 /**
1730 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1731 * @ha: HA context
1732 *
1733 * Returns 0 on success.
1734 */
1735 int
qla82xx_pci_config(scsi_qla_host_t * vha)1736 qla82xx_pci_config(scsi_qla_host_t *vha)
1737 {
1738 struct qla_hw_data *ha = vha->hw;
1739 int ret;
1740
1741 pci_set_master(ha->pdev);
1742 ret = pci_set_mwi(ha->pdev);
1743 ha->chip_revision = ha->pdev->revision;
1744 ql_dbg(ql_dbg_init, vha, 0x0043,
1745 "Chip revision:%d; pci_set_mwi() returned %d.\n",
1746 ha->chip_revision, ret);
1747 return 0;
1748 }
1749
1750 /**
1751 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1752 * @ha: HA context
1753 *
1754 * Returns 0 on success.
1755 */
1756 void
qla82xx_reset_chip(scsi_qla_host_t * vha)1757 qla82xx_reset_chip(scsi_qla_host_t *vha)
1758 {
1759 struct qla_hw_data *ha = vha->hw;
1760 ha->isp_ops->disable_intrs(ha);
1761 }
1762
qla82xx_config_rings(struct scsi_qla_host * vha)1763 void qla82xx_config_rings(struct scsi_qla_host *vha)
1764 {
1765 struct qla_hw_data *ha = vha->hw;
1766 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1767 struct init_cb_81xx *icb;
1768 struct req_que *req = ha->req_q_map[0];
1769 struct rsp_que *rsp = ha->rsp_q_map[0];
1770
1771 /* Setup ring parameters in initialization control block. */
1772 icb = (struct init_cb_81xx *)ha->init_cb;
1773 icb->request_q_outpointer = cpu_to_le16(0);
1774 icb->response_q_inpointer = cpu_to_le16(0);
1775 icb->request_q_length = cpu_to_le16(req->length);
1776 icb->response_q_length = cpu_to_le16(rsp->length);
1777 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1778 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1779 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1780 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1781
1782 WRT_REG_DWORD(®->req_q_out[0], 0);
1783 WRT_REG_DWORD(®->rsp_q_in[0], 0);
1784 WRT_REG_DWORD(®->rsp_q_out[0], 0);
1785 }
1786
1787 static int
qla82xx_fw_load_from_blob(struct qla_hw_data * ha)1788 qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
1789 {
1790 u64 *ptr64;
1791 u32 i, flashaddr, size;
1792 __le64 data;
1793
1794 size = (IMAGE_START - BOOTLD_START) / 8;
1795
1796 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
1797 flashaddr = BOOTLD_START;
1798
1799 for (i = 0; i < size; i++) {
1800 data = cpu_to_le64(ptr64[i]);
1801 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1802 return -EIO;
1803 flashaddr += 8;
1804 }
1805
1806 flashaddr = FLASH_ADDR_START;
1807 size = qla82xx_get_fw_size(ha) / 8;
1808 ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
1809
1810 for (i = 0; i < size; i++) {
1811 data = cpu_to_le64(ptr64[i]);
1812
1813 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1814 return -EIO;
1815 flashaddr += 8;
1816 }
1817 udelay(100);
1818
1819 /* Write a magic value to CAMRAM register
1820 * at a specified offset to indicate
1821 * that all data is written and
1822 * ready for firmware to initialize.
1823 */
1824 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
1825
1826 read_lock(&ha->hw_lock);
1827 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1828 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1829 read_unlock(&ha->hw_lock);
1830 return 0;
1831 }
1832
1833 static int
qla82xx_set_product_offset(struct qla_hw_data * ha)1834 qla82xx_set_product_offset(struct qla_hw_data *ha)
1835 {
1836 struct qla82xx_uri_table_desc *ptab_desc = NULL;
1837 const uint8_t *unirom = ha->hablob->fw->data;
1838 uint32_t i;
1839 __le32 entries;
1840 __le32 flags, file_chiprev, offset;
1841 uint8_t chiprev = ha->chip_revision;
1842 /* Hardcoding mn_present flag for P3P */
1843 int mn_present = 0;
1844 uint32_t flagbit;
1845
1846 ptab_desc = qla82xx_get_table_desc(unirom,
1847 QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
1848 if (!ptab_desc)
1849 return -1;
1850
1851 entries = cpu_to_le32(ptab_desc->num_entries);
1852
1853 for (i = 0; i < entries; i++) {
1854 offset = cpu_to_le32(ptab_desc->findex) +
1855 (i * cpu_to_le32(ptab_desc->entry_size));
1856 flags = cpu_to_le32(*((int *)&unirom[offset] +
1857 QLA82XX_URI_FLAGS_OFF));
1858 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] +
1859 QLA82XX_URI_CHIP_REV_OFF));
1860
1861 flagbit = mn_present ? 1 : 2;
1862
1863 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1864 ha->file_prd_off = offset;
1865 return 0;
1866 }
1867 }
1868 return -1;
1869 }
1870
1871 static int
qla82xx_validate_firmware_blob(scsi_qla_host_t * vha,uint8_t fw_type)1872 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1873 {
1874 __le32 val;
1875 uint32_t min_size;
1876 struct qla_hw_data *ha = vha->hw;
1877 const struct firmware *fw = ha->hablob->fw;
1878
1879 ha->fw_type = fw_type;
1880
1881 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1882 if (qla82xx_set_product_offset(ha))
1883 return -EINVAL;
1884
1885 min_size = QLA82XX_URI_FW_MIN_SIZE;
1886 } else {
1887 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1888 if ((__force u32)val != QLA82XX_BDINFO_MAGIC)
1889 return -EINVAL;
1890
1891 min_size = QLA82XX_FW_MIN_SIZE;
1892 }
1893
1894 if (fw->size < min_size)
1895 return -EINVAL;
1896 return 0;
1897 }
1898
1899 static int
qla82xx_check_cmdpeg_state(struct qla_hw_data * ha)1900 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
1901 {
1902 u32 val = 0;
1903 int retries = 60;
1904 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1905
1906 do {
1907 read_lock(&ha->hw_lock);
1908 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
1909 read_unlock(&ha->hw_lock);
1910
1911 switch (val) {
1912 case PHAN_INITIALIZE_COMPLETE:
1913 case PHAN_INITIALIZE_ACK:
1914 return QLA_SUCCESS;
1915 case PHAN_INITIALIZE_FAILED:
1916 break;
1917 default:
1918 break;
1919 }
1920 ql_log(ql_log_info, vha, 0x00a8,
1921 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1922 val, retries);
1923
1924 msleep(500);
1925
1926 } while (--retries);
1927
1928 ql_log(ql_log_fatal, vha, 0x00a9,
1929 "Cmd Peg initialization failed: 0x%x.\n", val);
1930
1931 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1932 read_lock(&ha->hw_lock);
1933 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1934 read_unlock(&ha->hw_lock);
1935 return QLA_FUNCTION_FAILED;
1936 }
1937
1938 static int
qla82xx_check_rcvpeg_state(struct qla_hw_data * ha)1939 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
1940 {
1941 u32 val = 0;
1942 int retries = 60;
1943 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1944
1945 do {
1946 read_lock(&ha->hw_lock);
1947 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
1948 read_unlock(&ha->hw_lock);
1949
1950 switch (val) {
1951 case PHAN_INITIALIZE_COMPLETE:
1952 case PHAN_INITIALIZE_ACK:
1953 return QLA_SUCCESS;
1954 case PHAN_INITIALIZE_FAILED:
1955 break;
1956 default:
1957 break;
1958 }
1959 ql_log(ql_log_info, vha, 0x00ab,
1960 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1961 val, retries);
1962
1963 msleep(500);
1964
1965 } while (--retries);
1966
1967 ql_log(ql_log_fatal, vha, 0x00ac,
1968 "Rcv Peg initializatin failed: 0x%x.\n", val);
1969 read_lock(&ha->hw_lock);
1970 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
1971 read_unlock(&ha->hw_lock);
1972 return QLA_FUNCTION_FAILED;
1973 }
1974
1975 /* ISR related functions */
1976 static struct qla82xx_legacy_intr_set legacy_intr[] = \
1977 QLA82XX_LEGACY_INTR_CONFIG;
1978
1979 /*
1980 * qla82xx_mbx_completion() - Process mailbox command completions.
1981 * @ha: SCSI driver HA context
1982 * @mb0: Mailbox0 register
1983 */
1984 void
qla82xx_mbx_completion(scsi_qla_host_t * vha,uint16_t mb0)1985 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
1986 {
1987 uint16_t cnt;
1988 uint16_t __iomem *wptr;
1989 struct qla_hw_data *ha = vha->hw;
1990 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1991 wptr = (uint16_t __iomem *)®->mailbox_out[1];
1992
1993 /* Load return mailbox registers. */
1994 ha->flags.mbox_int = 1;
1995 ha->mailbox_out[0] = mb0;
1996
1997 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
1998 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
1999 wptr++;
2000 }
2001
2002 if (!ha->mcp)
2003 ql_dbg(ql_dbg_async, vha, 0x5053,
2004 "MBX pointer ERROR.\n");
2005 }
2006
2007 /*
2008 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
2009 * @irq:
2010 * @dev_id: SCSI driver HA context
2011 * @regs:
2012 *
2013 * Called by system whenever the host adapter generates an interrupt.
2014 *
2015 * Returns handled flag.
2016 */
2017 irqreturn_t
qla82xx_intr_handler(int irq,void * dev_id)2018 qla82xx_intr_handler(int irq, void *dev_id)
2019 {
2020 scsi_qla_host_t *vha;
2021 struct qla_hw_data *ha;
2022 struct rsp_que *rsp;
2023 struct device_reg_82xx __iomem *reg;
2024 int status = 0, status1 = 0;
2025 unsigned long flags;
2026 unsigned long iter;
2027 uint32_t stat = 0;
2028 uint16_t mb[4];
2029
2030 rsp = (struct rsp_que *) dev_id;
2031 if (!rsp) {
2032 ql_log(ql_log_info, NULL, 0xb053,
2033 "%s: NULL response queue pointer.\n", __func__);
2034 return IRQ_NONE;
2035 }
2036 ha = rsp->hw;
2037
2038 if (!ha->flags.msi_enabled) {
2039 status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
2040 if (!(status & ha->nx_legacy_intr.int_vec_bit))
2041 return IRQ_NONE;
2042
2043 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
2044 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
2045 return IRQ_NONE;
2046 }
2047
2048 /* clear the interrupt */
2049 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
2050
2051 /* read twice to ensure write is flushed */
2052 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2053 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2054
2055 reg = &ha->iobase->isp82;
2056
2057 spin_lock_irqsave(&ha->hardware_lock, flags);
2058 vha = pci_get_drvdata(ha->pdev);
2059 for (iter = 1; iter--; ) {
2060
2061 if (RD_REG_DWORD(®->host_int)) {
2062 stat = RD_REG_DWORD(®->host_status);
2063
2064 switch (stat & 0xff) {
2065 case 0x1:
2066 case 0x2:
2067 case 0x10:
2068 case 0x11:
2069 qla82xx_mbx_completion(vha, MSW(stat));
2070 status |= MBX_INTERRUPT;
2071 break;
2072 case 0x12:
2073 mb[0] = MSW(stat);
2074 mb[1] = RD_REG_WORD(®->mailbox_out[1]);
2075 mb[2] = RD_REG_WORD(®->mailbox_out[2]);
2076 mb[3] = RD_REG_WORD(®->mailbox_out[3]);
2077 qla2x00_async_event(vha, rsp, mb);
2078 break;
2079 case 0x13:
2080 qla24xx_process_response_queue(vha, rsp);
2081 break;
2082 default:
2083 ql_dbg(ql_dbg_async, vha, 0x5054,
2084 "Unrecognized interrupt type (%d).\n",
2085 stat & 0xff);
2086 break;
2087 }
2088 }
2089 WRT_REG_DWORD(®->host_int, 0);
2090 }
2091
2092 qla2x00_handle_mbx_completion(ha, status);
2093 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2094
2095 if (!ha->flags.msi_enabled)
2096 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2097
2098 return IRQ_HANDLED;
2099 }
2100
2101 irqreturn_t
qla82xx_msix_default(int irq,void * dev_id)2102 qla82xx_msix_default(int irq, void *dev_id)
2103 {
2104 scsi_qla_host_t *vha;
2105 struct qla_hw_data *ha;
2106 struct rsp_que *rsp;
2107 struct device_reg_82xx __iomem *reg;
2108 int status = 0;
2109 unsigned long flags;
2110 uint32_t stat = 0;
2111 uint32_t host_int = 0;
2112 uint16_t mb[4];
2113
2114 rsp = (struct rsp_que *) dev_id;
2115 if (!rsp) {
2116 printk(KERN_INFO
2117 "%s(): NULL response queue pointer.\n", __func__);
2118 return IRQ_NONE;
2119 }
2120 ha = rsp->hw;
2121
2122 reg = &ha->iobase->isp82;
2123
2124 spin_lock_irqsave(&ha->hardware_lock, flags);
2125 vha = pci_get_drvdata(ha->pdev);
2126 do {
2127 host_int = RD_REG_DWORD(®->host_int);
2128 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2129 break;
2130 if (host_int) {
2131 stat = RD_REG_DWORD(®->host_status);
2132
2133 switch (stat & 0xff) {
2134 case 0x1:
2135 case 0x2:
2136 case 0x10:
2137 case 0x11:
2138 qla82xx_mbx_completion(vha, MSW(stat));
2139 status |= MBX_INTERRUPT;
2140 break;
2141 case 0x12:
2142 mb[0] = MSW(stat);
2143 mb[1] = RD_REG_WORD(®->mailbox_out[1]);
2144 mb[2] = RD_REG_WORD(®->mailbox_out[2]);
2145 mb[3] = RD_REG_WORD(®->mailbox_out[3]);
2146 qla2x00_async_event(vha, rsp, mb);
2147 break;
2148 case 0x13:
2149 qla24xx_process_response_queue(vha, rsp);
2150 break;
2151 default:
2152 ql_dbg(ql_dbg_async, vha, 0x5041,
2153 "Unrecognized interrupt type (%d).\n",
2154 stat & 0xff);
2155 break;
2156 }
2157 }
2158 WRT_REG_DWORD(®->host_int, 0);
2159 } while (0);
2160
2161 qla2x00_handle_mbx_completion(ha, status);
2162 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2163
2164 return IRQ_HANDLED;
2165 }
2166
2167 irqreturn_t
qla82xx_msix_rsp_q(int irq,void * dev_id)2168 qla82xx_msix_rsp_q(int irq, void *dev_id)
2169 {
2170 scsi_qla_host_t *vha;
2171 struct qla_hw_data *ha;
2172 struct rsp_que *rsp;
2173 struct device_reg_82xx __iomem *reg;
2174 unsigned long flags;
2175 uint32_t host_int = 0;
2176
2177 rsp = (struct rsp_que *) dev_id;
2178 if (!rsp) {
2179 printk(KERN_INFO
2180 "%s(): NULL response queue pointer.\n", __func__);
2181 return IRQ_NONE;
2182 }
2183
2184 ha = rsp->hw;
2185 reg = &ha->iobase->isp82;
2186 spin_lock_irqsave(&ha->hardware_lock, flags);
2187 vha = pci_get_drvdata(ha->pdev);
2188 host_int = RD_REG_DWORD(®->host_int);
2189 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2190 goto out;
2191 qla24xx_process_response_queue(vha, rsp);
2192 WRT_REG_DWORD(®->host_int, 0);
2193 out:
2194 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2195 return IRQ_HANDLED;
2196 }
2197
2198 void
qla82xx_poll(int irq,void * dev_id)2199 qla82xx_poll(int irq, void *dev_id)
2200 {
2201 scsi_qla_host_t *vha;
2202 struct qla_hw_data *ha;
2203 struct rsp_que *rsp;
2204 struct device_reg_82xx __iomem *reg;
2205 int status = 0;
2206 uint32_t stat;
2207 uint32_t host_int = 0;
2208 uint16_t mb[4];
2209 unsigned long flags;
2210
2211 rsp = (struct rsp_que *) dev_id;
2212 if (!rsp) {
2213 printk(KERN_INFO
2214 "%s(): NULL response queue pointer.\n", __func__);
2215 return;
2216 }
2217 ha = rsp->hw;
2218
2219 reg = &ha->iobase->isp82;
2220 spin_lock_irqsave(&ha->hardware_lock, flags);
2221 vha = pci_get_drvdata(ha->pdev);
2222
2223 host_int = RD_REG_DWORD(®->host_int);
2224 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2225 goto out;
2226 if (host_int) {
2227 stat = RD_REG_DWORD(®->host_status);
2228 switch (stat & 0xff) {
2229 case 0x1:
2230 case 0x2:
2231 case 0x10:
2232 case 0x11:
2233 qla82xx_mbx_completion(vha, MSW(stat));
2234 status |= MBX_INTERRUPT;
2235 break;
2236 case 0x12:
2237 mb[0] = MSW(stat);
2238 mb[1] = RD_REG_WORD(®->mailbox_out[1]);
2239 mb[2] = RD_REG_WORD(®->mailbox_out[2]);
2240 mb[3] = RD_REG_WORD(®->mailbox_out[3]);
2241 qla2x00_async_event(vha, rsp, mb);
2242 break;
2243 case 0x13:
2244 qla24xx_process_response_queue(vha, rsp);
2245 break;
2246 default:
2247 ql_dbg(ql_dbg_p3p, vha, 0xb013,
2248 "Unrecognized interrupt type (%d).\n",
2249 stat * 0xff);
2250 break;
2251 }
2252 WRT_REG_DWORD(®->host_int, 0);
2253 }
2254 out:
2255 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2256 }
2257
2258 void
qla82xx_enable_intrs(struct qla_hw_data * ha)2259 qla82xx_enable_intrs(struct qla_hw_data *ha)
2260 {
2261 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2262 qla82xx_mbx_intr_enable(vha);
2263 spin_lock_irq(&ha->hardware_lock);
2264 if (IS_QLA8044(ha))
2265 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0);
2266 else
2267 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2268 spin_unlock_irq(&ha->hardware_lock);
2269 ha->interrupts_on = 1;
2270 }
2271
2272 void
qla82xx_disable_intrs(struct qla_hw_data * ha)2273 qla82xx_disable_intrs(struct qla_hw_data *ha)
2274 {
2275 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2276 qla82xx_mbx_intr_disable(vha);
2277 spin_lock_irq(&ha->hardware_lock);
2278 if (IS_QLA8044(ha))
2279 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1);
2280 else
2281 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2282 spin_unlock_irq(&ha->hardware_lock);
2283 ha->interrupts_on = 0;
2284 }
2285
qla82xx_init_flags(struct qla_hw_data * ha)2286 void qla82xx_init_flags(struct qla_hw_data *ha)
2287 {
2288 struct qla82xx_legacy_intr_set *nx_legacy_intr;
2289
2290 /* ISP 8021 initializations */
2291 rwlock_init(&ha->hw_lock);
2292 ha->qdr_sn_window = -1;
2293 ha->ddr_mn_window = -1;
2294 ha->curr_window = 255;
2295 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2296 nx_legacy_intr = &legacy_intr[ha->portnum];
2297 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2298 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2299 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2300 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2301 }
2302
2303 static inline void
qla82xx_set_idc_version(scsi_qla_host_t * vha)2304 qla82xx_set_idc_version(scsi_qla_host_t *vha)
2305 {
2306 int idc_ver;
2307 uint32_t drv_active;
2308 struct qla_hw_data *ha = vha->hw;
2309
2310 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2311 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) {
2312 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
2313 QLA82XX_IDC_VERSION);
2314 ql_log(ql_log_info, vha, 0xb082,
2315 "IDC version updated to %d\n", QLA82XX_IDC_VERSION);
2316 } else {
2317 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION);
2318 if (idc_ver != QLA82XX_IDC_VERSION)
2319 ql_log(ql_log_info, vha, 0xb083,
2320 "qla2xxx driver IDC version %d is not compatible "
2321 "with IDC version %d of the other drivers\n",
2322 QLA82XX_IDC_VERSION, idc_ver);
2323 }
2324 }
2325
2326 inline void
qla82xx_set_drv_active(scsi_qla_host_t * vha)2327 qla82xx_set_drv_active(scsi_qla_host_t *vha)
2328 {
2329 uint32_t drv_active;
2330 struct qla_hw_data *ha = vha->hw;
2331
2332 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2333
2334 /* If reset value is all FF's, initialize DRV_ACTIVE */
2335 if (drv_active == 0xffffffff) {
2336 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
2337 QLA82XX_DRV_NOT_ACTIVE);
2338 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2339 }
2340 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2341 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2342 }
2343
2344 inline void
qla82xx_clear_drv_active(struct qla_hw_data * ha)2345 qla82xx_clear_drv_active(struct qla_hw_data *ha)
2346 {
2347 uint32_t drv_active;
2348
2349 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2350 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2351 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2352 }
2353
2354 static inline int
qla82xx_need_reset(struct qla_hw_data * ha)2355 qla82xx_need_reset(struct qla_hw_data *ha)
2356 {
2357 uint32_t drv_state;
2358 int rval;
2359
2360 if (ha->flags.nic_core_reset_owner)
2361 return 1;
2362 else {
2363 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2364 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2365 return rval;
2366 }
2367 }
2368
2369 static inline void
qla82xx_set_rst_ready(struct qla_hw_data * ha)2370 qla82xx_set_rst_ready(struct qla_hw_data *ha)
2371 {
2372 uint32_t drv_state;
2373 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2374
2375 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2376
2377 /* If reset value is all FF's, initialize DRV_STATE */
2378 if (drv_state == 0xffffffff) {
2379 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
2380 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2381 }
2382 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2383 ql_dbg(ql_dbg_init, vha, 0x00bb,
2384 "drv_state = 0x%08x.\n", drv_state);
2385 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2386 }
2387
2388 static inline void
qla82xx_clear_rst_ready(struct qla_hw_data * ha)2389 qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2390 {
2391 uint32_t drv_state;
2392
2393 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2394 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2395 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2396 }
2397
2398 static inline void
qla82xx_set_qsnt_ready(struct qla_hw_data * ha)2399 qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2400 {
2401 uint32_t qsnt_state;
2402
2403 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2404 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2405 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2406 }
2407
2408 void
qla82xx_clear_qsnt_ready(scsi_qla_host_t * vha)2409 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha)
2410 {
2411 struct qla_hw_data *ha = vha->hw;
2412 uint32_t qsnt_state;
2413
2414 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2415 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2416 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2417 }
2418
2419 static int
qla82xx_load_fw(scsi_qla_host_t * vha)2420 qla82xx_load_fw(scsi_qla_host_t *vha)
2421 {
2422 int rst;
2423 struct fw_blob *blob;
2424 struct qla_hw_data *ha = vha->hw;
2425
2426 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
2427 ql_log(ql_log_fatal, vha, 0x009f,
2428 "Error during CRB initialization.\n");
2429 return QLA_FUNCTION_FAILED;
2430 }
2431 udelay(500);
2432
2433 /* Bring QM and CAMRAM out of reset */
2434 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2435 rst &= ~((1 << 28) | (1 << 24));
2436 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2437
2438 /*
2439 * FW Load priority:
2440 * 1) Operational firmware residing in flash.
2441 * 2) Firmware via request-firmware interface (.bin file).
2442 */
2443 if (ql2xfwloadbin == 2)
2444 goto try_blob_fw;
2445
2446 ql_log(ql_log_info, vha, 0x00a0,
2447 "Attempting to load firmware from flash.\n");
2448
2449 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
2450 ql_log(ql_log_info, vha, 0x00a1,
2451 "Firmware loaded successfully from flash.\n");
2452 return QLA_SUCCESS;
2453 } else {
2454 ql_log(ql_log_warn, vha, 0x0108,
2455 "Firmware load from flash failed.\n");
2456 }
2457
2458 try_blob_fw:
2459 ql_log(ql_log_info, vha, 0x00a2,
2460 "Attempting to load firmware from blob.\n");
2461
2462 /* Load firmware blob. */
2463 blob = ha->hablob = qla2x00_request_firmware(vha);
2464 if (!blob) {
2465 ql_log(ql_log_fatal, vha, 0x00a3,
2466 "Firmware image not present.\n");
2467 goto fw_load_failed;
2468 }
2469
2470 /* Validating firmware blob */
2471 if (qla82xx_validate_firmware_blob(vha,
2472 QLA82XX_FLASH_ROMIMAGE)) {
2473 /* Fallback to URI format */
2474 if (qla82xx_validate_firmware_blob(vha,
2475 QLA82XX_UNIFIED_ROMIMAGE)) {
2476 ql_log(ql_log_fatal, vha, 0x00a4,
2477 "No valid firmware image found.\n");
2478 return QLA_FUNCTION_FAILED;
2479 }
2480 }
2481
2482 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
2483 ql_log(ql_log_info, vha, 0x00a5,
2484 "Firmware loaded successfully from binary blob.\n");
2485 return QLA_SUCCESS;
2486 }
2487
2488 ql_log(ql_log_fatal, vha, 0x00a6,
2489 "Firmware load failed for binary blob.\n");
2490 blob->fw = NULL;
2491 blob = NULL;
2492
2493 fw_load_failed:
2494 return QLA_FUNCTION_FAILED;
2495 }
2496
2497 int
qla82xx_start_firmware(scsi_qla_host_t * vha)2498 qla82xx_start_firmware(scsi_qla_host_t *vha)
2499 {
2500 uint16_t lnk;
2501 struct qla_hw_data *ha = vha->hw;
2502
2503 /* scrub dma mask expansion register */
2504 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
2505
2506 /* Put both the PEG CMD and RCV PEG to default state
2507 * of 0 before resetting the hardware
2508 */
2509 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2510 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2511
2512 /* Overwrite stale initialization register values */
2513 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2514 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2515
2516 if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
2517 ql_log(ql_log_fatal, vha, 0x00a7,
2518 "Error trying to start fw.\n");
2519 return QLA_FUNCTION_FAILED;
2520 }
2521
2522 /* Handshake with the card before we register the devices. */
2523 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
2524 ql_log(ql_log_fatal, vha, 0x00aa,
2525 "Error during card handshake.\n");
2526 return QLA_FUNCTION_FAILED;
2527 }
2528
2529 /* Negotiated Link width */
2530 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
2531 ha->link_width = (lnk >> 4) & 0x3f;
2532
2533 /* Synchronize with Receive peg */
2534 return qla82xx_check_rcvpeg_state(ha);
2535 }
2536
2537 static uint32_t *
qla82xx_read_flash_data(scsi_qla_host_t * vha,uint32_t * dwptr,uint32_t faddr,uint32_t length)2538 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
2539 uint32_t length)
2540 {
2541 uint32_t i;
2542 uint32_t val;
2543 struct qla_hw_data *ha = vha->hw;
2544
2545 /* Dword reads to flash. */
2546 for (i = 0; i < length/4; i++, faddr += 4) {
2547 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
2548 ql_log(ql_log_warn, vha, 0x0106,
2549 "Do ROM fast read failed.\n");
2550 goto done_read;
2551 }
2552 dwptr[i] = cpu_to_le32(val);
2553 }
2554 done_read:
2555 return dwptr;
2556 }
2557
2558 static int
qla82xx_unprotect_flash(struct qla_hw_data * ha)2559 qla82xx_unprotect_flash(struct qla_hw_data *ha)
2560 {
2561 int ret;
2562 uint32_t val;
2563 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2564
2565 ret = ql82xx_rom_lock_d(ha);
2566 if (ret < 0) {
2567 ql_log(ql_log_warn, vha, 0xb014,
2568 "ROM Lock failed.\n");
2569 return ret;
2570 }
2571
2572 ret = qla82xx_read_status_reg(ha, &val);
2573 if (ret < 0)
2574 goto done_unprotect;
2575
2576 val &= ~(BLOCK_PROTECT_BITS << 2);
2577 ret = qla82xx_write_status_reg(ha, val);
2578 if (ret < 0) {
2579 val |= (BLOCK_PROTECT_BITS << 2);
2580 qla82xx_write_status_reg(ha, val);
2581 }
2582
2583 if (qla82xx_write_disable_flash(ha) != 0)
2584 ql_log(ql_log_warn, vha, 0xb015,
2585 "Write disable failed.\n");
2586
2587 done_unprotect:
2588 qla82xx_rom_unlock(ha);
2589 return ret;
2590 }
2591
2592 static int
qla82xx_protect_flash(struct qla_hw_data * ha)2593 qla82xx_protect_flash(struct qla_hw_data *ha)
2594 {
2595 int ret;
2596 uint32_t val;
2597 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2598
2599 ret = ql82xx_rom_lock_d(ha);
2600 if (ret < 0) {
2601 ql_log(ql_log_warn, vha, 0xb016,
2602 "ROM Lock failed.\n");
2603 return ret;
2604 }
2605
2606 ret = qla82xx_read_status_reg(ha, &val);
2607 if (ret < 0)
2608 goto done_protect;
2609
2610 val |= (BLOCK_PROTECT_BITS << 2);
2611 /* LOCK all sectors */
2612 ret = qla82xx_write_status_reg(ha, val);
2613 if (ret < 0)
2614 ql_log(ql_log_warn, vha, 0xb017,
2615 "Write status register failed.\n");
2616
2617 if (qla82xx_write_disable_flash(ha) != 0)
2618 ql_log(ql_log_warn, vha, 0xb018,
2619 "Write disable failed.\n");
2620 done_protect:
2621 qla82xx_rom_unlock(ha);
2622 return ret;
2623 }
2624
2625 static int
qla82xx_erase_sector(struct qla_hw_data * ha,int addr)2626 qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
2627 {
2628 int ret = 0;
2629 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2630
2631 ret = ql82xx_rom_lock_d(ha);
2632 if (ret < 0) {
2633 ql_log(ql_log_warn, vha, 0xb019,
2634 "ROM Lock failed.\n");
2635 return ret;
2636 }
2637
2638 qla82xx_flash_set_write_enable(ha);
2639 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
2640 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
2641 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
2642
2643 if (qla82xx_wait_rom_done(ha)) {
2644 ql_log(ql_log_warn, vha, 0xb01a,
2645 "Error waiting for rom done.\n");
2646 ret = -1;
2647 goto done;
2648 }
2649 ret = qla82xx_flash_wait_write_finish(ha);
2650 done:
2651 qla82xx_rom_unlock(ha);
2652 return ret;
2653 }
2654
2655 /*
2656 * Address and length are byte address
2657 */
2658 uint8_t *
qla82xx_read_optrom_data(struct scsi_qla_host * vha,uint8_t * buf,uint32_t offset,uint32_t length)2659 qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2660 uint32_t offset, uint32_t length)
2661 {
2662 scsi_block_requests(vha->host);
2663 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length);
2664 scsi_unblock_requests(vha->host);
2665 return buf;
2666 }
2667
2668 static int
qla82xx_write_flash_data(struct scsi_qla_host * vha,uint32_t * dwptr,uint32_t faddr,uint32_t dwords)2669 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr,
2670 uint32_t faddr, uint32_t dwords)
2671 {
2672 int ret;
2673 uint32_t liter;
2674 uint32_t rest_addr;
2675 dma_addr_t optrom_dma;
2676 void *optrom = NULL;
2677 int page_mode = 0;
2678 struct qla_hw_data *ha = vha->hw;
2679
2680 ret = -1;
2681
2682 /* Prepare burst-capable write on supported ISPs. */
2683 if (page_mode && !(faddr & 0xfff) &&
2684 dwords > OPTROM_BURST_DWORDS) {
2685 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2686 &optrom_dma, GFP_KERNEL);
2687 if (!optrom) {
2688 ql_log(ql_log_warn, vha, 0xb01b,
2689 "Unable to allocate memory "
2690 "for optrom burst write (%x KB).\n",
2691 OPTROM_BURST_SIZE / 1024);
2692 }
2693 }
2694
2695 rest_addr = ha->fdt_block_size - 1;
2696
2697 ret = qla82xx_unprotect_flash(ha);
2698 if (ret) {
2699 ql_log(ql_log_warn, vha, 0xb01c,
2700 "Unable to unprotect flash for update.\n");
2701 goto write_done;
2702 }
2703
2704 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
2705 /* Are we at the beginning of a sector? */
2706 if ((faddr & rest_addr) == 0) {
2707
2708 ret = qla82xx_erase_sector(ha, faddr);
2709 if (ret) {
2710 ql_log(ql_log_warn, vha, 0xb01d,
2711 "Unable to erase sector: address=%x.\n",
2712 faddr);
2713 break;
2714 }
2715 }
2716
2717 /* Go with burst-write. */
2718 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
2719 /* Copy data to DMA'ble buffer. */
2720 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
2721
2722 ret = qla2x00_load_ram(vha, optrom_dma,
2723 (ha->flash_data_off | faddr),
2724 OPTROM_BURST_DWORDS);
2725 if (ret != QLA_SUCCESS) {
2726 ql_log(ql_log_warn, vha, 0xb01e,
2727 "Unable to burst-write optrom segment "
2728 "(%x/%x/%llx).\n", ret,
2729 (ha->flash_data_off | faddr),
2730 (unsigned long long)optrom_dma);
2731 ql_log(ql_log_warn, vha, 0xb01f,
2732 "Reverting to slow-write.\n");
2733
2734 dma_free_coherent(&ha->pdev->dev,
2735 OPTROM_BURST_SIZE, optrom, optrom_dma);
2736 optrom = NULL;
2737 } else {
2738 liter += OPTROM_BURST_DWORDS - 1;
2739 faddr += OPTROM_BURST_DWORDS - 1;
2740 dwptr += OPTROM_BURST_DWORDS - 1;
2741 continue;
2742 }
2743 }
2744
2745 ret = qla82xx_write_flash_dword(ha, faddr,
2746 cpu_to_le32(*dwptr));
2747 if (ret) {
2748 ql_dbg(ql_dbg_p3p, vha, 0xb020,
2749 "Unable to program flash address=%x data=%x.\n",
2750 faddr, *dwptr);
2751 break;
2752 }
2753 }
2754
2755 ret = qla82xx_protect_flash(ha);
2756 if (ret)
2757 ql_log(ql_log_warn, vha, 0xb021,
2758 "Unable to protect flash after update.\n");
2759 write_done:
2760 if (optrom)
2761 dma_free_coherent(&ha->pdev->dev,
2762 OPTROM_BURST_SIZE, optrom, optrom_dma);
2763 return ret;
2764 }
2765
2766 int
qla82xx_write_optrom_data(struct scsi_qla_host * vha,uint8_t * buf,uint32_t offset,uint32_t length)2767 qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2768 uint32_t offset, uint32_t length)
2769 {
2770 int rval;
2771
2772 /* Suspend HBA. */
2773 scsi_block_requests(vha->host);
2774 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset,
2775 length >> 2);
2776 scsi_unblock_requests(vha->host);
2777
2778 /* Convert return ISP82xx to generic */
2779 if (rval)
2780 rval = QLA_FUNCTION_FAILED;
2781 else
2782 rval = QLA_SUCCESS;
2783 return rval;
2784 }
2785
2786 void
qla82xx_start_iocbs(scsi_qla_host_t * vha)2787 qla82xx_start_iocbs(scsi_qla_host_t *vha)
2788 {
2789 struct qla_hw_data *ha = vha->hw;
2790 struct req_que *req = ha->req_q_map[0];
2791 uint32_t dbval;
2792
2793 /* Adjust ring index. */
2794 req->ring_index++;
2795 if (req->ring_index == req->length) {
2796 req->ring_index = 0;
2797 req->ring_ptr = req->ring;
2798 } else
2799 req->ring_ptr++;
2800
2801 dbval = 0x04 | (ha->portnum << 5);
2802
2803 dbval = dbval | (req->id << 8) | (req->ring_index << 16);
2804 if (ql2xdbwr)
2805 qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval);
2806 else {
2807 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
2808 wmb();
2809 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
2810 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
2811 wmb();
2812 }
2813 }
2814 }
2815
2816 static void
qla82xx_rom_lock_recovery(struct qla_hw_data * ha)2817 qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
2818 {
2819 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2820 uint32_t lock_owner = 0;
2821
2822 if (qla82xx_rom_lock(ha)) {
2823 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
2824 /* Someone else is holding the lock. */
2825 ql_log(ql_log_info, vha, 0xb022,
2826 "Resetting rom_lock, Lock Owner %u.\n", lock_owner);
2827 }
2828 /*
2829 * Either we got the lock, or someone
2830 * else died while holding it.
2831 * In either case, unlock.
2832 */
2833 qla82xx_rom_unlock(ha);
2834 }
2835
2836 /*
2837 * qla82xx_device_bootstrap
2838 * Initialize device, set DEV_READY, start fw
2839 *
2840 * Note:
2841 * IDC lock must be held upon entry
2842 *
2843 * Return:
2844 * Success : 0
2845 * Failed : 1
2846 */
2847 static int
qla82xx_device_bootstrap(scsi_qla_host_t * vha)2848 qla82xx_device_bootstrap(scsi_qla_host_t *vha)
2849 {
2850 int rval = QLA_SUCCESS;
2851 int i;
2852 uint32_t old_count, count;
2853 struct qla_hw_data *ha = vha->hw;
2854 int need_reset = 0;
2855
2856 need_reset = qla82xx_need_reset(ha);
2857
2858 if (need_reset) {
2859 /* We are trying to perform a recovery here. */
2860 if (ha->flags.isp82xx_fw_hung)
2861 qla82xx_rom_lock_recovery(ha);
2862 } else {
2863 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2864 for (i = 0; i < 10; i++) {
2865 msleep(200);
2866 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2867 if (count != old_count) {
2868 rval = QLA_SUCCESS;
2869 goto dev_ready;
2870 }
2871 }
2872 qla82xx_rom_lock_recovery(ha);
2873 }
2874
2875 /* set to DEV_INITIALIZING */
2876 ql_log(ql_log_info, vha, 0x009e,
2877 "HW State: INITIALIZING.\n");
2878 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
2879
2880 qla82xx_idc_unlock(ha);
2881 rval = qla82xx_start_firmware(vha);
2882 qla82xx_idc_lock(ha);
2883
2884 if (rval != QLA_SUCCESS) {
2885 ql_log(ql_log_fatal, vha, 0x00ad,
2886 "HW State: FAILED.\n");
2887 qla82xx_clear_drv_active(ha);
2888 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED);
2889 return rval;
2890 }
2891
2892 dev_ready:
2893 ql_log(ql_log_info, vha, 0x00ae,
2894 "HW State: READY.\n");
2895 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
2896
2897 return QLA_SUCCESS;
2898 }
2899
2900 /*
2901 * qla82xx_need_qsnt_handler
2902 * Code to start quiescence sequence
2903 *
2904 * Note:
2905 * IDC lock must be held upon entry
2906 *
2907 * Return: void
2908 */
2909
2910 static void
qla82xx_need_qsnt_handler(scsi_qla_host_t * vha)2911 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha)
2912 {
2913 struct qla_hw_data *ha = vha->hw;
2914 uint32_t dev_state, drv_state, drv_active;
2915 unsigned long reset_timeout;
2916
2917 if (vha->flags.online) {
2918 /*Block any further I/O and wait for pending cmnds to complete*/
2919 qla2x00_quiesce_io(vha);
2920 }
2921
2922 /* Set the quiescence ready bit */
2923 qla82xx_set_qsnt_ready(ha);
2924
2925 /*wait for 30 secs for other functions to ack */
2926 reset_timeout = jiffies + (30 * HZ);
2927
2928 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2929 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2930 /* Its 2 that is written when qsnt is acked, moving one bit */
2931 drv_active = drv_active << 0x01;
2932
2933 while (drv_state != drv_active) {
2934
2935 if (time_after_eq(jiffies, reset_timeout)) {
2936 /* quiescence timeout, other functions didn't ack
2937 * changing the state to DEV_READY
2938 */
2939 ql_log(ql_log_info, vha, 0xb023,
2940 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
2941 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME,
2942 drv_active, drv_state);
2943 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2944 QLA8XXX_DEV_READY);
2945 ql_log(ql_log_info, vha, 0xb025,
2946 "HW State: DEV_READY.\n");
2947 qla82xx_idc_unlock(ha);
2948 qla2x00_perform_loop_resync(vha);
2949 qla82xx_idc_lock(ha);
2950
2951 qla82xx_clear_qsnt_ready(vha);
2952 return;
2953 }
2954
2955 qla82xx_idc_unlock(ha);
2956 msleep(1000);
2957 qla82xx_idc_lock(ha);
2958
2959 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2960 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2961 drv_active = drv_active << 0x01;
2962 }
2963 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2964 /* everyone acked so set the state to DEV_QUIESCENCE */
2965 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
2966 ql_log(ql_log_info, vha, 0xb026,
2967 "HW State: DEV_QUIESCENT.\n");
2968 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT);
2969 }
2970 }
2971
2972 /*
2973 * qla82xx_wait_for_state_change
2974 * Wait for device state to change from given current state
2975 *
2976 * Note:
2977 * IDC lock must not be held upon entry
2978 *
2979 * Return:
2980 * Changed device state.
2981 */
2982 uint32_t
qla82xx_wait_for_state_change(scsi_qla_host_t * vha,uint32_t curr_state)2983 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state)
2984 {
2985 struct qla_hw_data *ha = vha->hw;
2986 uint32_t dev_state;
2987
2988 do {
2989 msleep(1000);
2990 qla82xx_idc_lock(ha);
2991 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2992 qla82xx_idc_unlock(ha);
2993 } while (dev_state == curr_state);
2994
2995 return dev_state;
2996 }
2997
2998 void
qla8xxx_dev_failed_handler(scsi_qla_host_t * vha)2999 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha)
3000 {
3001 struct qla_hw_data *ha = vha->hw;
3002
3003 /* Disable the board */
3004 ql_log(ql_log_fatal, vha, 0x00b8,
3005 "Disabling the board.\n");
3006
3007 if (IS_QLA82XX(ha)) {
3008 qla82xx_clear_drv_active(ha);
3009 qla82xx_idc_unlock(ha);
3010 } else if (IS_QLA8044(ha)) {
3011 qla8044_clear_drv_active(ha);
3012 qla8044_idc_unlock(ha);
3013 }
3014
3015 /* Set DEV_FAILED flag to disable timer */
3016 vha->device_flags |= DFLG_DEV_FAILED;
3017 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3018 qla2x00_mark_all_devices_lost(vha, 0);
3019 vha->flags.online = 0;
3020 vha->flags.init_done = 0;
3021 }
3022
3023 /*
3024 * qla82xx_need_reset_handler
3025 * Code to start reset sequence
3026 *
3027 * Note:
3028 * IDC lock must be held upon entry
3029 *
3030 * Return:
3031 * Success : 0
3032 * Failed : 1
3033 */
3034 static void
qla82xx_need_reset_handler(scsi_qla_host_t * vha)3035 qla82xx_need_reset_handler(scsi_qla_host_t *vha)
3036 {
3037 uint32_t dev_state, drv_state, drv_active;
3038 uint32_t active_mask = 0;
3039 unsigned long reset_timeout;
3040 struct qla_hw_data *ha = vha->hw;
3041 struct req_que *req = ha->req_q_map[0];
3042
3043 if (vha->flags.online) {
3044 qla82xx_idc_unlock(ha);
3045 qla2x00_abort_isp_cleanup(vha);
3046 ha->isp_ops->get_flash_version(vha, req->ring);
3047 ha->isp_ops->nvram_config(vha);
3048 qla82xx_idc_lock(ha);
3049 }
3050
3051 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3052 if (!ha->flags.nic_core_reset_owner) {
3053 ql_dbg(ql_dbg_p3p, vha, 0xb028,
3054 "reset_acknowledged by 0x%x\n", ha->portnum);
3055 qla82xx_set_rst_ready(ha);
3056 } else {
3057 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
3058 drv_active &= active_mask;
3059 ql_dbg(ql_dbg_p3p, vha, 0xb029,
3060 "active_mask: 0x%08x\n", active_mask);
3061 }
3062
3063 /* wait for 10 seconds for reset ack from all functions */
3064 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
3065
3066 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3067 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3068 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3069
3070 ql_dbg(ql_dbg_p3p, vha, 0xb02a,
3071 "drv_state: 0x%08x, drv_active: 0x%08x, "
3072 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3073 drv_state, drv_active, dev_state, active_mask);
3074
3075 while (drv_state != drv_active &&
3076 dev_state != QLA8XXX_DEV_INITIALIZING) {
3077 if (time_after_eq(jiffies, reset_timeout)) {
3078 ql_log(ql_log_warn, vha, 0x00b5,
3079 "Reset timeout.\n");
3080 break;
3081 }
3082 qla82xx_idc_unlock(ha);
3083 msleep(1000);
3084 qla82xx_idc_lock(ha);
3085 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3086 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3087 if (ha->flags.nic_core_reset_owner)
3088 drv_active &= active_mask;
3089 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3090 }
3091
3092 ql_dbg(ql_dbg_p3p, vha, 0xb02b,
3093 "drv_state: 0x%08x, drv_active: 0x%08x, "
3094 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3095 drv_state, drv_active, dev_state, active_mask);
3096
3097 ql_log(ql_log_info, vha, 0x00b6,
3098 "Device state is 0x%x = %s.\n",
3099 dev_state,
3100 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3101
3102 /* Force to DEV_COLD unless someone else is starting a reset */
3103 if (dev_state != QLA8XXX_DEV_INITIALIZING &&
3104 dev_state != QLA8XXX_DEV_COLD) {
3105 ql_log(ql_log_info, vha, 0x00b7,
3106 "HW State: COLD/RE-INIT.\n");
3107 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
3108 qla82xx_set_rst_ready(ha);
3109 if (ql2xmdenable) {
3110 if (qla82xx_md_collect(vha))
3111 ql_log(ql_log_warn, vha, 0xb02c,
3112 "Minidump not collected.\n");
3113 } else
3114 ql_log(ql_log_warn, vha, 0xb04f,
3115 "Minidump disabled.\n");
3116 }
3117 }
3118
3119 int
qla82xx_check_md_needed(scsi_qla_host_t * vha)3120 qla82xx_check_md_needed(scsi_qla_host_t *vha)
3121 {
3122 struct qla_hw_data *ha = vha->hw;
3123 uint16_t fw_major_version, fw_minor_version, fw_subminor_version;
3124 int rval = QLA_SUCCESS;
3125
3126 fw_major_version = ha->fw_major_version;
3127 fw_minor_version = ha->fw_minor_version;
3128 fw_subminor_version = ha->fw_subminor_version;
3129
3130 rval = qla2x00_get_fw_version(vha);
3131 if (rval != QLA_SUCCESS)
3132 return rval;
3133
3134 if (ql2xmdenable) {
3135 if (!ha->fw_dumped) {
3136 if ((fw_major_version != ha->fw_major_version ||
3137 fw_minor_version != ha->fw_minor_version ||
3138 fw_subminor_version != ha->fw_subminor_version) ||
3139 (ha->prev_minidump_failed)) {
3140 ql_dbg(ql_dbg_p3p, vha, 0xb02d,
3141 "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n",
3142 fw_major_version, fw_minor_version,
3143 fw_subminor_version,
3144 ha->fw_major_version,
3145 ha->fw_minor_version,
3146 ha->fw_subminor_version,
3147 ha->prev_minidump_failed);
3148 /* Release MiniDump resources */
3149 qla82xx_md_free(vha);
3150 /* ALlocate MiniDump resources */
3151 qla82xx_md_prep(vha);
3152 }
3153 } else
3154 ql_log(ql_log_info, vha, 0xb02e,
3155 "Firmware dump available to retrieve\n");
3156 }
3157 return rval;
3158 }
3159
3160
3161 static int
qla82xx_check_fw_alive(scsi_qla_host_t * vha)3162 qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3163 {
3164 uint32_t fw_heartbeat_counter;
3165 int status = 0;
3166
3167 fw_heartbeat_counter = qla82xx_rd_32(vha->hw,
3168 QLA82XX_PEG_ALIVE_COUNTER);
3169 /* all 0xff, assume AER/EEH in progress, ignore */
3170 if (fw_heartbeat_counter == 0xffffffff) {
3171 ql_dbg(ql_dbg_timer, vha, 0x6003,
3172 "FW heartbeat counter is 0xffffffff, "
3173 "returning status=%d.\n", status);
3174 return status;
3175 }
3176 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3177 vha->seconds_since_last_heartbeat++;
3178 /* FW not alive after 2 seconds */
3179 if (vha->seconds_since_last_heartbeat == 2) {
3180 vha->seconds_since_last_heartbeat = 0;
3181 status = 1;
3182 }
3183 } else
3184 vha->seconds_since_last_heartbeat = 0;
3185 vha->fw_heartbeat_counter = fw_heartbeat_counter;
3186 if (status)
3187 ql_dbg(ql_dbg_timer, vha, 0x6004,
3188 "Returning status=%d.\n", status);
3189 return status;
3190 }
3191
3192 /*
3193 * qla82xx_device_state_handler
3194 * Main state handler
3195 *
3196 * Note:
3197 * IDC lock must be held upon entry
3198 *
3199 * Return:
3200 * Success : 0
3201 * Failed : 1
3202 */
3203 int
qla82xx_device_state_handler(scsi_qla_host_t * vha)3204 qla82xx_device_state_handler(scsi_qla_host_t *vha)
3205 {
3206 uint32_t dev_state;
3207 uint32_t old_dev_state;
3208 int rval = QLA_SUCCESS;
3209 unsigned long dev_init_timeout;
3210 struct qla_hw_data *ha = vha->hw;
3211 int loopcount = 0;
3212
3213 qla82xx_idc_lock(ha);
3214 if (!vha->flags.init_done) {
3215 qla82xx_set_drv_active(vha);
3216 qla82xx_set_idc_version(vha);
3217 }
3218
3219 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3220 old_dev_state = dev_state;
3221 ql_log(ql_log_info, vha, 0x009b,
3222 "Device state is 0x%x = %s.\n",
3223 dev_state,
3224 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3225
3226 /* wait for 30 seconds for device to go ready */
3227 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
3228
3229 while (1) {
3230
3231 if (time_after_eq(jiffies, dev_init_timeout)) {
3232 ql_log(ql_log_fatal, vha, 0x009c,
3233 "Device init failed.\n");
3234 rval = QLA_FUNCTION_FAILED;
3235 break;
3236 }
3237 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3238 if (old_dev_state != dev_state) {
3239 loopcount = 0;
3240 old_dev_state = dev_state;
3241 }
3242 if (loopcount < 5) {
3243 ql_log(ql_log_info, vha, 0x009d,
3244 "Device state is 0x%x = %s.\n",
3245 dev_state,
3246 dev_state < MAX_STATES ? qdev_state(dev_state) :
3247 "Unknown");
3248 }
3249
3250 switch (dev_state) {
3251 case QLA8XXX_DEV_READY:
3252 ha->flags.nic_core_reset_owner = 0;
3253 goto rel_lock;
3254 case QLA8XXX_DEV_COLD:
3255 rval = qla82xx_device_bootstrap(vha);
3256 break;
3257 case QLA8XXX_DEV_INITIALIZING:
3258 qla82xx_idc_unlock(ha);
3259 msleep(1000);
3260 qla82xx_idc_lock(ha);
3261 break;
3262 case QLA8XXX_DEV_NEED_RESET:
3263 if (!ql2xdontresethba)
3264 qla82xx_need_reset_handler(vha);
3265 else {
3266 qla82xx_idc_unlock(ha);
3267 msleep(1000);
3268 qla82xx_idc_lock(ha);
3269 }
3270 dev_init_timeout = jiffies +
3271 (ha->fcoe_dev_init_timeout * HZ);
3272 break;
3273 case QLA8XXX_DEV_NEED_QUIESCENT:
3274 qla82xx_need_qsnt_handler(vha);
3275 /* Reset timeout value after quiescence handler */
3276 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
3277 * HZ);
3278 break;
3279 case QLA8XXX_DEV_QUIESCENT:
3280 /* Owner will exit and other will wait for the state
3281 * to get changed
3282 */
3283 if (ha->flags.quiesce_owner)
3284 goto rel_lock;
3285
3286 qla82xx_idc_unlock(ha);
3287 msleep(1000);
3288 qla82xx_idc_lock(ha);
3289
3290 /* Reset timeout value after quiescence handler */
3291 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
3292 * HZ);
3293 break;
3294 case QLA8XXX_DEV_FAILED:
3295 qla8xxx_dev_failed_handler(vha);
3296 rval = QLA_FUNCTION_FAILED;
3297 goto exit;
3298 default:
3299 qla82xx_idc_unlock(ha);
3300 msleep(1000);
3301 qla82xx_idc_lock(ha);
3302 }
3303 loopcount++;
3304 }
3305 rel_lock:
3306 qla82xx_idc_unlock(ha);
3307 exit:
3308 return rval;
3309 }
3310
qla82xx_check_temp(scsi_qla_host_t * vha)3311 static int qla82xx_check_temp(scsi_qla_host_t *vha)
3312 {
3313 uint32_t temp, temp_state, temp_val;
3314 struct qla_hw_data *ha = vha->hw;
3315
3316 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE);
3317 temp_state = qla82xx_get_temp_state(temp);
3318 temp_val = qla82xx_get_temp_val(temp);
3319
3320 if (temp_state == QLA82XX_TEMP_PANIC) {
3321 ql_log(ql_log_warn, vha, 0x600e,
3322 "Device temperature %d degrees C exceeds "
3323 " maximum allowed. Hardware has been shut down.\n",
3324 temp_val);
3325 return 1;
3326 } else if (temp_state == QLA82XX_TEMP_WARN) {
3327 ql_log(ql_log_warn, vha, 0x600f,
3328 "Device temperature %d degrees C exceeds "
3329 "operating range. Immediate action needed.\n",
3330 temp_val);
3331 }
3332 return 0;
3333 }
3334
qla82xx_read_temperature(scsi_qla_host_t * vha)3335 int qla82xx_read_temperature(scsi_qla_host_t *vha)
3336 {
3337 uint32_t temp;
3338
3339 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE);
3340 return qla82xx_get_temp_val(temp);
3341 }
3342
qla82xx_clear_pending_mbx(scsi_qla_host_t * vha)3343 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha)
3344 {
3345 struct qla_hw_data *ha = vha->hw;
3346
3347 if (ha->flags.mbox_busy) {
3348 ha->flags.mbox_int = 1;
3349 ha->flags.mbox_busy = 0;
3350 ql_log(ql_log_warn, vha, 0x6010,
3351 "Doing premature completion of mbx command.\n");
3352 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags))
3353 complete(&ha->mbx_intr_comp);
3354 }
3355 }
3356
qla82xx_watchdog(scsi_qla_host_t * vha)3357 void qla82xx_watchdog(scsi_qla_host_t *vha)
3358 {
3359 uint32_t dev_state, halt_status;
3360 struct qla_hw_data *ha = vha->hw;
3361
3362 /* don't poll if reset is going on */
3363 if (!ha->flags.nic_core_reset_hdlr_active) {
3364 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3365 if (qla82xx_check_temp(vha)) {
3366 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3367 ha->flags.isp82xx_fw_hung = 1;
3368 qla82xx_clear_pending_mbx(vha);
3369 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
3370 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
3371 ql_log(ql_log_warn, vha, 0x6001,
3372 "Adapter reset needed.\n");
3373 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3374 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
3375 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
3376 ql_log(ql_log_warn, vha, 0x6002,
3377 "Quiescent needed.\n");
3378 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
3379 } else if (dev_state == QLA8XXX_DEV_FAILED &&
3380 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) &&
3381 vha->flags.online == 1) {
3382 ql_log(ql_log_warn, vha, 0xb055,
3383 "Adapter state is failed. Offlining.\n");
3384 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3385 ha->flags.isp82xx_fw_hung = 1;
3386 qla82xx_clear_pending_mbx(vha);
3387 } else {
3388 if (qla82xx_check_fw_alive(vha)) {
3389 ql_dbg(ql_dbg_timer, vha, 0x6011,
3390 "disabling pause transmit on port 0 & 1.\n");
3391 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
3392 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1);
3393 halt_status = qla82xx_rd_32(ha,
3394 QLA82XX_PEG_HALT_STATUS1);
3395 ql_log(ql_log_info, vha, 0x6005,
3396 "dumping hw/fw registers:.\n "
3397 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3398 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3399 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3400 " PEG_NET_4_PC: 0x%x.\n", halt_status,
3401 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2),
3402 qla82xx_rd_32(ha,
3403 QLA82XX_CRB_PEG_NET_0 + 0x3c),
3404 qla82xx_rd_32(ha,
3405 QLA82XX_CRB_PEG_NET_1 + 0x3c),
3406 qla82xx_rd_32(ha,
3407 QLA82XX_CRB_PEG_NET_2 + 0x3c),
3408 qla82xx_rd_32(ha,
3409 QLA82XX_CRB_PEG_NET_3 + 0x3c),
3410 qla82xx_rd_32(ha,
3411 QLA82XX_CRB_PEG_NET_4 + 0x3c));
3412 if (((halt_status & 0x1fffff00) >> 8) == 0x67)
3413 ql_log(ql_log_warn, vha, 0xb052,
3414 "Firmware aborted with "
3415 "error code 0x00006700. Device is "
3416 "being reset.\n");
3417 if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3418 set_bit(ISP_UNRECOVERABLE,
3419 &vha->dpc_flags);
3420 } else {
3421 ql_log(ql_log_info, vha, 0x6006,
3422 "Detect abort needed.\n");
3423 set_bit(ISP_ABORT_NEEDED,
3424 &vha->dpc_flags);
3425 }
3426 ha->flags.isp82xx_fw_hung = 1;
3427 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n");
3428 qla82xx_clear_pending_mbx(vha);
3429 }
3430 }
3431 }
3432 }
3433
qla82xx_load_risc(scsi_qla_host_t * vha,uint32_t * srisc_addr)3434 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3435 {
3436 int rval = -1;
3437 struct qla_hw_data *ha = vha->hw;
3438
3439 if (IS_QLA82XX(ha))
3440 rval = qla82xx_device_state_handler(vha);
3441 else if (IS_QLA8044(ha)) {
3442 qla8044_idc_lock(ha);
3443 /* Decide the reset ownership */
3444 qla83xx_reset_ownership(vha);
3445 qla8044_idc_unlock(ha);
3446 rval = qla8044_device_state_handler(vha);
3447 }
3448 return rval;
3449 }
3450
3451 void
qla82xx_set_reset_owner(scsi_qla_host_t * vha)3452 qla82xx_set_reset_owner(scsi_qla_host_t *vha)
3453 {
3454 struct qla_hw_data *ha = vha->hw;
3455 uint32_t dev_state = 0;
3456
3457 if (IS_QLA82XX(ha))
3458 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3459 else if (IS_QLA8044(ha))
3460 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
3461
3462 if (dev_state == QLA8XXX_DEV_READY) {
3463 ql_log(ql_log_info, vha, 0xb02f,
3464 "HW State: NEED RESET\n");
3465 if (IS_QLA82XX(ha)) {
3466 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3467 QLA8XXX_DEV_NEED_RESET);
3468 ha->flags.nic_core_reset_owner = 1;
3469 ql_dbg(ql_dbg_p3p, vha, 0xb030,
3470 "reset_owner is 0x%x\n", ha->portnum);
3471 } else if (IS_QLA8044(ha))
3472 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
3473 QLA8XXX_DEV_NEED_RESET);
3474 } else
3475 ql_log(ql_log_info, vha, 0xb031,
3476 "Device state is 0x%x = %s.\n",
3477 dev_state,
3478 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3479 }
3480
3481 /*
3482 * qla82xx_abort_isp
3483 * Resets ISP and aborts all outstanding commands.
3484 *
3485 * Input:
3486 * ha = adapter block pointer.
3487 *
3488 * Returns:
3489 * 0 = success
3490 */
3491 int
qla82xx_abort_isp(scsi_qla_host_t * vha)3492 qla82xx_abort_isp(scsi_qla_host_t *vha)
3493 {
3494 int rval = -1;
3495 struct qla_hw_data *ha = vha->hw;
3496
3497 if (vha->device_flags & DFLG_DEV_FAILED) {
3498 ql_log(ql_log_warn, vha, 0x8024,
3499 "Device in failed state, exiting.\n");
3500 return QLA_SUCCESS;
3501 }
3502 ha->flags.nic_core_reset_hdlr_active = 1;
3503
3504 qla82xx_idc_lock(ha);
3505 qla82xx_set_reset_owner(vha);
3506 qla82xx_idc_unlock(ha);
3507
3508 if (IS_QLA82XX(ha))
3509 rval = qla82xx_device_state_handler(vha);
3510 else if (IS_QLA8044(ha)) {
3511 qla8044_idc_lock(ha);
3512 /* Decide the reset ownership */
3513 qla83xx_reset_ownership(vha);
3514 qla8044_idc_unlock(ha);
3515 rval = qla8044_device_state_handler(vha);
3516 }
3517
3518 qla82xx_idc_lock(ha);
3519 qla82xx_clear_rst_ready(ha);
3520 qla82xx_idc_unlock(ha);
3521
3522 if (rval == QLA_SUCCESS) {
3523 ha->flags.isp82xx_fw_hung = 0;
3524 ha->flags.nic_core_reset_hdlr_active = 0;
3525 qla82xx_restart_isp(vha);
3526 }
3527
3528 if (rval) {
3529 vha->flags.online = 1;
3530 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3531 if (ha->isp_abort_cnt == 0) {
3532 ql_log(ql_log_warn, vha, 0x8027,
3533 "ISP error recover failed - board "
3534 "disabled.\n");
3535 /*
3536 * The next call disables the board
3537 * completely.
3538 */
3539 ha->isp_ops->reset_adapter(vha);
3540 vha->flags.online = 0;
3541 clear_bit(ISP_ABORT_RETRY,
3542 &vha->dpc_flags);
3543 rval = QLA_SUCCESS;
3544 } else { /* schedule another ISP abort */
3545 ha->isp_abort_cnt--;
3546 ql_log(ql_log_warn, vha, 0x8036,
3547 "ISP abort - retry remaining %d.\n",
3548 ha->isp_abort_cnt);
3549 rval = QLA_FUNCTION_FAILED;
3550 }
3551 } else {
3552 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
3553 ql_dbg(ql_dbg_taskm, vha, 0x8029,
3554 "ISP error recovery - retrying (%d) more times.\n",
3555 ha->isp_abort_cnt);
3556 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3557 rval = QLA_FUNCTION_FAILED;
3558 }
3559 }
3560 return rval;
3561 }
3562
3563 /*
3564 * qla82xx_fcoe_ctx_reset
3565 * Perform a quick reset and aborts all outstanding commands.
3566 * This will only perform an FCoE context reset and avoids a full blown
3567 * chip reset.
3568 *
3569 * Input:
3570 * ha = adapter block pointer.
3571 * is_reset_path = flag for identifying the reset path.
3572 *
3573 * Returns:
3574 * 0 = success
3575 */
qla82xx_fcoe_ctx_reset(scsi_qla_host_t * vha)3576 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3577 {
3578 int rval = QLA_FUNCTION_FAILED;
3579
3580 if (vha->flags.online) {
3581 /* Abort all outstanding commands, so as to be requeued later */
3582 qla2x00_abort_isp_cleanup(vha);
3583 }
3584
3585 /* Stop currently executing firmware.
3586 * This will destroy existing FCoE context at the F/W end.
3587 */
3588 qla2x00_try_to_stop_firmware(vha);
3589
3590 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3591 rval = qla82xx_restart_isp(vha);
3592
3593 return rval;
3594 }
3595
3596 /*
3597 * qla2x00_wait_for_fcoe_ctx_reset
3598 * Wait till the FCoE context is reset.
3599 *
3600 * Note:
3601 * Does context switching here.
3602 * Release SPIN_LOCK (if any) before calling this routine.
3603 *
3604 * Return:
3605 * Success (fcoe_ctx reset is done) : 0
3606 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1
3607 */
qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t * vha)3608 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3609 {
3610 int status = QLA_FUNCTION_FAILED;
3611 unsigned long wait_reset;
3612
3613 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3614 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3615 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3616 && time_before(jiffies, wait_reset)) {
3617
3618 set_current_state(TASK_UNINTERRUPTIBLE);
3619 schedule_timeout(HZ);
3620
3621 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3622 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3623 status = QLA_SUCCESS;
3624 break;
3625 }
3626 }
3627 ql_dbg(ql_dbg_p3p, vha, 0xb027,
3628 "%s: status=%d.\n", __func__, status);
3629
3630 return status;
3631 }
3632
3633 void
qla82xx_chip_reset_cleanup(scsi_qla_host_t * vha)3634 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
3635 {
3636 int i, fw_state = 0;
3637 unsigned long flags;
3638 struct qla_hw_data *ha = vha->hw;
3639
3640 /* Check if 82XX firmware is alive or not
3641 * We may have arrived here from NEED_RESET
3642 * detection only
3643 */
3644 if (!ha->flags.isp82xx_fw_hung) {
3645 for (i = 0; i < 2; i++) {
3646 msleep(1000);
3647 if (IS_QLA82XX(ha))
3648 fw_state = qla82xx_check_fw_alive(vha);
3649 else if (IS_QLA8044(ha))
3650 fw_state = qla8044_check_fw_alive(vha);
3651 if (fw_state) {
3652 ha->flags.isp82xx_fw_hung = 1;
3653 qla82xx_clear_pending_mbx(vha);
3654 break;
3655 }
3656 }
3657 }
3658 ql_dbg(ql_dbg_init, vha, 0x00b0,
3659 "Entered %s fw_hung=%d.\n",
3660 __func__, ha->flags.isp82xx_fw_hung);
3661
3662 /* Abort all commands gracefully if fw NOT hung */
3663 if (!ha->flags.isp82xx_fw_hung) {
3664 int cnt, que;
3665 srb_t *sp;
3666 struct req_que *req;
3667
3668 spin_lock_irqsave(&ha->hardware_lock, flags);
3669 for (que = 0; que < ha->max_req_queues; que++) {
3670 req = ha->req_q_map[que];
3671 if (!req)
3672 continue;
3673 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
3674 sp = req->outstanding_cmds[cnt];
3675 if (sp) {
3676 if ((!sp->u.scmd.ctx ||
3677 (sp->flags &
3678 SRB_FCP_CMND_DMA_VALID)) &&
3679 !ha->flags.isp82xx_fw_hung) {
3680 spin_unlock_irqrestore(
3681 &ha->hardware_lock, flags);
3682 if (ha->isp_ops->abort_command(sp)) {
3683 ql_log(ql_log_info, vha,
3684 0x00b1,
3685 "mbx abort failed.\n");
3686 } else {
3687 ql_log(ql_log_info, vha,
3688 0x00b2,
3689 "mbx abort success.\n");
3690 }
3691 spin_lock_irqsave(&ha->hardware_lock, flags);
3692 }
3693 }
3694 }
3695 }
3696 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3697
3698 /* Wait for pending cmds (physical and virtual) to complete */
3699 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
3700 WAIT_HOST) == QLA_SUCCESS) {
3701 ql_dbg(ql_dbg_init, vha, 0x00b3,
3702 "Done wait for "
3703 "pending commands.\n");
3704 }
3705 }
3706 }
3707
3708 /* Minidump related functions */
3709 static int
qla82xx_minidump_process_control(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)3710 qla82xx_minidump_process_control(scsi_qla_host_t *vha,
3711 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3712 {
3713 struct qla_hw_data *ha = vha->hw;
3714 struct qla82xx_md_entry_crb *crb_entry;
3715 uint32_t read_value, opcode, poll_time;
3716 uint32_t addr, index, crb_addr;
3717 unsigned long wtime;
3718 struct qla82xx_md_template_hdr *tmplt_hdr;
3719 uint32_t rval = QLA_SUCCESS;
3720 int i;
3721
3722 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
3723 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr;
3724 crb_addr = crb_entry->addr;
3725
3726 for (i = 0; i < crb_entry->op_count; i++) {
3727 opcode = crb_entry->crb_ctrl.opcode;
3728 if (opcode & QLA82XX_DBG_OPCODE_WR) {
3729 qla82xx_md_rw_32(ha, crb_addr,
3730 crb_entry->value_1, 1);
3731 opcode &= ~QLA82XX_DBG_OPCODE_WR;
3732 }
3733
3734 if (opcode & QLA82XX_DBG_OPCODE_RW) {
3735 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3736 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3737 opcode &= ~QLA82XX_DBG_OPCODE_RW;
3738 }
3739
3740 if (opcode & QLA82XX_DBG_OPCODE_AND) {
3741 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3742 read_value &= crb_entry->value_2;
3743 opcode &= ~QLA82XX_DBG_OPCODE_AND;
3744 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3745 read_value |= crb_entry->value_3;
3746 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3747 }
3748 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3749 }
3750
3751 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3752 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3753 read_value |= crb_entry->value_3;
3754 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3755 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3756 }
3757
3758 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
3759 poll_time = crb_entry->crb_strd.poll_timeout;
3760 wtime = jiffies + poll_time;
3761 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3762
3763 do {
3764 if ((read_value & crb_entry->value_2)
3765 == crb_entry->value_1)
3766 break;
3767 else if (time_after_eq(jiffies, wtime)) {
3768 /* capturing dump failed */
3769 rval = QLA_FUNCTION_FAILED;
3770 break;
3771 } else
3772 read_value = qla82xx_md_rw_32(ha,
3773 crb_addr, 0, 0);
3774 } while (1);
3775 opcode &= ~QLA82XX_DBG_OPCODE_POLL;
3776 }
3777
3778 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
3779 if (crb_entry->crb_strd.state_index_a) {
3780 index = crb_entry->crb_strd.state_index_a;
3781 addr = tmplt_hdr->saved_state_array[index];
3782 } else
3783 addr = crb_addr;
3784
3785 read_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3786 index = crb_entry->crb_ctrl.state_index_v;
3787 tmplt_hdr->saved_state_array[index] = read_value;
3788 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
3789 }
3790
3791 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
3792 if (crb_entry->crb_strd.state_index_a) {
3793 index = crb_entry->crb_strd.state_index_a;
3794 addr = tmplt_hdr->saved_state_array[index];
3795 } else
3796 addr = crb_addr;
3797
3798 if (crb_entry->crb_ctrl.state_index_v) {
3799 index = crb_entry->crb_ctrl.state_index_v;
3800 read_value =
3801 tmplt_hdr->saved_state_array[index];
3802 } else
3803 read_value = crb_entry->value_1;
3804
3805 qla82xx_md_rw_32(ha, addr, read_value, 1);
3806 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
3807 }
3808
3809 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
3810 index = crb_entry->crb_ctrl.state_index_v;
3811 read_value = tmplt_hdr->saved_state_array[index];
3812 read_value <<= crb_entry->crb_ctrl.shl;
3813 read_value >>= crb_entry->crb_ctrl.shr;
3814 if (crb_entry->value_2)
3815 read_value &= crb_entry->value_2;
3816 read_value |= crb_entry->value_3;
3817 read_value += crb_entry->value_1;
3818 tmplt_hdr->saved_state_array[index] = read_value;
3819 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
3820 }
3821 crb_addr += crb_entry->crb_strd.addr_stride;
3822 }
3823 return rval;
3824 }
3825
3826 static void
qla82xx_minidump_process_rdocm(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)3827 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3828 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3829 {
3830 struct qla_hw_data *ha = vha->hw;
3831 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3832 struct qla82xx_md_entry_rdocm *ocm_hdr;
3833 uint32_t *data_ptr = *d_ptr;
3834
3835 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr;
3836 r_addr = ocm_hdr->read_addr;
3837 r_stride = ocm_hdr->read_addr_stride;
3838 loop_cnt = ocm_hdr->op_count;
3839
3840 for (i = 0; i < loop_cnt; i++) {
3841 r_value = RD_REG_DWORD(r_addr + ha->nx_pcibase);
3842 *data_ptr++ = cpu_to_le32(r_value);
3843 r_addr += r_stride;
3844 }
3845 *d_ptr = data_ptr;
3846 }
3847
3848 static void
qla82xx_minidump_process_rdmux(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)3849 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha,
3850 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3851 {
3852 struct qla_hw_data *ha = vha->hw;
3853 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3854 struct qla82xx_md_entry_mux *mux_hdr;
3855 uint32_t *data_ptr = *d_ptr;
3856
3857 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr;
3858 r_addr = mux_hdr->read_addr;
3859 s_addr = mux_hdr->select_addr;
3860 s_stride = mux_hdr->select_value_stride;
3861 s_value = mux_hdr->select_value;
3862 loop_cnt = mux_hdr->op_count;
3863
3864 for (i = 0; i < loop_cnt; i++) {
3865 qla82xx_md_rw_32(ha, s_addr, s_value, 1);
3866 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3867 *data_ptr++ = cpu_to_le32(s_value);
3868 *data_ptr++ = cpu_to_le32(r_value);
3869 s_value += s_stride;
3870 }
3871 *d_ptr = data_ptr;
3872 }
3873
3874 static void
qla82xx_minidump_process_rdcrb(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)3875 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha,
3876 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3877 {
3878 struct qla_hw_data *ha = vha->hw;
3879 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3880 struct qla82xx_md_entry_crb *crb_hdr;
3881 uint32_t *data_ptr = *d_ptr;
3882
3883 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr;
3884 r_addr = crb_hdr->addr;
3885 r_stride = crb_hdr->crb_strd.addr_stride;
3886 loop_cnt = crb_hdr->op_count;
3887
3888 for (i = 0; i < loop_cnt; i++) {
3889 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3890 *data_ptr++ = cpu_to_le32(r_addr);
3891 *data_ptr++ = cpu_to_le32(r_value);
3892 r_addr += r_stride;
3893 }
3894 *d_ptr = data_ptr;
3895 }
3896
3897 static int
qla82xx_minidump_process_l2tag(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)3898 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha,
3899 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3900 {
3901 struct qla_hw_data *ha = vha->hw;
3902 uint32_t addr, r_addr, c_addr, t_r_addr;
3903 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3904 unsigned long p_wait, w_time, p_mask;
3905 uint32_t c_value_w, c_value_r;
3906 struct qla82xx_md_entry_cache *cache_hdr;
3907 int rval = QLA_FUNCTION_FAILED;
3908 uint32_t *data_ptr = *d_ptr;
3909
3910 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3911 loop_count = cache_hdr->op_count;
3912 r_addr = cache_hdr->read_addr;
3913 c_addr = cache_hdr->control_addr;
3914 c_value_w = cache_hdr->cache_ctrl.write_value;
3915
3916 t_r_addr = cache_hdr->tag_reg_addr;
3917 t_value = cache_hdr->addr_ctrl.init_tag_value;
3918 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3919 p_wait = cache_hdr->cache_ctrl.poll_wait;
3920 p_mask = cache_hdr->cache_ctrl.poll_mask;
3921
3922 for (i = 0; i < loop_count; i++) {
3923 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3924 if (c_value_w)
3925 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3926
3927 if (p_mask) {
3928 w_time = jiffies + p_wait;
3929 do {
3930 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0);
3931 if ((c_value_r & p_mask) == 0)
3932 break;
3933 else if (time_after_eq(jiffies, w_time)) {
3934 /* capturing dump failed */
3935 ql_dbg(ql_dbg_p3p, vha, 0xb032,
3936 "c_value_r: 0x%x, poll_mask: 0x%lx, "
3937 "w_time: 0x%lx\n",
3938 c_value_r, p_mask, w_time);
3939 return rval;
3940 }
3941 } while (1);
3942 }
3943
3944 addr = r_addr;
3945 for (k = 0; k < r_cnt; k++) {
3946 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3947 *data_ptr++ = cpu_to_le32(r_value);
3948 addr += cache_hdr->read_ctrl.read_addr_stride;
3949 }
3950 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3951 }
3952 *d_ptr = data_ptr;
3953 return QLA_SUCCESS;
3954 }
3955
3956 static void
qla82xx_minidump_process_l1cache(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)3957 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha,
3958 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3959 {
3960 struct qla_hw_data *ha = vha->hw;
3961 uint32_t addr, r_addr, c_addr, t_r_addr;
3962 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3963 uint32_t c_value_w;
3964 struct qla82xx_md_entry_cache *cache_hdr;
3965 uint32_t *data_ptr = *d_ptr;
3966
3967 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3968 loop_count = cache_hdr->op_count;
3969 r_addr = cache_hdr->read_addr;
3970 c_addr = cache_hdr->control_addr;
3971 c_value_w = cache_hdr->cache_ctrl.write_value;
3972
3973 t_r_addr = cache_hdr->tag_reg_addr;
3974 t_value = cache_hdr->addr_ctrl.init_tag_value;
3975 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3976
3977 for (i = 0; i < loop_count; i++) {
3978 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3979 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3980 addr = r_addr;
3981 for (k = 0; k < r_cnt; k++) {
3982 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3983 *data_ptr++ = cpu_to_le32(r_value);
3984 addr += cache_hdr->read_ctrl.read_addr_stride;
3985 }
3986 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3987 }
3988 *d_ptr = data_ptr;
3989 }
3990
3991 static void
qla82xx_minidump_process_queue(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)3992 qla82xx_minidump_process_queue(scsi_qla_host_t *vha,
3993 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3994 {
3995 struct qla_hw_data *ha = vha->hw;
3996 uint32_t s_addr, r_addr;
3997 uint32_t r_stride, r_value, r_cnt, qid = 0;
3998 uint32_t i, k, loop_cnt;
3999 struct qla82xx_md_entry_queue *q_hdr;
4000 uint32_t *data_ptr = *d_ptr;
4001
4002 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr;
4003 s_addr = q_hdr->select_addr;
4004 r_cnt = q_hdr->rd_strd.read_addr_cnt;
4005 r_stride = q_hdr->rd_strd.read_addr_stride;
4006 loop_cnt = q_hdr->op_count;
4007
4008 for (i = 0; i < loop_cnt; i++) {
4009 qla82xx_md_rw_32(ha, s_addr, qid, 1);
4010 r_addr = q_hdr->read_addr;
4011 for (k = 0; k < r_cnt; k++) {
4012 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
4013 *data_ptr++ = cpu_to_le32(r_value);
4014 r_addr += r_stride;
4015 }
4016 qid += q_hdr->q_strd.queue_id_stride;
4017 }
4018 *d_ptr = data_ptr;
4019 }
4020
4021 static void
qla82xx_minidump_process_rdrom(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)4022 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha,
4023 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4024 {
4025 struct qla_hw_data *ha = vha->hw;
4026 uint32_t r_addr, r_value;
4027 uint32_t i, loop_cnt;
4028 struct qla82xx_md_entry_rdrom *rom_hdr;
4029 uint32_t *data_ptr = *d_ptr;
4030
4031 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr;
4032 r_addr = rom_hdr->read_addr;
4033 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
4034
4035 for (i = 0; i < loop_cnt; i++) {
4036 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
4037 (r_addr & 0xFFFF0000), 1);
4038 r_value = qla82xx_md_rw_32(ha,
4039 MD_DIRECT_ROM_READ_BASE +
4040 (r_addr & 0x0000FFFF), 0, 0);
4041 *data_ptr++ = cpu_to_le32(r_value);
4042 r_addr += sizeof(uint32_t);
4043 }
4044 *d_ptr = data_ptr;
4045 }
4046
4047 static int
qla82xx_minidump_process_rdmem(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)4048 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha,
4049 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4050 {
4051 struct qla_hw_data *ha = vha->hw;
4052 uint32_t r_addr, r_value, r_data;
4053 uint32_t i, j, loop_cnt;
4054 struct qla82xx_md_entry_rdmem *m_hdr;
4055 unsigned long flags;
4056 int rval = QLA_FUNCTION_FAILED;
4057 uint32_t *data_ptr = *d_ptr;
4058
4059 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr;
4060 r_addr = m_hdr->read_addr;
4061 loop_cnt = m_hdr->read_data_size/16;
4062
4063 if (r_addr & 0xf) {
4064 ql_log(ql_log_warn, vha, 0xb033,
4065 "Read addr 0x%x not 16 bytes aligned\n", r_addr);
4066 return rval;
4067 }
4068
4069 if (m_hdr->read_data_size % 16) {
4070 ql_log(ql_log_warn, vha, 0xb034,
4071 "Read data[0x%x] not multiple of 16 bytes\n",
4072 m_hdr->read_data_size);
4073 return rval;
4074 }
4075
4076 ql_dbg(ql_dbg_p3p, vha, 0xb035,
4077 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
4078 __func__, r_addr, m_hdr->read_data_size, loop_cnt);
4079
4080 write_lock_irqsave(&ha->hw_lock, flags);
4081 for (i = 0; i < loop_cnt; i++) {
4082 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
4083 r_value = 0;
4084 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
4085 r_value = MIU_TA_CTL_ENABLE;
4086 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4087 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
4088 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4089
4090 for (j = 0; j < MAX_CTL_CHECK; j++) {
4091 r_value = qla82xx_md_rw_32(ha,
4092 MD_MIU_TEST_AGT_CTRL, 0, 0);
4093 if ((r_value & MIU_TA_CTL_BUSY) == 0)
4094 break;
4095 }
4096
4097 if (j >= MAX_CTL_CHECK) {
4098 printk_ratelimited(KERN_ERR
4099 "failed to read through agent\n");
4100 write_unlock_irqrestore(&ha->hw_lock, flags);
4101 return rval;
4102 }
4103
4104 for (j = 0; j < 4; j++) {
4105 r_data = qla82xx_md_rw_32(ha,
4106 MD_MIU_TEST_AGT_RDDATA[j], 0, 0);
4107 *data_ptr++ = cpu_to_le32(r_data);
4108 }
4109 r_addr += 16;
4110 }
4111 write_unlock_irqrestore(&ha->hw_lock, flags);
4112 *d_ptr = data_ptr;
4113 return QLA_SUCCESS;
4114 }
4115
4116 int
qla82xx_validate_template_chksum(scsi_qla_host_t * vha)4117 qla82xx_validate_template_chksum(scsi_qla_host_t *vha)
4118 {
4119 struct qla_hw_data *ha = vha->hw;
4120 uint64_t chksum = 0;
4121 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr;
4122 int count = ha->md_template_size/sizeof(uint32_t);
4123
4124 while (count-- > 0)
4125 chksum += *d_ptr++;
4126 while (chksum >> 32)
4127 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32);
4128 return ~chksum;
4129 }
4130
4131 static void
qla82xx_mark_entry_skipped(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,int index)4132 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha,
4133 qla82xx_md_entry_hdr_t *entry_hdr, int index)
4134 {
4135 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
4136 ql_dbg(ql_dbg_p3p, vha, 0xb036,
4137 "Skipping entry[%d]: "
4138 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4139 index, entry_hdr->entry_type,
4140 entry_hdr->d_ctrl.entry_capture_mask);
4141 }
4142
4143 int
qla82xx_md_collect(scsi_qla_host_t * vha)4144 qla82xx_md_collect(scsi_qla_host_t *vha)
4145 {
4146 struct qla_hw_data *ha = vha->hw;
4147 int no_entry_hdr = 0;
4148 qla82xx_md_entry_hdr_t *entry_hdr;
4149 struct qla82xx_md_template_hdr *tmplt_hdr;
4150 uint32_t *data_ptr;
4151 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
4152 int i = 0, rval = QLA_FUNCTION_FAILED;
4153
4154 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4155 data_ptr = (uint32_t *)ha->md_dump;
4156
4157 if (ha->fw_dumped) {
4158 ql_log(ql_log_warn, vha, 0xb037,
4159 "Firmware has been previously dumped (%p) "
4160 "-- ignoring request.\n", ha->fw_dump);
4161 goto md_failed;
4162 }
4163
4164 ha->fw_dumped = 0;
4165
4166 if (!ha->md_tmplt_hdr || !ha->md_dump) {
4167 ql_log(ql_log_warn, vha, 0xb038,
4168 "Memory not allocated for minidump capture\n");
4169 goto md_failed;
4170 }
4171
4172 if (ha->flags.isp82xx_no_md_cap) {
4173 ql_log(ql_log_warn, vha, 0xb054,
4174 "Forced reset from application, "
4175 "ignore minidump capture\n");
4176 ha->flags.isp82xx_no_md_cap = 0;
4177 goto md_failed;
4178 }
4179
4180 if (qla82xx_validate_template_chksum(vha)) {
4181 ql_log(ql_log_info, vha, 0xb039,
4182 "Template checksum validation error\n");
4183 goto md_failed;
4184 }
4185
4186 no_entry_hdr = tmplt_hdr->num_of_entries;
4187 ql_dbg(ql_dbg_p3p, vha, 0xb03a,
4188 "No of entry headers in Template: 0x%x\n", no_entry_hdr);
4189
4190 ql_dbg(ql_dbg_p3p, vha, 0xb03b,
4191 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
4192
4193 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
4194
4195 /* Validate whether required debug level is set */
4196 if ((f_capture_mask & 0x3) != 0x3) {
4197 ql_log(ql_log_warn, vha, 0xb03c,
4198 "Minimum required capture mask[0x%x] level not set\n",
4199 f_capture_mask);
4200 goto md_failed;
4201 }
4202 tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
4203
4204 tmplt_hdr->driver_info[0] = vha->host_no;
4205 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) |
4206 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) |
4207 QLA_DRIVER_BETA_VER;
4208
4209 total_data_size = ha->md_dump_size;
4210
4211 ql_dbg(ql_dbg_p3p, vha, 0xb03d,
4212 "Total minidump data_size 0x%x to be captured\n", total_data_size);
4213
4214 /* Check whether template obtained is valid */
4215 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) {
4216 ql_log(ql_log_warn, vha, 0xb04e,
4217 "Bad template header entry type: 0x%x obtained\n",
4218 tmplt_hdr->entry_type);
4219 goto md_failed;
4220 }
4221
4222 entry_hdr = (qla82xx_md_entry_hdr_t *) \
4223 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
4224
4225 /* Walk through the entry headers */
4226 for (i = 0; i < no_entry_hdr; i++) {
4227
4228 if (data_collected > total_data_size) {
4229 ql_log(ql_log_warn, vha, 0xb03e,
4230 "More MiniDump data collected: [0x%x]\n",
4231 data_collected);
4232 goto md_failed;
4233 }
4234
4235 if (!(entry_hdr->d_ctrl.entry_capture_mask &
4236 ql2xmdcapmask)) {
4237 entry_hdr->d_ctrl.driver_flags |=
4238 QLA82XX_DBG_SKIPPED_FLAG;
4239 ql_dbg(ql_dbg_p3p, vha, 0xb03f,
4240 "Skipping entry[%d]: "
4241 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4242 i, entry_hdr->entry_type,
4243 entry_hdr->d_ctrl.entry_capture_mask);
4244 goto skip_nxt_entry;
4245 }
4246
4247 ql_dbg(ql_dbg_p3p, vha, 0xb040,
4248 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
4249 "entry_type: 0x%x, captrue_mask: 0x%x\n",
4250 __func__, i, data_ptr, entry_hdr,
4251 entry_hdr->entry_type,
4252 entry_hdr->d_ctrl.entry_capture_mask);
4253
4254 ql_dbg(ql_dbg_p3p, vha, 0xb041,
4255 "Data collected: [0x%x], Dump size left:[0x%x]\n",
4256 data_collected, (ha->md_dump_size - data_collected));
4257
4258 /* Decode the entry type and take
4259 * required action to capture debug data */
4260 switch (entry_hdr->entry_type) {
4261 case QLA82XX_RDEND:
4262 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4263 break;
4264 case QLA82XX_CNTRL:
4265 rval = qla82xx_minidump_process_control(vha,
4266 entry_hdr, &data_ptr);
4267 if (rval != QLA_SUCCESS) {
4268 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4269 goto md_failed;
4270 }
4271 break;
4272 case QLA82XX_RDCRB:
4273 qla82xx_minidump_process_rdcrb(vha,
4274 entry_hdr, &data_ptr);
4275 break;
4276 case QLA82XX_RDMEM:
4277 rval = qla82xx_minidump_process_rdmem(vha,
4278 entry_hdr, &data_ptr);
4279 if (rval != QLA_SUCCESS) {
4280 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4281 goto md_failed;
4282 }
4283 break;
4284 case QLA82XX_BOARD:
4285 case QLA82XX_RDROM:
4286 qla82xx_minidump_process_rdrom(vha,
4287 entry_hdr, &data_ptr);
4288 break;
4289 case QLA82XX_L2DTG:
4290 case QLA82XX_L2ITG:
4291 case QLA82XX_L2DAT:
4292 case QLA82XX_L2INS:
4293 rval = qla82xx_minidump_process_l2tag(vha,
4294 entry_hdr, &data_ptr);
4295 if (rval != QLA_SUCCESS) {
4296 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4297 goto md_failed;
4298 }
4299 break;
4300 case QLA82XX_L1DAT:
4301 case QLA82XX_L1INS:
4302 qla82xx_minidump_process_l1cache(vha,
4303 entry_hdr, &data_ptr);
4304 break;
4305 case QLA82XX_RDOCM:
4306 qla82xx_minidump_process_rdocm(vha,
4307 entry_hdr, &data_ptr);
4308 break;
4309 case QLA82XX_RDMUX:
4310 qla82xx_minidump_process_rdmux(vha,
4311 entry_hdr, &data_ptr);
4312 break;
4313 case QLA82XX_QUEUE:
4314 qla82xx_minidump_process_queue(vha,
4315 entry_hdr, &data_ptr);
4316 break;
4317 case QLA82XX_RDNOP:
4318 default:
4319 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4320 break;
4321 }
4322
4323 ql_dbg(ql_dbg_p3p, vha, 0xb042,
4324 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr);
4325
4326 data_collected = (uint8_t *)data_ptr -
4327 (uint8_t *)ha->md_dump;
4328 skip_nxt_entry:
4329 entry_hdr = (qla82xx_md_entry_hdr_t *) \
4330 (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
4331 }
4332
4333 if (data_collected != total_data_size) {
4334 ql_dbg(ql_dbg_p3p, vha, 0xb043,
4335 "MiniDump data mismatch: Data collected: [0x%x],"
4336 "total_data_size:[0x%x]\n",
4337 data_collected, total_data_size);
4338 goto md_failed;
4339 }
4340
4341 ql_log(ql_log_info, vha, 0xb044,
4342 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
4343 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
4344 ha->fw_dumped = 1;
4345 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
4346
4347 md_failed:
4348 return rval;
4349 }
4350
4351 int
qla82xx_md_alloc(scsi_qla_host_t * vha)4352 qla82xx_md_alloc(scsi_qla_host_t *vha)
4353 {
4354 struct qla_hw_data *ha = vha->hw;
4355 int i, k;
4356 struct qla82xx_md_template_hdr *tmplt_hdr;
4357
4358 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4359
4360 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) {
4361 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF;
4362 ql_log(ql_log_info, vha, 0xb045,
4363 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
4364 ql2xmdcapmask);
4365 }
4366
4367 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) {
4368 if (i & ql2xmdcapmask)
4369 ha->md_dump_size += tmplt_hdr->capture_size_array[k];
4370 }
4371
4372 if (ha->md_dump) {
4373 ql_log(ql_log_warn, vha, 0xb046,
4374 "Firmware dump previously allocated.\n");
4375 return 1;
4376 }
4377
4378 ha->md_dump = vmalloc(ha->md_dump_size);
4379 if (ha->md_dump == NULL) {
4380 ql_log(ql_log_warn, vha, 0xb047,
4381 "Unable to allocate memory for Minidump size "
4382 "(0x%x).\n", ha->md_dump_size);
4383 return 1;
4384 }
4385 return 0;
4386 }
4387
4388 void
qla82xx_md_free(scsi_qla_host_t * vha)4389 qla82xx_md_free(scsi_qla_host_t *vha)
4390 {
4391 struct qla_hw_data *ha = vha->hw;
4392
4393 /* Release the template header allocated */
4394 if (ha->md_tmplt_hdr) {
4395 ql_log(ql_log_info, vha, 0xb048,
4396 "Free MiniDump template: %p, size (%d KB)\n",
4397 ha->md_tmplt_hdr, ha->md_template_size / 1024);
4398 dma_free_coherent(&ha->pdev->dev, ha->md_template_size,
4399 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4400 ha->md_tmplt_hdr = NULL;
4401 }
4402
4403 /* Release the template data buffer allocated */
4404 if (ha->md_dump) {
4405 ql_log(ql_log_info, vha, 0xb049,
4406 "Free MiniDump memory: %p, size (%d KB)\n",
4407 ha->md_dump, ha->md_dump_size / 1024);
4408 vfree(ha->md_dump);
4409 ha->md_dump_size = 0;
4410 ha->md_dump = NULL;
4411 }
4412 }
4413
4414 void
qla82xx_md_prep(scsi_qla_host_t * vha)4415 qla82xx_md_prep(scsi_qla_host_t *vha)
4416 {
4417 struct qla_hw_data *ha = vha->hw;
4418 int rval;
4419
4420 /* Get Minidump template size */
4421 rval = qla82xx_md_get_template_size(vha);
4422 if (rval == QLA_SUCCESS) {
4423 ql_log(ql_log_info, vha, 0xb04a,
4424 "MiniDump Template size obtained (%d KB)\n",
4425 ha->md_template_size / 1024);
4426
4427 /* Get Minidump template */
4428 if (IS_QLA8044(ha))
4429 rval = qla8044_md_get_template(vha);
4430 else
4431 rval = qla82xx_md_get_template(vha);
4432
4433 if (rval == QLA_SUCCESS) {
4434 ql_dbg(ql_dbg_p3p, vha, 0xb04b,
4435 "MiniDump Template obtained\n");
4436
4437 /* Allocate memory for minidump */
4438 rval = qla82xx_md_alloc(vha);
4439 if (rval == QLA_SUCCESS)
4440 ql_log(ql_log_info, vha, 0xb04c,
4441 "MiniDump memory allocated (%d KB)\n",
4442 ha->md_dump_size / 1024);
4443 else {
4444 ql_log(ql_log_info, vha, 0xb04d,
4445 "Free MiniDump template: %p, size: (%d KB)\n",
4446 ha->md_tmplt_hdr,
4447 ha->md_template_size / 1024);
4448 dma_free_coherent(&ha->pdev->dev,
4449 ha->md_template_size,
4450 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4451 ha->md_tmplt_hdr = NULL;
4452 }
4453
4454 }
4455 }
4456 }
4457
4458 int
qla82xx_beacon_on(struct scsi_qla_host * vha)4459 qla82xx_beacon_on(struct scsi_qla_host *vha)
4460 {
4461
4462 int rval;
4463 struct qla_hw_data *ha = vha->hw;
4464 qla82xx_idc_lock(ha);
4465 rval = qla82xx_mbx_beacon_ctl(vha, 1);
4466
4467 if (rval) {
4468 ql_log(ql_log_warn, vha, 0xb050,
4469 "mbx set led config failed in %s\n", __func__);
4470 goto exit;
4471 }
4472 ha->beacon_blink_led = 1;
4473 exit:
4474 qla82xx_idc_unlock(ha);
4475 return rval;
4476 }
4477
4478 int
qla82xx_beacon_off(struct scsi_qla_host * vha)4479 qla82xx_beacon_off(struct scsi_qla_host *vha)
4480 {
4481
4482 int rval;
4483 struct qla_hw_data *ha = vha->hw;
4484 qla82xx_idc_lock(ha);
4485 rval = qla82xx_mbx_beacon_ctl(vha, 0);
4486
4487 if (rval) {
4488 ql_log(ql_log_warn, vha, 0xb051,
4489 "mbx set led config failed in %s\n", __func__);
4490 goto exit;
4491 }
4492 ha->beacon_blink_led = 0;
4493 exit:
4494 qla82xx_idc_unlock(ha);
4495 return rval;
4496 }
4497
4498 void
qla82xx_fw_dump(scsi_qla_host_t * vha,int hardware_locked)4499 qla82xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
4500 {
4501 struct qla_hw_data *ha = vha->hw;
4502
4503 if (!ha->allow_cna_fw_dump)
4504 return;
4505
4506 scsi_block_requests(vha->host);
4507 ha->flags.isp82xx_no_md_cap = 1;
4508 qla82xx_idc_lock(ha);
4509 qla82xx_set_reset_owner(vha);
4510 qla82xx_idc_unlock(ha);
4511 qla2x00_wait_for_chip_reset(vha);
4512 scsi_unblock_requests(vha->host);
4513 }
4514