1 /* 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2015 Intel Corporation. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * BSD LICENSE 20 * 21 * Copyright(c) 2015 Intel Corporation. 22 * 23 * Redistribution and use in source and binary forms, with or without 24 * modification, are permitted provided that the following conditions 25 * are met: 26 * 27 * - Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * - Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in 31 * the documentation and/or other materials provided with the 32 * distribution. 33 * - Neither the name of Intel Corporation nor the names of its 34 * contributors may be used to endorse or promote products derived 35 * from this software without specific prior written permission. 36 * 37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 * 49 */ 50 /* QSFP support common definitions, for hfi driver */ 51 52 #define QSFP_DEV 0xA0 53 #define QSFP_PWR_LAG_MSEC 2000 54 #define QSFP_MODPRS_LAG_MSEC 20 55 /* 128 byte pages, per SFF 8636 rev 2.4 */ 56 #define QSFP_MAX_NUM_PAGES 5 57 58 /* 59 * Below are masks for QSFP pins. Pins are the same for HFI0 and HFI1. 60 * _N means asserted low 61 */ 62 #define QSFP_HFI0_I2CCLK (1 << 0) 63 #define QSFP_HFI0_I2CDAT (1 << 1) 64 #define QSFP_HFI0_RESET_N (1 << 2) 65 #define QSFP_HFI0_INT_N (1 << 3) 66 #define QSFP_HFI0_MODPRST_N (1 << 4) 67 68 /* QSFP is paged at 256 bytes */ 69 #define QSFP_PAGESIZE 256 70 71 /* Defined fields that Intel requires of qualified cables */ 72 /* Byte 0 is Identifier, not checked */ 73 /* Byte 1 is reserved "status MSB" */ 74 /* Byte 2 is "status LSB" We only care that D2 "Flat Mem" is set. */ 75 /* 76 * Rest of first 128 not used, although 127 is reserved for page select 77 * if module is not "Flat memory". 78 */ 79 #define QSFP_PAGE_SELECT_BYTE_OFFS 127 80 /* Byte 128 is Identifier: must be 0x0c for QSFP, or 0x0d for QSFP+ */ 81 #define QSFP_MOD_ID_OFFS 128 82 /* 83 * Byte 129 is "Extended Identifier". We only care about D7,D6: Power class 84 * 0:1.5W, 1:2.0W, 2:2.5W, 3:3.5W 85 */ 86 #define QSFP_MOD_PWR_OFFS 129 87 /* Byte 130 is Connector type. Not Intel req'd */ 88 /* Bytes 131..138 are Transceiver types, bit maps for various tech, none IB */ 89 /* Byte 139 is encoding. code 0x01 is 8b10b. Not Intel req'd */ 90 /* byte 140 is nominal bit-rate, in units of 100Mbits/sec Not Intel req'd */ 91 /* Byte 141 is Extended Rate Select. Not Intel req'd */ 92 /* Bytes 142..145 are lengths for various fiber types. Not Intel req'd */ 93 /* Byte 146 is length for Copper. Units of 1 meter */ 94 #define QSFP_MOD_LEN_OFFS 146 95 /* 96 * Byte 147 is Device technology. D0..3 not Intel req'd 97 * D4..7 select from 15 choices, translated by table: 98 */ 99 #define QSFP_MOD_TECH_OFFS 147 100 extern const char *const hfi1_qsfp_devtech[16]; 101 /* Active Equalization includes fiber, copper full EQ, and copper near Eq */ 102 #define QSFP_IS_ACTIVE(tech) ((0xA2FF >> ((tech) >> 4)) & 1) 103 /* Active Equalization includes fiber, copper full EQ, and copper far Eq */ 104 #define QSFP_IS_ACTIVE_FAR(tech) ((0x32FF >> ((tech) >> 4)) & 1) 105 /* Attenuation should be valid for copper other than full/near Eq */ 106 #define QSFP_HAS_ATTEN(tech) ((0x4D00 >> ((tech) >> 4)) & 1) 107 /* Length is only valid if technology is "copper" */ 108 #define QSFP_IS_CU(tech) ((0xED00 >> ((tech) >> 4)) & 1) 109 #define QSFP_TECH_1490 9 110 111 #define QSFP_OUI(oui) (((unsigned)oui[0] << 16) | ((unsigned)oui[1] << 8) | \ 112 oui[2]) 113 #define QSFP_OUI_AMPHENOL 0x415048 114 #define QSFP_OUI_FINISAR 0x009065 115 #define QSFP_OUI_GORE 0x002177 116 117 /* Bytes 148..163 are Vendor Name, Left-justified Blank-filled */ 118 #define QSFP_VEND_OFFS 148 119 #define QSFP_VEND_LEN 16 120 /* Byte 164 is IB Extended transceiver codes Bits D0..3 are SDR,DDR,QDR,EDR */ 121 #define QSFP_IBXCV_OFFS 164 122 /* Bytes 165..167 are Vendor OUI number */ 123 #define QSFP_VOUI_OFFS 165 124 #define QSFP_VOUI_LEN 3 125 /* Bytes 168..183 are Vendor Part Number, string */ 126 #define QSFP_PN_OFFS 168 127 #define QSFP_PN_LEN 16 128 /* Bytes 184,185 are Vendor Rev. Left Justified, Blank-filled */ 129 #define QSFP_REV_OFFS 184 130 #define QSFP_REV_LEN 2 131 /* 132 * Bytes 186,187 are Wavelength, if Optical. Not Intel req'd 133 * If copper, they are attenuation in dB: 134 * Byte 186 is at 2.5Gb/sec (SDR), Byte 187 at 5.0Gb/sec (DDR) 135 */ 136 #define QSFP_ATTEN_OFFS 186 137 #define QSFP_ATTEN_LEN 2 138 /* Bytes 188,189 are Wavelength tolerance, not Intel req'd */ 139 /* Byte 190 is Max Case Temp. Not Intel req'd */ 140 /* Byte 191 is LSB of sum of bytes 128..190. Not Intel req'd */ 141 #define QSFP_CC_OFFS 191 142 /* Bytes 192..195 are Options implemented in qsfp. Not Intel req'd */ 143 /* Bytes 196..211 are Serial Number, String */ 144 #define QSFP_SN_OFFS 196 145 #define QSFP_SN_LEN 16 146 /* Bytes 212..219 are date-code YYMMDD (MM==1 for Jan) */ 147 #define QSFP_DATE_OFFS 212 148 #define QSFP_DATE_LEN 6 149 /* Bytes 218,219 are optional lot-code, string */ 150 #define QSFP_LOT_OFFS 218 151 #define QSFP_LOT_LEN 2 152 /* Bytes 220, 221 indicate monitoring options, Not Intel req'd */ 153 /* Byte 223 is LSB of sum of bytes 192..222 */ 154 #define QSFP_CC_EXT_OFFS 223 155 156 /* 157 * Interrupt flag masks 158 */ 159 #define QSFP_DATA_NOT_READY 0x01 160 161 #define QSFP_HIGH_TEMP_ALARM 0x80 162 #define QSFP_LOW_TEMP_ALARM 0x40 163 #define QSFP_HIGH_TEMP_WARNING 0x20 164 #define QSFP_LOW_TEMP_WARNING 0x10 165 166 #define QSFP_HIGH_VCC_ALARM 0x80 167 #define QSFP_LOW_VCC_ALARM 0x40 168 #define QSFP_HIGH_VCC_WARNING 0x20 169 #define QSFP_LOW_VCC_WARNING 0x10 170 171 #define QSFP_HIGH_POWER_ALARM 0x88 172 #define QSFP_LOW_POWER_ALARM 0x44 173 #define QSFP_HIGH_POWER_WARNING 0x22 174 #define QSFP_LOW_POWER_WARNING 0x11 175 176 #define QSFP_HIGH_BIAS_ALARM 0x88 177 #define QSFP_LOW_BIAS_ALARM 0x44 178 #define QSFP_HIGH_BIAS_WARNING 0x22 179 #define QSFP_LOW_BIAS_WARNING 0x11 180 181 /* 182 * struct qsfp_data encapsulates state of QSFP device for one port. 183 * it will be part of port-specific data if a board supports QSFP. 184 * 185 * Since multiple board-types use QSFP, and their pport_data structs 186 * differ (in the chip-specific section), we need a pointer to its head. 187 * 188 * Avoiding premature optimization, we will have one work_struct per port, 189 * and let the qsfp_lock arbitrate access to common resources. 190 * 191 */ 192 193 #define QSFP_PWR(pbyte) (((pbyte) >> 6) & 3) 194 #define QSFP_ATTEN_SDR(attenarray) (attenarray[0]) 195 #define QSFP_ATTEN_DDR(attenarray) (attenarray[1]) 196 197 struct qsfp_data { 198 /* Helps to find our way */ 199 struct hfi1_pportdata *ppd; 200 struct work_struct qsfp_work; 201 u8 cache[QSFP_MAX_NUM_PAGES*128]; 202 spinlock_t qsfp_lock; 203 u8 check_interrupt_flags; 204 u8 qsfp_interrupt_functional; 205 u8 cache_valid; 206 u8 cache_refresh_required; 207 }; 208 209 int refresh_qsfp_cache(struct hfi1_pportdata *ppd, 210 struct qsfp_data *cp); 211 int qsfp_mod_present(struct hfi1_pportdata *ppd); 212 int get_cable_info(struct hfi1_devdata *dd, u32 port_num, u32 addr, 213 u32 len, u8 *data); 214 215 int i2c_write(struct hfi1_pportdata *ppd, u32 target, int i2c_addr, 216 int offset, void *bp, int len); 217 int i2c_read(struct hfi1_pportdata *ppd, u32 target, int i2c_addr, 218 int offset, void *bp, int len); 219 int qsfp_write(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp, 220 int len); 221 int qsfp_read(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp, 222 int len); 223