1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/radeon_drm.h>
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include <linux/pm_runtime.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_plane_helper.h>
36 #include <drm/drm_edid.h>
37
38 #include <linux/gcd.h>
39
avivo_crtc_load_lut(struct drm_crtc * crtc)40 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
41 {
42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
43 struct drm_device *dev = crtc->dev;
44 struct radeon_device *rdev = dev->dev_private;
45 int i;
46
47 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
48 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
49
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
52 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
53
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
56 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
57
58 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
59 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
60 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
61
62 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
63 for (i = 0; i < 256; i++) {
64 WREG32(AVIVO_DC_LUT_30_COLOR,
65 (radeon_crtc->lut_r[i] << 20) |
66 (radeon_crtc->lut_g[i] << 10) |
67 (radeon_crtc->lut_b[i] << 0));
68 }
69
70 /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
71 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
72 }
73
dce4_crtc_load_lut(struct drm_crtc * crtc)74 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
75 {
76 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
77 struct drm_device *dev = crtc->dev;
78 struct radeon_device *rdev = dev->dev_private;
79 int i;
80
81 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
82 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
83
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
86 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
87
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
90 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
91
92 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
93 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
94
95 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
96 for (i = 0; i < 256; i++) {
97 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
98 (radeon_crtc->lut_r[i] << 20) |
99 (radeon_crtc->lut_g[i] << 10) |
100 (radeon_crtc->lut_b[i] << 0));
101 }
102 }
103
dce5_crtc_load_lut(struct drm_crtc * crtc)104 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
105 {
106 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
107 struct drm_device *dev = crtc->dev;
108 struct radeon_device *rdev = dev->dev_private;
109 int i;
110
111 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
112
113 msleep(10);
114
115 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
116 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
117 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
118 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
119 NI_GRPH_PRESCALE_BYPASS);
120 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
121 NI_OVL_PRESCALE_BYPASS);
122 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
123 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
124 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
125
126 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
127
128 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
129 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
130 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
131
132 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
133 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
134 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
135
136 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
137 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
138
139 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
140 for (i = 0; i < 256; i++) {
141 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
142 (radeon_crtc->lut_r[i] << 20) |
143 (radeon_crtc->lut_g[i] << 10) |
144 (radeon_crtc->lut_b[i] << 0));
145 }
146
147 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
148 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
149 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
150 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
151 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
152 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
153 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
154 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
155 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
156 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
157 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
158 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
159 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
160 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
161 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
162 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
163 if (ASIC_IS_DCE8(rdev)) {
164 /* XXX this only needs to be programmed once per crtc at startup,
165 * not sure where the best place for it is
166 */
167 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
168 CIK_CURSOR_ALPHA_BLND_ENA);
169 }
170 }
171
legacy_crtc_load_lut(struct drm_crtc * crtc)172 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
173 {
174 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
175 struct drm_device *dev = crtc->dev;
176 struct radeon_device *rdev = dev->dev_private;
177 int i;
178 uint32_t dac2_cntl;
179
180 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
181 if (radeon_crtc->crtc_id == 0)
182 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
183 else
184 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
185 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
186
187 WREG8(RADEON_PALETTE_INDEX, 0);
188 for (i = 0; i < 256; i++) {
189 WREG32(RADEON_PALETTE_30_DATA,
190 (radeon_crtc->lut_r[i] << 20) |
191 (radeon_crtc->lut_g[i] << 10) |
192 (radeon_crtc->lut_b[i] << 0));
193 }
194 }
195
radeon_crtc_load_lut(struct drm_crtc * crtc)196 void radeon_crtc_load_lut(struct drm_crtc *crtc)
197 {
198 struct drm_device *dev = crtc->dev;
199 struct radeon_device *rdev = dev->dev_private;
200
201 if (!crtc->enabled)
202 return;
203
204 if (ASIC_IS_DCE5(rdev))
205 dce5_crtc_load_lut(crtc);
206 else if (ASIC_IS_DCE4(rdev))
207 dce4_crtc_load_lut(crtc);
208 else if (ASIC_IS_AVIVO(rdev))
209 avivo_crtc_load_lut(crtc);
210 else
211 legacy_crtc_load_lut(crtc);
212 }
213
214 /** Sets the color ramps on behalf of fbcon */
radeon_crtc_fb_gamma_set(struct drm_crtc * crtc,u16 red,u16 green,u16 blue,int regno)215 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
216 u16 blue, int regno)
217 {
218 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
219
220 radeon_crtc->lut_r[regno] = red >> 6;
221 radeon_crtc->lut_g[regno] = green >> 6;
222 radeon_crtc->lut_b[regno] = blue >> 6;
223 }
224
225 /** Gets the color ramps on behalf of fbcon */
radeon_crtc_fb_gamma_get(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,int regno)226 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
227 u16 *blue, int regno)
228 {
229 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
230
231 *red = radeon_crtc->lut_r[regno] << 6;
232 *green = radeon_crtc->lut_g[regno] << 6;
233 *blue = radeon_crtc->lut_b[regno] << 6;
234 }
235
radeon_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t start,uint32_t size)236 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
237 u16 *blue, uint32_t start, uint32_t size)
238 {
239 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
240 int end = (start + size > 256) ? 256 : start + size, i;
241
242 /* userspace palettes are always correct as is */
243 for (i = start; i < end; i++) {
244 radeon_crtc->lut_r[i] = red[i] >> 6;
245 radeon_crtc->lut_g[i] = green[i] >> 6;
246 radeon_crtc->lut_b[i] = blue[i] >> 6;
247 }
248 radeon_crtc_load_lut(crtc);
249 }
250
radeon_crtc_destroy(struct drm_crtc * crtc)251 static void radeon_crtc_destroy(struct drm_crtc *crtc)
252 {
253 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
254
255 drm_crtc_cleanup(crtc);
256 destroy_workqueue(radeon_crtc->flip_queue);
257 kfree(radeon_crtc);
258 }
259
260 /**
261 * radeon_unpin_work_func - unpin old buffer object
262 *
263 * @__work - kernel work item
264 *
265 * Unpin the old frame buffer object outside of the interrupt handler
266 */
radeon_unpin_work_func(struct work_struct * __work)267 static void radeon_unpin_work_func(struct work_struct *__work)
268 {
269 struct radeon_flip_work *work =
270 container_of(__work, struct radeon_flip_work, unpin_work);
271 int r;
272
273 /* unpin of the old buffer */
274 r = radeon_bo_reserve(work->old_rbo, false);
275 if (likely(r == 0)) {
276 r = radeon_bo_unpin(work->old_rbo);
277 if (unlikely(r != 0)) {
278 DRM_ERROR("failed to unpin buffer after flip\n");
279 }
280 radeon_bo_unreserve(work->old_rbo);
281 } else
282 DRM_ERROR("failed to reserve buffer after flip\n");
283
284 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
285 kfree(work);
286 }
287
radeon_crtc_handle_vblank(struct radeon_device * rdev,int crtc_id)288 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
289 {
290 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
291 unsigned long flags;
292 u32 update_pending;
293 int vpos, hpos;
294
295 /* can happen during initialization */
296 if (radeon_crtc == NULL)
297 return;
298
299 /* Skip the pageflip completion check below (based on polling) on
300 * asics which reliably support hw pageflip completion irqs. pflip
301 * irqs are a reliable and race-free method of handling pageflip
302 * completion detection. A use_pflipirq module parameter < 2 allows
303 * to override this in case of asics with faulty pflip irqs.
304 * A module parameter of 0 would only use this polling based path,
305 * a parameter of 1 would use pflip irq only as a backup to this
306 * path, as in Linux 3.16.
307 */
308 if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
309 return;
310
311 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
312 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
313 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
314 "RADEON_FLIP_SUBMITTED(%d)\n",
315 radeon_crtc->flip_status,
316 RADEON_FLIP_SUBMITTED);
317 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
318 return;
319 }
320
321 update_pending = radeon_page_flip_pending(rdev, crtc_id);
322
323 /* Has the pageflip already completed in crtc, or is it certain
324 * to complete in this vblank?
325 */
326 if (update_pending &&
327 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev,
328 crtc_id,
329 USE_REAL_VBLANKSTART,
330 &vpos, &hpos, NULL, NULL,
331 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
332 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
333 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
334 /* crtc didn't flip in this target vblank interval,
335 * but flip is pending in crtc. Based on the current
336 * scanout position we know that the current frame is
337 * (nearly) complete and the flip will (likely)
338 * complete before the start of the next frame.
339 */
340 update_pending = 0;
341 }
342 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
343 if (!update_pending)
344 radeon_crtc_handle_flip(rdev, crtc_id);
345 }
346
347 /**
348 * radeon_crtc_handle_flip - page flip completed
349 *
350 * @rdev: radeon device pointer
351 * @crtc_id: crtc number this event is for
352 *
353 * Called when we are sure that a page flip for this crtc is completed.
354 */
radeon_crtc_handle_flip(struct radeon_device * rdev,int crtc_id)355 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
356 {
357 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
358 struct radeon_flip_work *work;
359 unsigned long flags;
360
361 /* this can happen at init */
362 if (radeon_crtc == NULL)
363 return;
364
365 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
366 work = radeon_crtc->flip_work;
367 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
368 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
369 "RADEON_FLIP_SUBMITTED(%d)\n",
370 radeon_crtc->flip_status,
371 RADEON_FLIP_SUBMITTED);
372 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
373 return;
374 }
375
376 /* Pageflip completed. Clean up. */
377 radeon_crtc->flip_status = RADEON_FLIP_NONE;
378 radeon_crtc->flip_work = NULL;
379
380 /* wakeup userspace */
381 if (work->event)
382 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
383
384 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
385
386 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
387 radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
388 queue_work(radeon_crtc->flip_queue, &work->unpin_work);
389 }
390
391 /**
392 * radeon_flip_work_func - page flip framebuffer
393 *
394 * @work - kernel work item
395 *
396 * Wait for the buffer object to become idle and do the actual page flip
397 */
radeon_flip_work_func(struct work_struct * __work)398 static void radeon_flip_work_func(struct work_struct *__work)
399 {
400 struct radeon_flip_work *work =
401 container_of(__work, struct radeon_flip_work, flip_work);
402 struct radeon_device *rdev = work->rdev;
403 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
404
405 struct drm_crtc *crtc = &radeon_crtc->base;
406 unsigned long flags;
407 int r;
408 int vpos, hpos, stat, min_udelay = 0;
409 unsigned repcnt = 4;
410 struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id];
411
412 down_read(&rdev->exclusive_lock);
413 if (work->fence) {
414 struct radeon_fence *fence;
415
416 fence = to_radeon_fence(work->fence);
417 if (fence && fence->rdev == rdev) {
418 r = radeon_fence_wait(fence, false);
419 if (r == -EDEADLK) {
420 up_read(&rdev->exclusive_lock);
421 do {
422 r = radeon_gpu_reset(rdev);
423 } while (r == -EAGAIN);
424 down_read(&rdev->exclusive_lock);
425 }
426 } else
427 r = fence_wait(work->fence, false);
428
429 if (r)
430 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
431
432 /* We continue with the page flip even if we failed to wait on
433 * the fence, otherwise the DRM core and userspace will be
434 * confused about which BO the CRTC is scanning out
435 */
436
437 fence_put(work->fence);
438 work->fence = NULL;
439 }
440
441 /* We borrow the event spin lock for protecting flip_status */
442 spin_lock_irqsave(&crtc->dev->event_lock, flags);
443
444 /* set the proper interrupt */
445 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
446
447 /* If this happens to execute within the "virtually extended" vblank
448 * interval before the start of the real vblank interval then it needs
449 * to delay programming the mmio flip until the real vblank is entered.
450 * This prevents completing a flip too early due to the way we fudge
451 * our vblank counter and vblank timestamps in order to work around the
452 * problem that the hw fires vblank interrupts before actual start of
453 * vblank (when line buffer refilling is done for a frame). It
454 * complements the fudging logic in radeon_get_crtc_scanoutpos() for
455 * timestamping and radeon_get_vblank_counter_kms() for vblank counts.
456 *
457 * In practice this won't execute very often unless on very fast
458 * machines because the time window for this to happen is very small.
459 */
460 while (radeon_crtc->enabled && --repcnt) {
461 /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank
462 * start in hpos, and to the "fudged earlier" vblank start in
463 * vpos.
464 */
465 stat = radeon_get_crtc_scanoutpos(rdev->ddev, work->crtc_id,
466 GET_DISTANCE_TO_VBLANKSTART,
467 &vpos, &hpos, NULL, NULL,
468 &crtc->hwmode);
469
470 if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
471 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) ||
472 !(vpos >= 0 && hpos <= 0))
473 break;
474
475 /* Sleep at least until estimated real start of hw vblank */
476 min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5);
477 if (min_udelay > vblank->framedur_ns / 2000) {
478 /* Don't wait ridiculously long - something is wrong */
479 repcnt = 0;
480 break;
481 }
482 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
483 usleep_range(min_udelay, 2 * min_udelay);
484 spin_lock_irqsave(&crtc->dev->event_lock, flags);
485 };
486
487 if (!repcnt)
488 DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, "
489 "framedur %d, linedur %d, stat %d, vpos %d, "
490 "hpos %d\n", work->crtc_id, min_udelay,
491 vblank->framedur_ns / 1000,
492 vblank->linedur_ns / 1000, stat, vpos, hpos);
493
494 /* do the flip (mmio) */
495 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base);
496
497 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
498 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
499 up_read(&rdev->exclusive_lock);
500 }
501
radeon_crtc_page_flip(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event,uint32_t page_flip_flags)502 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
503 struct drm_framebuffer *fb,
504 struct drm_pending_vblank_event *event,
505 uint32_t page_flip_flags)
506 {
507 struct drm_device *dev = crtc->dev;
508 struct radeon_device *rdev = dev->dev_private;
509 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
510 struct radeon_framebuffer *old_radeon_fb;
511 struct radeon_framebuffer *new_radeon_fb;
512 struct drm_gem_object *obj;
513 struct radeon_flip_work *work;
514 struct radeon_bo *new_rbo;
515 uint32_t tiling_flags, pitch_pixels;
516 uint64_t base;
517 unsigned long flags;
518 int r;
519
520 work = kzalloc(sizeof *work, GFP_KERNEL);
521 if (work == NULL)
522 return -ENOMEM;
523
524 INIT_WORK(&work->flip_work, radeon_flip_work_func);
525 INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
526
527 work->rdev = rdev;
528 work->crtc_id = radeon_crtc->crtc_id;
529 work->event = event;
530
531 /* schedule unpin of the old buffer */
532 old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
533 obj = old_radeon_fb->obj;
534
535 /* take a reference to the old object */
536 drm_gem_object_reference(obj);
537 work->old_rbo = gem_to_radeon_bo(obj);
538
539 new_radeon_fb = to_radeon_framebuffer(fb);
540 obj = new_radeon_fb->obj;
541 new_rbo = gem_to_radeon_bo(obj);
542
543 /* pin the new buffer */
544 DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
545 work->old_rbo, new_rbo);
546
547 r = radeon_bo_reserve(new_rbo, false);
548 if (unlikely(r != 0)) {
549 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
550 goto cleanup;
551 }
552 /* Only 27 bit offset for legacy CRTC */
553 r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
554 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
555 if (unlikely(r != 0)) {
556 radeon_bo_unreserve(new_rbo);
557 r = -EINVAL;
558 DRM_ERROR("failed to pin new rbo buffer before flip\n");
559 goto cleanup;
560 }
561 work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
562 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
563 radeon_bo_unreserve(new_rbo);
564
565 if (!ASIC_IS_AVIVO(rdev)) {
566 /* crtc offset is from display base addr not FB location */
567 base -= radeon_crtc->legacy_display_base_addr;
568 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
569
570 if (tiling_flags & RADEON_TILING_MACRO) {
571 if (ASIC_IS_R300(rdev)) {
572 base &= ~0x7ff;
573 } else {
574 int byteshift = fb->bits_per_pixel >> 4;
575 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
576 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
577 }
578 } else {
579 int offset = crtc->y * pitch_pixels + crtc->x;
580 switch (fb->bits_per_pixel) {
581 case 8:
582 default:
583 offset *= 1;
584 break;
585 case 15:
586 case 16:
587 offset *= 2;
588 break;
589 case 24:
590 offset *= 3;
591 break;
592 case 32:
593 offset *= 4;
594 break;
595 }
596 base += offset;
597 }
598 base &= ~7;
599 }
600 work->base = base;
601
602 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id);
603 if (r) {
604 DRM_ERROR("failed to get vblank before flip\n");
605 goto pflip_cleanup;
606 }
607
608 /* We borrow the event spin lock for protecting flip_work */
609 spin_lock_irqsave(&crtc->dev->event_lock, flags);
610
611 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
612 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
613 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
614 r = -EBUSY;
615 goto vblank_cleanup;
616 }
617 radeon_crtc->flip_status = RADEON_FLIP_PENDING;
618 radeon_crtc->flip_work = work;
619
620 /* update crtc fb */
621 crtc->primary->fb = fb;
622
623 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
624
625 queue_work(radeon_crtc->flip_queue, &work->flip_work);
626 return 0;
627
628 vblank_cleanup:
629 drm_vblank_put(crtc->dev, radeon_crtc->crtc_id);
630
631 pflip_cleanup:
632 if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
633 DRM_ERROR("failed to reserve new rbo in error path\n");
634 goto cleanup;
635 }
636 if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
637 DRM_ERROR("failed to unpin new rbo in error path\n");
638 }
639 radeon_bo_unreserve(new_rbo);
640
641 cleanup:
642 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
643 fence_put(work->fence);
644 kfree(work);
645 return r;
646 }
647
648 static int
radeon_crtc_set_config(struct drm_mode_set * set)649 radeon_crtc_set_config(struct drm_mode_set *set)
650 {
651 struct drm_device *dev;
652 struct radeon_device *rdev;
653 struct drm_crtc *crtc;
654 bool active = false;
655 int ret;
656
657 if (!set || !set->crtc)
658 return -EINVAL;
659
660 dev = set->crtc->dev;
661
662 ret = pm_runtime_get_sync(dev->dev);
663 if (ret < 0) {
664 pm_runtime_put_autosuspend(dev->dev);
665 return ret;
666 }
667
668 ret = drm_crtc_helper_set_config(set);
669
670 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
671 if (crtc->enabled)
672 active = true;
673
674 pm_runtime_mark_last_busy(dev->dev);
675
676 rdev = dev->dev_private;
677 /* if we have active crtcs and we don't have a power ref,
678 take the current one */
679 if (active && !rdev->have_disp_power_ref) {
680 rdev->have_disp_power_ref = true;
681 return ret;
682 }
683 /* if we have no active crtcs, then drop the power ref
684 we got before */
685 if (!active && rdev->have_disp_power_ref) {
686 pm_runtime_put_autosuspend(dev->dev);
687 rdev->have_disp_power_ref = false;
688 }
689
690 /* drop the power reference we got coming in here */
691 pm_runtime_put_autosuspend(dev->dev);
692 return ret;
693 }
694 static const struct drm_crtc_funcs radeon_crtc_funcs = {
695 .cursor_set2 = radeon_crtc_cursor_set2,
696 .cursor_move = radeon_crtc_cursor_move,
697 .gamma_set = radeon_crtc_gamma_set,
698 .set_config = radeon_crtc_set_config,
699 .destroy = radeon_crtc_destroy,
700 .page_flip = radeon_crtc_page_flip,
701 };
702
radeon_crtc_init(struct drm_device * dev,int index)703 static void radeon_crtc_init(struct drm_device *dev, int index)
704 {
705 struct radeon_device *rdev = dev->dev_private;
706 struct radeon_crtc *radeon_crtc;
707 int i;
708
709 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
710 if (radeon_crtc == NULL)
711 return;
712
713 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
714
715 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
716 radeon_crtc->crtc_id = index;
717 radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc");
718 rdev->mode_info.crtcs[index] = radeon_crtc;
719
720 if (rdev->family >= CHIP_BONAIRE) {
721 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
722 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
723 } else {
724 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
725 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
726 }
727 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
728 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
729
730 #if 0
731 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
732 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
733 radeon_crtc->mode_set.num_connectors = 0;
734 #endif
735
736 for (i = 0; i < 256; i++) {
737 radeon_crtc->lut_r[i] = i << 2;
738 radeon_crtc->lut_g[i] = i << 2;
739 radeon_crtc->lut_b[i] = i << 2;
740 }
741
742 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
743 radeon_atombios_init_crtc(dev, radeon_crtc);
744 else
745 radeon_legacy_init_crtc(dev, radeon_crtc);
746 }
747
748 static const char *encoder_names[38] = {
749 "NONE",
750 "INTERNAL_LVDS",
751 "INTERNAL_TMDS1",
752 "INTERNAL_TMDS2",
753 "INTERNAL_DAC1",
754 "INTERNAL_DAC2",
755 "INTERNAL_SDVOA",
756 "INTERNAL_SDVOB",
757 "SI170B",
758 "CH7303",
759 "CH7301",
760 "INTERNAL_DVO1",
761 "EXTERNAL_SDVOA",
762 "EXTERNAL_SDVOB",
763 "TITFP513",
764 "INTERNAL_LVTM1",
765 "VT1623",
766 "HDMI_SI1930",
767 "HDMI_INTERNAL",
768 "INTERNAL_KLDSCP_TMDS1",
769 "INTERNAL_KLDSCP_DVO1",
770 "INTERNAL_KLDSCP_DAC1",
771 "INTERNAL_KLDSCP_DAC2",
772 "SI178",
773 "MVPU_FPGA",
774 "INTERNAL_DDI",
775 "VT1625",
776 "HDMI_SI1932",
777 "DP_AN9801",
778 "DP_DP501",
779 "INTERNAL_UNIPHY",
780 "INTERNAL_KLDSCP_LVTMA",
781 "INTERNAL_UNIPHY1",
782 "INTERNAL_UNIPHY2",
783 "NUTMEG",
784 "TRAVIS",
785 "INTERNAL_VCE",
786 "INTERNAL_UNIPHY3",
787 };
788
789 static const char *hpd_names[6] = {
790 "HPD1",
791 "HPD2",
792 "HPD3",
793 "HPD4",
794 "HPD5",
795 "HPD6",
796 };
797
radeon_print_display_setup(struct drm_device * dev)798 static void radeon_print_display_setup(struct drm_device *dev)
799 {
800 struct drm_connector *connector;
801 struct radeon_connector *radeon_connector;
802 struct drm_encoder *encoder;
803 struct radeon_encoder *radeon_encoder;
804 uint32_t devices;
805 int i = 0;
806
807 DRM_INFO("Radeon Display Connectors\n");
808 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
809 radeon_connector = to_radeon_connector(connector);
810 DRM_INFO("Connector %d:\n", i);
811 DRM_INFO(" %s\n", connector->name);
812 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
813 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
814 if (radeon_connector->ddc_bus) {
815 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
816 radeon_connector->ddc_bus->rec.mask_clk_reg,
817 radeon_connector->ddc_bus->rec.mask_data_reg,
818 radeon_connector->ddc_bus->rec.a_clk_reg,
819 radeon_connector->ddc_bus->rec.a_data_reg,
820 radeon_connector->ddc_bus->rec.en_clk_reg,
821 radeon_connector->ddc_bus->rec.en_data_reg,
822 radeon_connector->ddc_bus->rec.y_clk_reg,
823 radeon_connector->ddc_bus->rec.y_data_reg);
824 if (radeon_connector->router.ddc_valid)
825 DRM_INFO(" DDC Router 0x%x/0x%x\n",
826 radeon_connector->router.ddc_mux_control_pin,
827 radeon_connector->router.ddc_mux_state);
828 if (radeon_connector->router.cd_valid)
829 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
830 radeon_connector->router.cd_mux_control_pin,
831 radeon_connector->router.cd_mux_state);
832 } else {
833 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
834 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
835 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
836 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
837 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
838 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
839 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
840 }
841 DRM_INFO(" Encoders:\n");
842 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
843 radeon_encoder = to_radeon_encoder(encoder);
844 devices = radeon_encoder->devices & radeon_connector->devices;
845 if (devices) {
846 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
847 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
848 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
849 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
850 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
851 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
852 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
853 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
854 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
855 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
856 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
857 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
858 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
859 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
860 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
861 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
862 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
863 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
864 if (devices & ATOM_DEVICE_TV1_SUPPORT)
865 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
866 if (devices & ATOM_DEVICE_CV_SUPPORT)
867 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
868 }
869 }
870 i++;
871 }
872 }
873
radeon_setup_enc_conn(struct drm_device * dev)874 static bool radeon_setup_enc_conn(struct drm_device *dev)
875 {
876 struct radeon_device *rdev = dev->dev_private;
877 bool ret = false;
878
879 if (rdev->bios) {
880 if (rdev->is_atom_bios) {
881 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
882 if (ret == false)
883 ret = radeon_get_atom_connector_info_from_object_table(dev);
884 } else {
885 ret = radeon_get_legacy_connector_info_from_bios(dev);
886 if (ret == false)
887 ret = radeon_get_legacy_connector_info_from_table(dev);
888 }
889 } else {
890 if (!ASIC_IS_AVIVO(rdev))
891 ret = radeon_get_legacy_connector_info_from_table(dev);
892 }
893 if (ret) {
894 radeon_setup_encoder_clones(dev);
895 radeon_print_display_setup(dev);
896 }
897
898 return ret;
899 }
900
901 /* avivo */
902
903 /**
904 * avivo_reduce_ratio - fractional number reduction
905 *
906 * @nom: nominator
907 * @den: denominator
908 * @nom_min: minimum value for nominator
909 * @den_min: minimum value for denominator
910 *
911 * Find the greatest common divisor and apply it on both nominator and
912 * denominator, but make nominator and denominator are at least as large
913 * as their minimum values.
914 */
avivo_reduce_ratio(unsigned * nom,unsigned * den,unsigned nom_min,unsigned den_min)915 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
916 unsigned nom_min, unsigned den_min)
917 {
918 unsigned tmp;
919
920 /* reduce the numbers to a simpler ratio */
921 tmp = gcd(*nom, *den);
922 *nom /= tmp;
923 *den /= tmp;
924
925 /* make sure nominator is large enough */
926 if (*nom < nom_min) {
927 tmp = DIV_ROUND_UP(nom_min, *nom);
928 *nom *= tmp;
929 *den *= tmp;
930 }
931
932 /* make sure the denominator is large enough */
933 if (*den < den_min) {
934 tmp = DIV_ROUND_UP(den_min, *den);
935 *nom *= tmp;
936 *den *= tmp;
937 }
938 }
939
940 /**
941 * avivo_get_fb_ref_div - feedback and ref divider calculation
942 *
943 * @nom: nominator
944 * @den: denominator
945 * @post_div: post divider
946 * @fb_div_max: feedback divider maximum
947 * @ref_div_max: reference divider maximum
948 * @fb_div: resulting feedback divider
949 * @ref_div: resulting reference divider
950 *
951 * Calculate feedback and reference divider for a given post divider. Makes
952 * sure we stay within the limits.
953 */
avivo_get_fb_ref_div(unsigned nom,unsigned den,unsigned post_div,unsigned fb_div_max,unsigned ref_div_max,unsigned * fb_div,unsigned * ref_div)954 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
955 unsigned fb_div_max, unsigned ref_div_max,
956 unsigned *fb_div, unsigned *ref_div)
957 {
958 /* limit reference * post divider to a maximum */
959 ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
960
961 /* get matching reference and feedback divider */
962 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
963 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
964
965 /* limit fb divider to its maximum */
966 if (*fb_div > fb_div_max) {
967 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
968 *fb_div = fb_div_max;
969 }
970 }
971
972 /**
973 * radeon_compute_pll_avivo - compute PLL paramaters
974 *
975 * @pll: information about the PLL
976 * @dot_clock_p: resulting pixel clock
977 * fb_div_p: resulting feedback divider
978 * frac_fb_div_p: fractional part of the feedback divider
979 * ref_div_p: resulting reference divider
980 * post_div_p: resulting reference divider
981 *
982 * Try to calculate the PLL parameters to generate the given frequency:
983 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
984 */
radeon_compute_pll_avivo(struct radeon_pll * pll,u32 freq,u32 * dot_clock_p,u32 * fb_div_p,u32 * frac_fb_div_p,u32 * ref_div_p,u32 * post_div_p)985 void radeon_compute_pll_avivo(struct radeon_pll *pll,
986 u32 freq,
987 u32 *dot_clock_p,
988 u32 *fb_div_p,
989 u32 *frac_fb_div_p,
990 u32 *ref_div_p,
991 u32 *post_div_p)
992 {
993 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
994 freq : freq / 10;
995
996 unsigned fb_div_min, fb_div_max, fb_div;
997 unsigned post_div_min, post_div_max, post_div;
998 unsigned ref_div_min, ref_div_max, ref_div;
999 unsigned post_div_best, diff_best;
1000 unsigned nom, den;
1001
1002 /* determine allowed feedback divider range */
1003 fb_div_min = pll->min_feedback_div;
1004 fb_div_max = pll->max_feedback_div;
1005
1006 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1007 fb_div_min *= 10;
1008 fb_div_max *= 10;
1009 }
1010
1011 /* determine allowed ref divider range */
1012 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1013 ref_div_min = pll->reference_div;
1014 else
1015 ref_div_min = pll->min_ref_div;
1016
1017 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
1018 pll->flags & RADEON_PLL_USE_REF_DIV)
1019 ref_div_max = pll->reference_div;
1020 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1021 /* fix for problems on RS880 */
1022 ref_div_max = min(pll->max_ref_div, 7u);
1023 else
1024 ref_div_max = pll->max_ref_div;
1025
1026 /* determine allowed post divider range */
1027 if (pll->flags & RADEON_PLL_USE_POST_DIV) {
1028 post_div_min = pll->post_div;
1029 post_div_max = pll->post_div;
1030 } else {
1031 unsigned vco_min, vco_max;
1032
1033 if (pll->flags & RADEON_PLL_IS_LCD) {
1034 vco_min = pll->lcd_pll_out_min;
1035 vco_max = pll->lcd_pll_out_max;
1036 } else {
1037 vco_min = pll->pll_out_min;
1038 vco_max = pll->pll_out_max;
1039 }
1040
1041 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1042 vco_min *= 10;
1043 vco_max *= 10;
1044 }
1045
1046 post_div_min = vco_min / target_clock;
1047 if ((target_clock * post_div_min) < vco_min)
1048 ++post_div_min;
1049 if (post_div_min < pll->min_post_div)
1050 post_div_min = pll->min_post_div;
1051
1052 post_div_max = vco_max / target_clock;
1053 if ((target_clock * post_div_max) > vco_max)
1054 --post_div_max;
1055 if (post_div_max > pll->max_post_div)
1056 post_div_max = pll->max_post_div;
1057 }
1058
1059 /* represent the searched ratio as fractional number */
1060 nom = target_clock;
1061 den = pll->reference_freq;
1062
1063 /* reduce the numbers to a simpler ratio */
1064 avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1065
1066 /* now search for a post divider */
1067 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1068 post_div_best = post_div_min;
1069 else
1070 post_div_best = post_div_max;
1071 diff_best = ~0;
1072
1073 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1074 unsigned diff;
1075 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1076 ref_div_max, &fb_div, &ref_div);
1077 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1078 (ref_div * post_div));
1079
1080 if (diff < diff_best || (diff == diff_best &&
1081 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1082
1083 post_div_best = post_div;
1084 diff_best = diff;
1085 }
1086 }
1087 post_div = post_div_best;
1088
1089 /* get the feedback and reference divider for the optimal value */
1090 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1091 &fb_div, &ref_div);
1092
1093 /* reduce the numbers to a simpler ratio once more */
1094 /* this also makes sure that the reference divider is large enough */
1095 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1096
1097 /* avoid high jitter with small fractional dividers */
1098 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1099 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1100 if (fb_div < fb_div_min) {
1101 unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1102 fb_div *= tmp;
1103 ref_div *= tmp;
1104 }
1105 }
1106
1107 /* and finally save the result */
1108 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1109 *fb_div_p = fb_div / 10;
1110 *frac_fb_div_p = fb_div % 10;
1111 } else {
1112 *fb_div_p = fb_div;
1113 *frac_fb_div_p = 0;
1114 }
1115
1116 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1117 (pll->reference_freq * *frac_fb_div_p)) /
1118 (ref_div * post_div * 10);
1119 *ref_div_p = ref_div;
1120 *post_div_p = post_div;
1121
1122 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1123 freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1124 ref_div, post_div);
1125 }
1126
1127 /* pre-avivo */
radeon_div(uint64_t n,uint32_t d)1128 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1129 {
1130 uint64_t mod;
1131
1132 n += d / 2;
1133
1134 mod = do_div(n, d);
1135 return n;
1136 }
1137
radeon_compute_pll_legacy(struct radeon_pll * pll,uint64_t freq,uint32_t * dot_clock_p,uint32_t * fb_div_p,uint32_t * frac_fb_div_p,uint32_t * ref_div_p,uint32_t * post_div_p)1138 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1139 uint64_t freq,
1140 uint32_t *dot_clock_p,
1141 uint32_t *fb_div_p,
1142 uint32_t *frac_fb_div_p,
1143 uint32_t *ref_div_p,
1144 uint32_t *post_div_p)
1145 {
1146 uint32_t min_ref_div = pll->min_ref_div;
1147 uint32_t max_ref_div = pll->max_ref_div;
1148 uint32_t min_post_div = pll->min_post_div;
1149 uint32_t max_post_div = pll->max_post_div;
1150 uint32_t min_fractional_feed_div = 0;
1151 uint32_t max_fractional_feed_div = 0;
1152 uint32_t best_vco = pll->best_vco;
1153 uint32_t best_post_div = 1;
1154 uint32_t best_ref_div = 1;
1155 uint32_t best_feedback_div = 1;
1156 uint32_t best_frac_feedback_div = 0;
1157 uint32_t best_freq = -1;
1158 uint32_t best_error = 0xffffffff;
1159 uint32_t best_vco_diff = 1;
1160 uint32_t post_div;
1161 u32 pll_out_min, pll_out_max;
1162
1163 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1164 freq = freq * 1000;
1165
1166 if (pll->flags & RADEON_PLL_IS_LCD) {
1167 pll_out_min = pll->lcd_pll_out_min;
1168 pll_out_max = pll->lcd_pll_out_max;
1169 } else {
1170 pll_out_min = pll->pll_out_min;
1171 pll_out_max = pll->pll_out_max;
1172 }
1173
1174 if (pll_out_min > 64800)
1175 pll_out_min = 64800;
1176
1177 if (pll->flags & RADEON_PLL_USE_REF_DIV)
1178 min_ref_div = max_ref_div = pll->reference_div;
1179 else {
1180 while (min_ref_div < max_ref_div-1) {
1181 uint32_t mid = (min_ref_div + max_ref_div) / 2;
1182 uint32_t pll_in = pll->reference_freq / mid;
1183 if (pll_in < pll->pll_in_min)
1184 max_ref_div = mid;
1185 else if (pll_in > pll->pll_in_max)
1186 min_ref_div = mid;
1187 else
1188 break;
1189 }
1190 }
1191
1192 if (pll->flags & RADEON_PLL_USE_POST_DIV)
1193 min_post_div = max_post_div = pll->post_div;
1194
1195 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1196 min_fractional_feed_div = pll->min_frac_feedback_div;
1197 max_fractional_feed_div = pll->max_frac_feedback_div;
1198 }
1199
1200 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1201 uint32_t ref_div;
1202
1203 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1204 continue;
1205
1206 /* legacy radeons only have a few post_divs */
1207 if (pll->flags & RADEON_PLL_LEGACY) {
1208 if ((post_div == 5) ||
1209 (post_div == 7) ||
1210 (post_div == 9) ||
1211 (post_div == 10) ||
1212 (post_div == 11) ||
1213 (post_div == 13) ||
1214 (post_div == 14) ||
1215 (post_div == 15))
1216 continue;
1217 }
1218
1219 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1220 uint32_t feedback_div, current_freq = 0, error, vco_diff;
1221 uint32_t pll_in = pll->reference_freq / ref_div;
1222 uint32_t min_feed_div = pll->min_feedback_div;
1223 uint32_t max_feed_div = pll->max_feedback_div + 1;
1224
1225 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1226 continue;
1227
1228 while (min_feed_div < max_feed_div) {
1229 uint32_t vco;
1230 uint32_t min_frac_feed_div = min_fractional_feed_div;
1231 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1232 uint32_t frac_feedback_div;
1233 uint64_t tmp;
1234
1235 feedback_div = (min_feed_div + max_feed_div) / 2;
1236
1237 tmp = (uint64_t)pll->reference_freq * feedback_div;
1238 vco = radeon_div(tmp, ref_div);
1239
1240 if (vco < pll_out_min) {
1241 min_feed_div = feedback_div + 1;
1242 continue;
1243 } else if (vco > pll_out_max) {
1244 max_feed_div = feedback_div;
1245 continue;
1246 }
1247
1248 while (min_frac_feed_div < max_frac_feed_div) {
1249 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1250 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1251 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1252 current_freq = radeon_div(tmp, ref_div * post_div);
1253
1254 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1255 if (freq < current_freq)
1256 error = 0xffffffff;
1257 else
1258 error = freq - current_freq;
1259 } else
1260 error = abs(current_freq - freq);
1261 vco_diff = abs(vco - best_vco);
1262
1263 if ((best_vco == 0 && error < best_error) ||
1264 (best_vco != 0 &&
1265 ((best_error > 100 && error < best_error - 100) ||
1266 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1267 best_post_div = post_div;
1268 best_ref_div = ref_div;
1269 best_feedback_div = feedback_div;
1270 best_frac_feedback_div = frac_feedback_div;
1271 best_freq = current_freq;
1272 best_error = error;
1273 best_vco_diff = vco_diff;
1274 } else if (current_freq == freq) {
1275 if (best_freq == -1) {
1276 best_post_div = post_div;
1277 best_ref_div = ref_div;
1278 best_feedback_div = feedback_div;
1279 best_frac_feedback_div = frac_feedback_div;
1280 best_freq = current_freq;
1281 best_error = error;
1282 best_vco_diff = vco_diff;
1283 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1284 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1285 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1286 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1287 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1288 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1289 best_post_div = post_div;
1290 best_ref_div = ref_div;
1291 best_feedback_div = feedback_div;
1292 best_frac_feedback_div = frac_feedback_div;
1293 best_freq = current_freq;
1294 best_error = error;
1295 best_vco_diff = vco_diff;
1296 }
1297 }
1298 if (current_freq < freq)
1299 min_frac_feed_div = frac_feedback_div + 1;
1300 else
1301 max_frac_feed_div = frac_feedback_div;
1302 }
1303 if (current_freq < freq)
1304 min_feed_div = feedback_div + 1;
1305 else
1306 max_feed_div = feedback_div;
1307 }
1308 }
1309 }
1310
1311 *dot_clock_p = best_freq / 10000;
1312 *fb_div_p = best_feedback_div;
1313 *frac_fb_div_p = best_frac_feedback_div;
1314 *ref_div_p = best_ref_div;
1315 *post_div_p = best_post_div;
1316 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1317 (long long)freq,
1318 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1319 best_ref_div, best_post_div);
1320
1321 }
1322
radeon_user_framebuffer_destroy(struct drm_framebuffer * fb)1323 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1324 {
1325 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1326
1327 if (radeon_fb->obj) {
1328 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1329 }
1330 drm_framebuffer_cleanup(fb);
1331 kfree(radeon_fb);
1332 }
1333
radeon_user_framebuffer_create_handle(struct drm_framebuffer * fb,struct drm_file * file_priv,unsigned int * handle)1334 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1335 struct drm_file *file_priv,
1336 unsigned int *handle)
1337 {
1338 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1339
1340 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1341 }
1342
1343 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1344 .destroy = radeon_user_framebuffer_destroy,
1345 .create_handle = radeon_user_framebuffer_create_handle,
1346 };
1347
1348 int
radeon_framebuffer_init(struct drm_device * dev,struct radeon_framebuffer * rfb,struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1349 radeon_framebuffer_init(struct drm_device *dev,
1350 struct radeon_framebuffer *rfb,
1351 struct drm_mode_fb_cmd2 *mode_cmd,
1352 struct drm_gem_object *obj)
1353 {
1354 int ret;
1355 rfb->obj = obj;
1356 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1357 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1358 if (ret) {
1359 rfb->obj = NULL;
1360 return ret;
1361 }
1362 return 0;
1363 }
1364
1365 static struct drm_framebuffer *
radeon_user_framebuffer_create(struct drm_device * dev,struct drm_file * file_priv,struct drm_mode_fb_cmd2 * mode_cmd)1366 radeon_user_framebuffer_create(struct drm_device *dev,
1367 struct drm_file *file_priv,
1368 struct drm_mode_fb_cmd2 *mode_cmd)
1369 {
1370 struct drm_gem_object *obj;
1371 struct radeon_framebuffer *radeon_fb;
1372 int ret;
1373
1374 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1375 if (obj == NULL) {
1376 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1377 "can't create framebuffer\n", mode_cmd->handles[0]);
1378 return ERR_PTR(-ENOENT);
1379 }
1380
1381 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1382 if (obj->import_attach) {
1383 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
1384 return ERR_PTR(-EINVAL);
1385 }
1386
1387 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1388 if (radeon_fb == NULL) {
1389 drm_gem_object_unreference_unlocked(obj);
1390 return ERR_PTR(-ENOMEM);
1391 }
1392
1393 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1394 if (ret) {
1395 kfree(radeon_fb);
1396 drm_gem_object_unreference_unlocked(obj);
1397 return ERR_PTR(ret);
1398 }
1399
1400 return &radeon_fb->base;
1401 }
1402
radeon_output_poll_changed(struct drm_device * dev)1403 static void radeon_output_poll_changed(struct drm_device *dev)
1404 {
1405 struct radeon_device *rdev = dev->dev_private;
1406 radeon_fb_output_poll_changed(rdev);
1407 }
1408
1409 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1410 .fb_create = radeon_user_framebuffer_create,
1411 .output_poll_changed = radeon_output_poll_changed
1412 };
1413
1414 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1415 { { 0, "driver" },
1416 { 1, "bios" },
1417 };
1418
1419 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1420 { { TV_STD_NTSC, "ntsc" },
1421 { TV_STD_PAL, "pal" },
1422 { TV_STD_PAL_M, "pal-m" },
1423 { TV_STD_PAL_60, "pal-60" },
1424 { TV_STD_NTSC_J, "ntsc-j" },
1425 { TV_STD_SCART_PAL, "scart-pal" },
1426 { TV_STD_PAL_CN, "pal-cn" },
1427 { TV_STD_SECAM, "secam" },
1428 };
1429
1430 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1431 { { UNDERSCAN_OFF, "off" },
1432 { UNDERSCAN_ON, "on" },
1433 { UNDERSCAN_AUTO, "auto" },
1434 };
1435
1436 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1437 { { RADEON_AUDIO_DISABLE, "off" },
1438 { RADEON_AUDIO_ENABLE, "on" },
1439 { RADEON_AUDIO_AUTO, "auto" },
1440 };
1441
1442 /* XXX support different dither options? spatial, temporal, both, etc. */
1443 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1444 { { RADEON_FMT_DITHER_DISABLE, "off" },
1445 { RADEON_FMT_DITHER_ENABLE, "on" },
1446 };
1447
1448 static struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1449 { { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1450 { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1451 { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1452 { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1453 };
1454
radeon_modeset_create_props(struct radeon_device * rdev)1455 static int radeon_modeset_create_props(struct radeon_device *rdev)
1456 {
1457 int sz;
1458
1459 if (rdev->is_atom_bios) {
1460 rdev->mode_info.coherent_mode_property =
1461 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1462 if (!rdev->mode_info.coherent_mode_property)
1463 return -ENOMEM;
1464 }
1465
1466 if (!ASIC_IS_AVIVO(rdev)) {
1467 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1468 rdev->mode_info.tmds_pll_property =
1469 drm_property_create_enum(rdev->ddev, 0,
1470 "tmds_pll",
1471 radeon_tmds_pll_enum_list, sz);
1472 }
1473
1474 rdev->mode_info.load_detect_property =
1475 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1476 if (!rdev->mode_info.load_detect_property)
1477 return -ENOMEM;
1478
1479 drm_mode_create_scaling_mode_property(rdev->ddev);
1480
1481 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1482 rdev->mode_info.tv_std_property =
1483 drm_property_create_enum(rdev->ddev, 0,
1484 "tv standard",
1485 radeon_tv_std_enum_list, sz);
1486
1487 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1488 rdev->mode_info.underscan_property =
1489 drm_property_create_enum(rdev->ddev, 0,
1490 "underscan",
1491 radeon_underscan_enum_list, sz);
1492
1493 rdev->mode_info.underscan_hborder_property =
1494 drm_property_create_range(rdev->ddev, 0,
1495 "underscan hborder", 0, 128);
1496 if (!rdev->mode_info.underscan_hborder_property)
1497 return -ENOMEM;
1498
1499 rdev->mode_info.underscan_vborder_property =
1500 drm_property_create_range(rdev->ddev, 0,
1501 "underscan vborder", 0, 128);
1502 if (!rdev->mode_info.underscan_vborder_property)
1503 return -ENOMEM;
1504
1505 sz = ARRAY_SIZE(radeon_audio_enum_list);
1506 rdev->mode_info.audio_property =
1507 drm_property_create_enum(rdev->ddev, 0,
1508 "audio",
1509 radeon_audio_enum_list, sz);
1510
1511 sz = ARRAY_SIZE(radeon_dither_enum_list);
1512 rdev->mode_info.dither_property =
1513 drm_property_create_enum(rdev->ddev, 0,
1514 "dither",
1515 radeon_dither_enum_list, sz);
1516
1517 sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1518 rdev->mode_info.output_csc_property =
1519 drm_property_create_enum(rdev->ddev, 0,
1520 "output_csc",
1521 radeon_output_csc_enum_list, sz);
1522
1523 return 0;
1524 }
1525
radeon_update_display_priority(struct radeon_device * rdev)1526 void radeon_update_display_priority(struct radeon_device *rdev)
1527 {
1528 /* adjustment options for the display watermarks */
1529 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1530 /* set display priority to high for r3xx, rv515 chips
1531 * this avoids flickering due to underflow to the
1532 * display controllers during heavy acceleration.
1533 * Don't force high on rs4xx igp chips as it seems to
1534 * affect the sound card. See kernel bug 15982.
1535 */
1536 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1537 !(rdev->flags & RADEON_IS_IGP))
1538 rdev->disp_priority = 2;
1539 else
1540 rdev->disp_priority = 0;
1541 } else
1542 rdev->disp_priority = radeon_disp_priority;
1543
1544 }
1545
1546 /*
1547 * Allocate hdmi structs and determine register offsets
1548 */
radeon_afmt_init(struct radeon_device * rdev)1549 static void radeon_afmt_init(struct radeon_device *rdev)
1550 {
1551 int i;
1552
1553 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1554 rdev->mode_info.afmt[i] = NULL;
1555
1556 if (ASIC_IS_NODCE(rdev)) {
1557 /* nothing to do */
1558 } else if (ASIC_IS_DCE4(rdev)) {
1559 static uint32_t eg_offsets[] = {
1560 EVERGREEN_CRTC0_REGISTER_OFFSET,
1561 EVERGREEN_CRTC1_REGISTER_OFFSET,
1562 EVERGREEN_CRTC2_REGISTER_OFFSET,
1563 EVERGREEN_CRTC3_REGISTER_OFFSET,
1564 EVERGREEN_CRTC4_REGISTER_OFFSET,
1565 EVERGREEN_CRTC5_REGISTER_OFFSET,
1566 0x13830 - 0x7030,
1567 };
1568 int num_afmt;
1569
1570 /* DCE8 has 7 audio blocks tied to DIG encoders */
1571 /* DCE6 has 6 audio blocks tied to DIG encoders */
1572 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1573 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1574 if (ASIC_IS_DCE8(rdev))
1575 num_afmt = 7;
1576 else if (ASIC_IS_DCE6(rdev))
1577 num_afmt = 6;
1578 else if (ASIC_IS_DCE5(rdev))
1579 num_afmt = 6;
1580 else if (ASIC_IS_DCE41(rdev))
1581 num_afmt = 2;
1582 else /* DCE4 */
1583 num_afmt = 6;
1584
1585 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1586 for (i = 0; i < num_afmt; i++) {
1587 rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1588 if (rdev->mode_info.afmt[i]) {
1589 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1590 rdev->mode_info.afmt[i]->id = i;
1591 }
1592 }
1593 } else if (ASIC_IS_DCE3(rdev)) {
1594 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1595 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1596 if (rdev->mode_info.afmt[0]) {
1597 rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1598 rdev->mode_info.afmt[0]->id = 0;
1599 }
1600 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1601 if (rdev->mode_info.afmt[1]) {
1602 rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1603 rdev->mode_info.afmt[1]->id = 1;
1604 }
1605 } else if (ASIC_IS_DCE2(rdev)) {
1606 /* DCE2 has at least 1 routable audio block */
1607 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1608 if (rdev->mode_info.afmt[0]) {
1609 rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1610 rdev->mode_info.afmt[0]->id = 0;
1611 }
1612 /* r6xx has 2 routable audio blocks */
1613 if (rdev->family >= CHIP_R600) {
1614 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1615 if (rdev->mode_info.afmt[1]) {
1616 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1617 rdev->mode_info.afmt[1]->id = 1;
1618 }
1619 }
1620 }
1621 }
1622
radeon_afmt_fini(struct radeon_device * rdev)1623 static void radeon_afmt_fini(struct radeon_device *rdev)
1624 {
1625 int i;
1626
1627 for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1628 kfree(rdev->mode_info.afmt[i]);
1629 rdev->mode_info.afmt[i] = NULL;
1630 }
1631 }
1632
radeon_modeset_init(struct radeon_device * rdev)1633 int radeon_modeset_init(struct radeon_device *rdev)
1634 {
1635 int i;
1636 int ret;
1637
1638 drm_mode_config_init(rdev->ddev);
1639 rdev->mode_info.mode_config_initialized = true;
1640
1641 rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1642
1643 if (ASIC_IS_DCE5(rdev)) {
1644 rdev->ddev->mode_config.max_width = 16384;
1645 rdev->ddev->mode_config.max_height = 16384;
1646 } else if (ASIC_IS_AVIVO(rdev)) {
1647 rdev->ddev->mode_config.max_width = 8192;
1648 rdev->ddev->mode_config.max_height = 8192;
1649 } else {
1650 rdev->ddev->mode_config.max_width = 4096;
1651 rdev->ddev->mode_config.max_height = 4096;
1652 }
1653
1654 rdev->ddev->mode_config.preferred_depth = 24;
1655 rdev->ddev->mode_config.prefer_shadow = 1;
1656
1657 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1658
1659 ret = radeon_modeset_create_props(rdev);
1660 if (ret) {
1661 return ret;
1662 }
1663
1664 /* init i2c buses */
1665 radeon_i2c_init(rdev);
1666
1667 /* check combios for a valid hardcoded EDID - Sun servers */
1668 if (!rdev->is_atom_bios) {
1669 /* check for hardcoded EDID in BIOS */
1670 radeon_combios_check_hardcoded_edid(rdev);
1671 }
1672
1673 /* allocate crtcs */
1674 for (i = 0; i < rdev->num_crtc; i++) {
1675 radeon_crtc_init(rdev->ddev, i);
1676 }
1677
1678 /* okay we should have all the bios connectors */
1679 ret = radeon_setup_enc_conn(rdev->ddev);
1680 if (!ret) {
1681 return ret;
1682 }
1683
1684 /* init dig PHYs, disp eng pll */
1685 if (rdev->is_atom_bios) {
1686 radeon_atom_encoder_init(rdev);
1687 radeon_atom_disp_eng_pll_init(rdev);
1688 }
1689
1690 /* initialize hpd */
1691 radeon_hpd_init(rdev);
1692
1693 /* setup afmt */
1694 radeon_afmt_init(rdev);
1695
1696 radeon_fbdev_init(rdev);
1697 drm_kms_helper_poll_init(rdev->ddev);
1698
1699 /* do pm late init */
1700 ret = radeon_pm_late_init(rdev);
1701
1702 return 0;
1703 }
1704
radeon_modeset_fini(struct radeon_device * rdev)1705 void radeon_modeset_fini(struct radeon_device *rdev)
1706 {
1707 radeon_fbdev_fini(rdev);
1708 kfree(rdev->mode_info.bios_hardcoded_edid);
1709
1710 if (rdev->mode_info.mode_config_initialized) {
1711 radeon_afmt_fini(rdev);
1712 drm_kms_helper_poll_fini(rdev->ddev);
1713 radeon_hpd_fini(rdev);
1714 drm_mode_config_cleanup(rdev->ddev);
1715 rdev->mode_info.mode_config_initialized = false;
1716 }
1717 /* free i2c buses */
1718 radeon_i2c_fini(rdev);
1719 }
1720
is_hdtv_mode(const struct drm_display_mode * mode)1721 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1722 {
1723 /* try and guess if this is a tv or a monitor */
1724 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1725 (mode->vdisplay == 576) || /* 576p */
1726 (mode->vdisplay == 720) || /* 720p */
1727 (mode->vdisplay == 1080)) /* 1080p */
1728 return true;
1729 else
1730 return false;
1731 }
1732
radeon_crtc_scaling_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1733 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1734 const struct drm_display_mode *mode,
1735 struct drm_display_mode *adjusted_mode)
1736 {
1737 struct drm_device *dev = crtc->dev;
1738 struct radeon_device *rdev = dev->dev_private;
1739 struct drm_encoder *encoder;
1740 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1741 struct radeon_encoder *radeon_encoder;
1742 struct drm_connector *connector;
1743 struct radeon_connector *radeon_connector;
1744 bool first = true;
1745 u32 src_v = 1, dst_v = 1;
1746 u32 src_h = 1, dst_h = 1;
1747
1748 radeon_crtc->h_border = 0;
1749 radeon_crtc->v_border = 0;
1750
1751 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1752 if (encoder->crtc != crtc)
1753 continue;
1754 radeon_encoder = to_radeon_encoder(encoder);
1755 connector = radeon_get_connector_for_encoder(encoder);
1756 radeon_connector = to_radeon_connector(connector);
1757
1758 if (first) {
1759 /* set scaling */
1760 if (radeon_encoder->rmx_type == RMX_OFF)
1761 radeon_crtc->rmx_type = RMX_OFF;
1762 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1763 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1764 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1765 else
1766 radeon_crtc->rmx_type = RMX_OFF;
1767 /* copy native mode */
1768 memcpy(&radeon_crtc->native_mode,
1769 &radeon_encoder->native_mode,
1770 sizeof(struct drm_display_mode));
1771 src_v = crtc->mode.vdisplay;
1772 dst_v = radeon_crtc->native_mode.vdisplay;
1773 src_h = crtc->mode.hdisplay;
1774 dst_h = radeon_crtc->native_mode.hdisplay;
1775
1776 /* fix up for overscan on hdmi */
1777 if (ASIC_IS_AVIVO(rdev) &&
1778 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1779 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1780 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1781 drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1782 is_hdtv_mode(mode)))) {
1783 if (radeon_encoder->underscan_hborder != 0)
1784 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1785 else
1786 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1787 if (radeon_encoder->underscan_vborder != 0)
1788 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1789 else
1790 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1791 radeon_crtc->rmx_type = RMX_FULL;
1792 src_v = crtc->mode.vdisplay;
1793 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1794 src_h = crtc->mode.hdisplay;
1795 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1796 }
1797 first = false;
1798 } else {
1799 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1800 /* WARNING: Right now this can't happen but
1801 * in the future we need to check that scaling
1802 * are consistent across different encoder
1803 * (ie all encoder can work with the same
1804 * scaling).
1805 */
1806 DRM_ERROR("Scaling not consistent across encoder.\n");
1807 return false;
1808 }
1809 }
1810 }
1811 if (radeon_crtc->rmx_type != RMX_OFF) {
1812 fixed20_12 a, b;
1813 a.full = dfixed_const(src_v);
1814 b.full = dfixed_const(dst_v);
1815 radeon_crtc->vsc.full = dfixed_div(a, b);
1816 a.full = dfixed_const(src_h);
1817 b.full = dfixed_const(dst_h);
1818 radeon_crtc->hsc.full = dfixed_div(a, b);
1819 } else {
1820 radeon_crtc->vsc.full = dfixed_const(1);
1821 radeon_crtc->hsc.full = dfixed_const(1);
1822 }
1823 return true;
1824 }
1825
1826 /*
1827 * Retrieve current video scanout position of crtc on a given gpu, and
1828 * an optional accurate timestamp of when query happened.
1829 *
1830 * \param dev Device to query.
1831 * \param crtc Crtc to query.
1832 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1833 * For driver internal use only also supports these flags:
1834 *
1835 * USE_REAL_VBLANKSTART to use the real start of vblank instead
1836 * of a fudged earlier start of vblank.
1837 *
1838 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
1839 * fudged earlier start of vblank in *vpos and the distance
1840 * to true start of vblank in *hpos.
1841 *
1842 * \param *vpos Location where vertical scanout position should be stored.
1843 * \param *hpos Location where horizontal scanout position should go.
1844 * \param *stime Target location for timestamp taken immediately before
1845 * scanout position query. Can be NULL to skip timestamp.
1846 * \param *etime Target location for timestamp taken immediately after
1847 * scanout position query. Can be NULL to skip timestamp.
1848 *
1849 * Returns vpos as a positive number while in active scanout area.
1850 * Returns vpos as a negative number inside vblank, counting the number
1851 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1852 * until start of active scanout / end of vblank."
1853 *
1854 * \return Flags, or'ed together as follows:
1855 *
1856 * DRM_SCANOUTPOS_VALID = Query successful.
1857 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1858 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1859 * this flag means that returned position may be offset by a constant but
1860 * unknown small number of scanlines wrt. real scanout position.
1861 *
1862 */
radeon_get_crtc_scanoutpos(struct drm_device * dev,unsigned int pipe,unsigned int flags,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)1863 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1864 unsigned int flags, int *vpos, int *hpos,
1865 ktime_t *stime, ktime_t *etime,
1866 const struct drm_display_mode *mode)
1867 {
1868 u32 stat_crtc = 0, vbl = 0, position = 0;
1869 int vbl_start, vbl_end, vtotal, ret = 0;
1870 bool in_vbl = true;
1871
1872 struct radeon_device *rdev = dev->dev_private;
1873
1874 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1875
1876 /* Get optional system timestamp before query. */
1877 if (stime)
1878 *stime = ktime_get();
1879
1880 if (ASIC_IS_DCE4(rdev)) {
1881 if (pipe == 0) {
1882 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1883 EVERGREEN_CRTC0_REGISTER_OFFSET);
1884 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1885 EVERGREEN_CRTC0_REGISTER_OFFSET);
1886 ret |= DRM_SCANOUTPOS_VALID;
1887 }
1888 if (pipe == 1) {
1889 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1890 EVERGREEN_CRTC1_REGISTER_OFFSET);
1891 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1892 EVERGREEN_CRTC1_REGISTER_OFFSET);
1893 ret |= DRM_SCANOUTPOS_VALID;
1894 }
1895 if (pipe == 2) {
1896 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1897 EVERGREEN_CRTC2_REGISTER_OFFSET);
1898 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1899 EVERGREEN_CRTC2_REGISTER_OFFSET);
1900 ret |= DRM_SCANOUTPOS_VALID;
1901 }
1902 if (pipe == 3) {
1903 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1904 EVERGREEN_CRTC3_REGISTER_OFFSET);
1905 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1906 EVERGREEN_CRTC3_REGISTER_OFFSET);
1907 ret |= DRM_SCANOUTPOS_VALID;
1908 }
1909 if (pipe == 4) {
1910 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1911 EVERGREEN_CRTC4_REGISTER_OFFSET);
1912 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1913 EVERGREEN_CRTC4_REGISTER_OFFSET);
1914 ret |= DRM_SCANOUTPOS_VALID;
1915 }
1916 if (pipe == 5) {
1917 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1918 EVERGREEN_CRTC5_REGISTER_OFFSET);
1919 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1920 EVERGREEN_CRTC5_REGISTER_OFFSET);
1921 ret |= DRM_SCANOUTPOS_VALID;
1922 }
1923 } else if (ASIC_IS_AVIVO(rdev)) {
1924 if (pipe == 0) {
1925 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1926 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1927 ret |= DRM_SCANOUTPOS_VALID;
1928 }
1929 if (pipe == 1) {
1930 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1931 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1932 ret |= DRM_SCANOUTPOS_VALID;
1933 }
1934 } else {
1935 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1936 if (pipe == 0) {
1937 /* Assume vbl_end == 0, get vbl_start from
1938 * upper 16 bits.
1939 */
1940 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1941 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1942 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1943 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1944 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1945 if (!(stat_crtc & 1))
1946 in_vbl = false;
1947
1948 ret |= DRM_SCANOUTPOS_VALID;
1949 }
1950 if (pipe == 1) {
1951 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1952 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1953 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1954 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1955 if (!(stat_crtc & 1))
1956 in_vbl = false;
1957
1958 ret |= DRM_SCANOUTPOS_VALID;
1959 }
1960 }
1961
1962 /* Get optional system timestamp after query. */
1963 if (etime)
1964 *etime = ktime_get();
1965
1966 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1967
1968 /* Decode into vertical and horizontal scanout position. */
1969 *vpos = position & 0x1fff;
1970 *hpos = (position >> 16) & 0x1fff;
1971
1972 /* Valid vblank area boundaries from gpu retrieved? */
1973 if (vbl > 0) {
1974 /* Yes: Decode. */
1975 ret |= DRM_SCANOUTPOS_ACCURATE;
1976 vbl_start = vbl & 0x1fff;
1977 vbl_end = (vbl >> 16) & 0x1fff;
1978 }
1979 else {
1980 /* No: Fake something reasonable which gives at least ok results. */
1981 vbl_start = mode->crtc_vdisplay;
1982 vbl_end = 0;
1983 }
1984
1985 /* Called from driver internal vblank counter query code? */
1986 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1987 /* Caller wants distance from real vbl_start in *hpos */
1988 *hpos = *vpos - vbl_start;
1989 }
1990
1991 /* Fudge vblank to start a few scanlines earlier to handle the
1992 * problem that vblank irqs fire a few scanlines before start
1993 * of vblank. Some driver internal callers need the true vblank
1994 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1995 *
1996 * The cause of the "early" vblank irq is that the irq is triggered
1997 * by the line buffer logic when the line buffer read position enters
1998 * the vblank, whereas our crtc scanout position naturally lags the
1999 * line buffer read position.
2000 */
2001 if (!(flags & USE_REAL_VBLANKSTART))
2002 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
2003
2004 /* Test scanout position against vblank region. */
2005 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
2006 in_vbl = false;
2007
2008 /* In vblank? */
2009 if (in_vbl)
2010 ret |= DRM_SCANOUTPOS_IN_VBLANK;
2011
2012 /* Called from driver internal vblank counter query code? */
2013 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
2014 /* Caller wants distance from fudged earlier vbl_start */
2015 *vpos -= vbl_start;
2016 return ret;
2017 }
2018
2019 /* Check if inside vblank area and apply corrective offsets:
2020 * vpos will then be >=0 in video scanout area, but negative
2021 * within vblank area, counting down the number of lines until
2022 * start of scanout.
2023 */
2024
2025 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
2026 if (in_vbl && (*vpos >= vbl_start)) {
2027 vtotal = mode->crtc_vtotal;
2028 *vpos = *vpos - vtotal;
2029 }
2030
2031 /* Correct for shifted end of vbl at vbl_end. */
2032 *vpos = *vpos - vbl_end;
2033
2034 return ret;
2035 }
2036