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1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <drm/drmP.h>
29 #include "radeon.h"
30 #include <drm/radeon_drm.h>
31 #include "radeon_asic.h"
32 
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
35 #include <linux/pm_runtime.h>
36 
37 #include "radeon_kfd.h"
38 
39 #if defined(CONFIG_VGA_SWITCHEROO)
40 bool radeon_has_atpx(void);
41 #else
radeon_has_atpx(void)42 static inline bool radeon_has_atpx(void) { return false; }
43 #endif
44 
45 /**
46  * radeon_driver_unload_kms - Main unload function for KMS.
47  *
48  * @dev: drm dev pointer
49  *
50  * This is the main unload function for KMS (all asics).
51  * It calls radeon_modeset_fini() to tear down the
52  * displays, and radeon_device_fini() to tear down
53  * the rest of the device (CP, writeback, etc.).
54  * Returns 0 on success.
55  */
radeon_driver_unload_kms(struct drm_device * dev)56 int radeon_driver_unload_kms(struct drm_device *dev)
57 {
58 	struct radeon_device *rdev = dev->dev_private;
59 
60 	if (rdev == NULL)
61 		return 0;
62 
63 	if (rdev->rmmio == NULL)
64 		goto done_free;
65 
66 	pm_runtime_get_sync(dev->dev);
67 
68 	radeon_kfd_device_fini(rdev);
69 
70 	radeon_acpi_fini(rdev);
71 
72 	radeon_modeset_fini(rdev);
73 	radeon_device_fini(rdev);
74 
75 done_free:
76 	kfree(rdev);
77 	dev->dev_private = NULL;
78 	return 0;
79 }
80 
81 /**
82  * radeon_driver_load_kms - Main load function for KMS.
83  *
84  * @dev: drm dev pointer
85  * @flags: device flags
86  *
87  * This is the main load function for KMS (all asics).
88  * It calls radeon_device_init() to set up the non-display
89  * parts of the chip (asic init, CP, writeback, etc.), and
90  * radeon_modeset_init() to set up the display parts
91  * (crtcs, encoders, hotplug detect, etc.).
92  * Returns 0 on success, error on failure.
93  */
radeon_driver_load_kms(struct drm_device * dev,unsigned long flags)94 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
95 {
96 	struct radeon_device *rdev;
97 	int r, acpi_status;
98 
99 	rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
100 	if (rdev == NULL) {
101 		return -ENOMEM;
102 	}
103 	dev->dev_private = (void *)rdev;
104 
105 	/* update BUS flag */
106 	if (drm_pci_device_is_agp(dev)) {
107 		flags |= RADEON_IS_AGP;
108 	} else if (pci_is_pcie(dev->pdev)) {
109 		flags |= RADEON_IS_PCIE;
110 	} else {
111 		flags |= RADEON_IS_PCI;
112 	}
113 
114 	if ((radeon_runtime_pm != 0) &&
115 	    radeon_has_atpx() &&
116 	    ((flags & RADEON_IS_IGP) == 0))
117 		flags |= RADEON_IS_PX;
118 
119 	/* radeon_device_init should report only fatal error
120 	 * like memory allocation failure or iomapping failure,
121 	 * or memory manager initialization failure, it must
122 	 * properly initialize the GPU MC controller and permit
123 	 * VRAM allocation
124 	 */
125 	r = radeon_device_init(rdev, dev, dev->pdev, flags);
126 	if (r) {
127 		dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
128 		goto out;
129 	}
130 
131 	/* Again modeset_init should fail only on fatal error
132 	 * otherwise it should provide enough functionalities
133 	 * for shadowfb to run
134 	 */
135 	r = radeon_modeset_init(rdev);
136 	if (r)
137 		dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
138 
139 	/* Call ACPI methods: require modeset init
140 	 * but failure is not fatal
141 	 */
142 	if (!r) {
143 		acpi_status = radeon_acpi_init(rdev);
144 		if (acpi_status)
145 		dev_dbg(&dev->pdev->dev,
146 				"Error during ACPI methods call\n");
147 	}
148 
149 	radeon_kfd_device_probe(rdev);
150 	radeon_kfd_device_init(rdev);
151 
152 	if (radeon_is_px(dev)) {
153 		pm_runtime_use_autosuspend(dev->dev);
154 		pm_runtime_set_autosuspend_delay(dev->dev, 5000);
155 		pm_runtime_set_active(dev->dev);
156 		pm_runtime_allow(dev->dev);
157 		pm_runtime_mark_last_busy(dev->dev);
158 		pm_runtime_put_autosuspend(dev->dev);
159 	}
160 
161 out:
162 	if (r)
163 		radeon_driver_unload_kms(dev);
164 
165 
166 	return r;
167 }
168 
169 /**
170  * radeon_set_filp_rights - Set filp right.
171  *
172  * @dev: drm dev pointer
173  * @owner: drm file
174  * @applier: drm file
175  * @value: value
176  *
177  * Sets the filp rights for the device (all asics).
178  */
radeon_set_filp_rights(struct drm_device * dev,struct drm_file ** owner,struct drm_file * applier,uint32_t * value)179 static void radeon_set_filp_rights(struct drm_device *dev,
180 				   struct drm_file **owner,
181 				   struct drm_file *applier,
182 				   uint32_t *value)
183 {
184 	struct radeon_device *rdev = dev->dev_private;
185 
186 	mutex_lock(&rdev->gem.mutex);
187 	if (*value == 1) {
188 		/* wants rights */
189 		if (!*owner)
190 			*owner = applier;
191 	} else if (*value == 0) {
192 		/* revokes rights */
193 		if (*owner == applier)
194 			*owner = NULL;
195 	}
196 	*value = *owner == applier ? 1 : 0;
197 	mutex_unlock(&rdev->gem.mutex);
198 }
199 
200 /*
201  * Userspace get information ioctl
202  */
203 /**
204  * radeon_info_ioctl - answer a device specific request.
205  *
206  * @rdev: radeon device pointer
207  * @data: request object
208  * @filp: drm filp
209  *
210  * This function is used to pass device specific parameters to the userspace
211  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
212  * etc. (all asics).
213  * Returns 0 on success, -EINVAL on failure.
214  */
radeon_info_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)215 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
216 {
217 	struct radeon_device *rdev = dev->dev_private;
218 	struct drm_radeon_info *info = data;
219 	struct radeon_mode_info *minfo = &rdev->mode_info;
220 	uint32_t *value, value_tmp, *value_ptr, value_size;
221 	uint64_t value64;
222 	struct drm_crtc *crtc;
223 	int i, found;
224 
225 	value_ptr = (uint32_t *)((unsigned long)info->value);
226 	value = &value_tmp;
227 	value_size = sizeof(uint32_t);
228 
229 	switch (info->request) {
230 	case RADEON_INFO_DEVICE_ID:
231 		*value = dev->pdev->device;
232 		break;
233 	case RADEON_INFO_NUM_GB_PIPES:
234 		*value = rdev->num_gb_pipes;
235 		break;
236 	case RADEON_INFO_NUM_Z_PIPES:
237 		*value = rdev->num_z_pipes;
238 		break;
239 	case RADEON_INFO_ACCEL_WORKING:
240 		/* xf86-video-ati 6.13.0 relies on this being false for evergreen */
241 		if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
242 			*value = false;
243 		else
244 			*value = rdev->accel_working;
245 		break;
246 	case RADEON_INFO_CRTC_FROM_ID:
247 		if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
248 			DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
249 			return -EFAULT;
250 		}
251 		for (i = 0, found = 0; i < rdev->num_crtc; i++) {
252 			crtc = (struct drm_crtc *)minfo->crtcs[i];
253 			if (crtc && crtc->base.id == *value) {
254 				struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
255 				*value = radeon_crtc->crtc_id;
256 				found = 1;
257 				break;
258 			}
259 		}
260 		if (!found) {
261 			DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
262 			return -EINVAL;
263 		}
264 		break;
265 	case RADEON_INFO_ACCEL_WORKING2:
266 		if (rdev->family == CHIP_HAWAII) {
267 			if (rdev->accel_working) {
268 				if (rdev->new_fw)
269 					*value = 3;
270 				else
271 					*value = 2;
272 			} else {
273 				*value = 0;
274 			}
275 		} else {
276 			*value = rdev->accel_working;
277 		}
278 		break;
279 	case RADEON_INFO_TILING_CONFIG:
280 		if (rdev->family >= CHIP_BONAIRE)
281 			*value = rdev->config.cik.tile_config;
282 		else if (rdev->family >= CHIP_TAHITI)
283 			*value = rdev->config.si.tile_config;
284 		else if (rdev->family >= CHIP_CAYMAN)
285 			*value = rdev->config.cayman.tile_config;
286 		else if (rdev->family >= CHIP_CEDAR)
287 			*value = rdev->config.evergreen.tile_config;
288 		else if (rdev->family >= CHIP_RV770)
289 			*value = rdev->config.rv770.tile_config;
290 		else if (rdev->family >= CHIP_R600)
291 			*value = rdev->config.r600.tile_config;
292 		else {
293 			DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
294 			return -EINVAL;
295 		}
296 		break;
297 	case RADEON_INFO_WANT_HYPERZ:
298 		/* The "value" here is both an input and output parameter.
299 		 * If the input value is 1, filp requests hyper-z access.
300 		 * If the input value is 0, filp revokes its hyper-z access.
301 		 *
302 		 * When returning, the value is 1 if filp owns hyper-z access,
303 		 * 0 otherwise. */
304 		if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
305 			DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
306 			return -EFAULT;
307 		}
308 		if (*value >= 2) {
309 			DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
310 			return -EINVAL;
311 		}
312 		radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
313 		break;
314 	case RADEON_INFO_WANT_CMASK:
315 		/* The same logic as Hyper-Z. */
316 		if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
317 			DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
318 			return -EFAULT;
319 		}
320 		if (*value >= 2) {
321 			DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
322 			return -EINVAL;
323 		}
324 		radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
325 		break;
326 	case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
327 		/* return clock value in KHz */
328 		if (rdev->asic->get_xclk)
329 			*value = radeon_get_xclk(rdev) * 10;
330 		else
331 			*value = rdev->clock.spll.reference_freq * 10;
332 		break;
333 	case RADEON_INFO_NUM_BACKENDS:
334 		if (rdev->family >= CHIP_BONAIRE)
335 			*value = rdev->config.cik.max_backends_per_se *
336 				rdev->config.cik.max_shader_engines;
337 		else if (rdev->family >= CHIP_TAHITI)
338 			*value = rdev->config.si.max_backends_per_se *
339 				rdev->config.si.max_shader_engines;
340 		else if (rdev->family >= CHIP_CAYMAN)
341 			*value = rdev->config.cayman.max_backends_per_se *
342 				rdev->config.cayman.max_shader_engines;
343 		else if (rdev->family >= CHIP_CEDAR)
344 			*value = rdev->config.evergreen.max_backends;
345 		else if (rdev->family >= CHIP_RV770)
346 			*value = rdev->config.rv770.max_backends;
347 		else if (rdev->family >= CHIP_R600)
348 			*value = rdev->config.r600.max_backends;
349 		else {
350 			return -EINVAL;
351 		}
352 		break;
353 	case RADEON_INFO_NUM_TILE_PIPES:
354 		if (rdev->family >= CHIP_BONAIRE)
355 			*value = rdev->config.cik.max_tile_pipes;
356 		else if (rdev->family >= CHIP_TAHITI)
357 			*value = rdev->config.si.max_tile_pipes;
358 		else if (rdev->family >= CHIP_CAYMAN)
359 			*value = rdev->config.cayman.max_tile_pipes;
360 		else if (rdev->family >= CHIP_CEDAR)
361 			*value = rdev->config.evergreen.max_tile_pipes;
362 		else if (rdev->family >= CHIP_RV770)
363 			*value = rdev->config.rv770.max_tile_pipes;
364 		else if (rdev->family >= CHIP_R600)
365 			*value = rdev->config.r600.max_tile_pipes;
366 		else {
367 			return -EINVAL;
368 		}
369 		break;
370 	case RADEON_INFO_FUSION_GART_WORKING:
371 		*value = 1;
372 		break;
373 	case RADEON_INFO_BACKEND_MAP:
374 		if (rdev->family >= CHIP_BONAIRE)
375 			*value = rdev->config.cik.backend_map;
376 		else if (rdev->family >= CHIP_TAHITI)
377 			*value = rdev->config.si.backend_map;
378 		else if (rdev->family >= CHIP_CAYMAN)
379 			*value = rdev->config.cayman.backend_map;
380 		else if (rdev->family >= CHIP_CEDAR)
381 			*value = rdev->config.evergreen.backend_map;
382 		else if (rdev->family >= CHIP_RV770)
383 			*value = rdev->config.rv770.backend_map;
384 		else if (rdev->family >= CHIP_R600)
385 			*value = rdev->config.r600.backend_map;
386 		else {
387 			return -EINVAL;
388 		}
389 		break;
390 	case RADEON_INFO_VA_START:
391 		/* this is where we report if vm is supported or not */
392 		if (rdev->family < CHIP_CAYMAN)
393 			return -EINVAL;
394 		*value = RADEON_VA_RESERVED_SIZE;
395 		break;
396 	case RADEON_INFO_IB_VM_MAX_SIZE:
397 		/* this is where we report if vm is supported or not */
398 		if (rdev->family < CHIP_CAYMAN)
399 			return -EINVAL;
400 		*value = RADEON_IB_VM_MAX_SIZE;
401 		break;
402 	case RADEON_INFO_MAX_PIPES:
403 		if (rdev->family >= CHIP_BONAIRE)
404 			*value = rdev->config.cik.max_cu_per_sh;
405 		else if (rdev->family >= CHIP_TAHITI)
406 			*value = rdev->config.si.max_cu_per_sh;
407 		else if (rdev->family >= CHIP_CAYMAN)
408 			*value = rdev->config.cayman.max_pipes_per_simd;
409 		else if (rdev->family >= CHIP_CEDAR)
410 			*value = rdev->config.evergreen.max_pipes;
411 		else if (rdev->family >= CHIP_RV770)
412 			*value = rdev->config.rv770.max_pipes;
413 		else if (rdev->family >= CHIP_R600)
414 			*value = rdev->config.r600.max_pipes;
415 		else {
416 			return -EINVAL;
417 		}
418 		break;
419 	case RADEON_INFO_TIMESTAMP:
420 		if (rdev->family < CHIP_R600) {
421 			DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
422 			return -EINVAL;
423 		}
424 		value = (uint32_t*)&value64;
425 		value_size = sizeof(uint64_t);
426 		value64 = radeon_get_gpu_clock_counter(rdev);
427 		break;
428 	case RADEON_INFO_MAX_SE:
429 		if (rdev->family >= CHIP_BONAIRE)
430 			*value = rdev->config.cik.max_shader_engines;
431 		else if (rdev->family >= CHIP_TAHITI)
432 			*value = rdev->config.si.max_shader_engines;
433 		else if (rdev->family >= CHIP_CAYMAN)
434 			*value = rdev->config.cayman.max_shader_engines;
435 		else if (rdev->family >= CHIP_CEDAR)
436 			*value = rdev->config.evergreen.num_ses;
437 		else
438 			*value = 1;
439 		break;
440 	case RADEON_INFO_MAX_SH_PER_SE:
441 		if (rdev->family >= CHIP_BONAIRE)
442 			*value = rdev->config.cik.max_sh_per_se;
443 		else if (rdev->family >= CHIP_TAHITI)
444 			*value = rdev->config.si.max_sh_per_se;
445 		else
446 			return -EINVAL;
447 		break;
448 	case RADEON_INFO_FASTFB_WORKING:
449 		*value = rdev->fastfb_working;
450 		break;
451 	case RADEON_INFO_RING_WORKING:
452 		if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
453 			DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
454 			return -EFAULT;
455 		}
456 		switch (*value) {
457 		case RADEON_CS_RING_GFX:
458 		case RADEON_CS_RING_COMPUTE:
459 			*value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
460 			break;
461 		case RADEON_CS_RING_DMA:
462 			*value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
463 			*value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
464 			break;
465 		case RADEON_CS_RING_UVD:
466 			*value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
467 			break;
468 		case RADEON_CS_RING_VCE:
469 			*value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
470 			break;
471 		default:
472 			return -EINVAL;
473 		}
474 		break;
475 	case RADEON_INFO_SI_TILE_MODE_ARRAY:
476 		if (rdev->family >= CHIP_BONAIRE) {
477 			value = rdev->config.cik.tile_mode_array;
478 			value_size = sizeof(uint32_t)*32;
479 		} else if (rdev->family >= CHIP_TAHITI) {
480 			value = rdev->config.si.tile_mode_array;
481 			value_size = sizeof(uint32_t)*32;
482 		} else {
483 			DRM_DEBUG_KMS("tile mode array is si+ only!\n");
484 			return -EINVAL;
485 		}
486 		break;
487 	case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
488 		if (rdev->family >= CHIP_BONAIRE) {
489 			value = rdev->config.cik.macrotile_mode_array;
490 			value_size = sizeof(uint32_t)*16;
491 		} else {
492 			DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
493 			return -EINVAL;
494 		}
495 		break;
496 	case RADEON_INFO_SI_CP_DMA_COMPUTE:
497 		*value = 1;
498 		break;
499 	case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
500 		if (rdev->family >= CHIP_BONAIRE) {
501 			*value = rdev->config.cik.backend_enable_mask;
502 		} else if (rdev->family >= CHIP_TAHITI) {
503 			*value = rdev->config.si.backend_enable_mask;
504 		} else {
505 			DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
506 			return -EINVAL;
507 		}
508 		break;
509 	case RADEON_INFO_MAX_SCLK:
510 		if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
511 		    rdev->pm.dpm_enabled)
512 			*value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
513 		else
514 			*value = rdev->pm.default_sclk * 10;
515 		break;
516 	case RADEON_INFO_VCE_FW_VERSION:
517 		*value = rdev->vce.fw_version;
518 		break;
519 	case RADEON_INFO_VCE_FB_VERSION:
520 		*value = rdev->vce.fb_version;
521 		break;
522 	case RADEON_INFO_NUM_BYTES_MOVED:
523 		value = (uint32_t*)&value64;
524 		value_size = sizeof(uint64_t);
525 		value64 = atomic64_read(&rdev->num_bytes_moved);
526 		break;
527 	case RADEON_INFO_VRAM_USAGE:
528 		value = (uint32_t*)&value64;
529 		value_size = sizeof(uint64_t);
530 		value64 = atomic64_read(&rdev->vram_usage);
531 		break;
532 	case RADEON_INFO_GTT_USAGE:
533 		value = (uint32_t*)&value64;
534 		value_size = sizeof(uint64_t);
535 		value64 = atomic64_read(&rdev->gtt_usage);
536 		break;
537 	case RADEON_INFO_ACTIVE_CU_COUNT:
538 		if (rdev->family >= CHIP_BONAIRE)
539 			*value = rdev->config.cik.active_cus;
540 		else if (rdev->family >= CHIP_TAHITI)
541 			*value = rdev->config.si.active_cus;
542 		else if (rdev->family >= CHIP_CAYMAN)
543 			*value = rdev->config.cayman.active_simds;
544 		else if (rdev->family >= CHIP_CEDAR)
545 			*value = rdev->config.evergreen.active_simds;
546 		else if (rdev->family >= CHIP_RV770)
547 			*value = rdev->config.rv770.active_simds;
548 		else if (rdev->family >= CHIP_R600)
549 			*value = rdev->config.r600.active_simds;
550 		else
551 			*value = 1;
552 		break;
553 	case RADEON_INFO_CURRENT_GPU_TEMP:
554 		/* get temperature in millidegrees C */
555 		if (rdev->asic->pm.get_temperature)
556 			*value = radeon_get_temperature(rdev);
557 		else
558 			*value = 0;
559 		break;
560 	case RADEON_INFO_CURRENT_GPU_SCLK:
561 		/* get sclk in Mhz */
562 		if (rdev->pm.dpm_enabled)
563 			*value = radeon_dpm_get_current_sclk(rdev) / 100;
564 		else
565 			*value = rdev->pm.current_sclk / 100;
566 		break;
567 	case RADEON_INFO_CURRENT_GPU_MCLK:
568 		/* get mclk in Mhz */
569 		if (rdev->pm.dpm_enabled)
570 			*value = radeon_dpm_get_current_mclk(rdev) / 100;
571 		else
572 			*value = rdev->pm.current_mclk / 100;
573 		break;
574 	case RADEON_INFO_READ_REG:
575 		if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
576 			DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
577 			return -EFAULT;
578 		}
579 		if (radeon_get_allowed_info_register(rdev, *value, value))
580 			return -EINVAL;
581 		break;
582 	case RADEON_INFO_VA_UNMAP_WORKING:
583 		*value = true;
584 		break;
585 	case RADEON_INFO_GPU_RESET_COUNTER:
586 		*value = atomic_read(&rdev->gpu_reset_counter);
587 		break;
588 	default:
589 		DRM_DEBUG_KMS("Invalid request %d\n", info->request);
590 		return -EINVAL;
591 	}
592 	if (copy_to_user(value_ptr, (char*)value, value_size)) {
593 		DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
594 		return -EFAULT;
595 	}
596 	return 0;
597 }
598 
599 
600 /*
601  * Outdated mess for old drm with Xorg being in charge (void function now).
602  */
603 /**
604  * radeon_driver_lastclose_kms - drm callback for last close
605  *
606  * @dev: drm dev pointer
607  *
608  * Switch vga_switcheroo state after last close (all asics).
609  */
radeon_driver_lastclose_kms(struct drm_device * dev)610 void radeon_driver_lastclose_kms(struct drm_device *dev)
611 {
612 	struct radeon_device *rdev = dev->dev_private;
613 
614 	radeon_fbdev_restore_mode(rdev);
615 	vga_switcheroo_process_delayed_switch();
616 }
617 
618 /**
619  * radeon_driver_open_kms - drm callback for open
620  *
621  * @dev: drm dev pointer
622  * @file_priv: drm file
623  *
624  * On device open, init vm on cayman+ (all asics).
625  * Returns 0 on success, error on failure.
626  */
radeon_driver_open_kms(struct drm_device * dev,struct drm_file * file_priv)627 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
628 {
629 	struct radeon_device *rdev = dev->dev_private;
630 	int r;
631 
632 	file_priv->driver_priv = NULL;
633 
634 	r = pm_runtime_get_sync(dev->dev);
635 	if (r < 0) {
636 		pm_runtime_put_autosuspend(dev->dev);
637 		return r;
638 	}
639 
640 	/* new gpu have virtual address space support */
641 	if (rdev->family >= CHIP_CAYMAN) {
642 		struct radeon_fpriv *fpriv;
643 		struct radeon_vm *vm;
644 		int r;
645 
646 		fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
647 		if (unlikely(!fpriv)) {
648 			return -ENOMEM;
649 		}
650 
651 		if (rdev->accel_working) {
652 			vm = &fpriv->vm;
653 			r = radeon_vm_init(rdev, vm);
654 			if (r) {
655 				kfree(fpriv);
656 				return r;
657 			}
658 
659 			r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
660 			if (r) {
661 				radeon_vm_fini(rdev, vm);
662 				kfree(fpriv);
663 				return r;
664 			}
665 
666 			/* map the ib pool buffer read only into
667 			 * virtual address space */
668 			vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
669 							rdev->ring_tmp_bo.bo);
670 			r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
671 						  RADEON_VA_IB_OFFSET,
672 						  RADEON_VM_PAGE_READABLE |
673 						  RADEON_VM_PAGE_SNOOPED);
674 			if (r) {
675 				radeon_vm_fini(rdev, vm);
676 				kfree(fpriv);
677 				return r;
678 			}
679 		}
680 		file_priv->driver_priv = fpriv;
681 	}
682 
683 	pm_runtime_mark_last_busy(dev->dev);
684 	pm_runtime_put_autosuspend(dev->dev);
685 	return 0;
686 }
687 
688 /**
689  * radeon_driver_postclose_kms - drm callback for post close
690  *
691  * @dev: drm dev pointer
692  * @file_priv: drm file
693  *
694  * On device post close, tear down vm on cayman+ (all asics).
695  */
radeon_driver_postclose_kms(struct drm_device * dev,struct drm_file * file_priv)696 void radeon_driver_postclose_kms(struct drm_device *dev,
697 				 struct drm_file *file_priv)
698 {
699 	struct radeon_device *rdev = dev->dev_private;
700 
701 	/* new gpu have virtual address space support */
702 	if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
703 		struct radeon_fpriv *fpriv = file_priv->driver_priv;
704 		struct radeon_vm *vm = &fpriv->vm;
705 		int r;
706 
707 		if (rdev->accel_working) {
708 			r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
709 			if (!r) {
710 				if (vm->ib_bo_va)
711 					radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
712 				radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
713 			}
714 			radeon_vm_fini(rdev, vm);
715 		}
716 
717 		kfree(fpriv);
718 		file_priv->driver_priv = NULL;
719 	}
720 }
721 
722 /**
723  * radeon_driver_preclose_kms - drm callback for pre close
724  *
725  * @dev: drm dev pointer
726  * @file_priv: drm file
727  *
728  * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
729  * (all asics).
730  */
radeon_driver_preclose_kms(struct drm_device * dev,struct drm_file * file_priv)731 void radeon_driver_preclose_kms(struct drm_device *dev,
732 				struct drm_file *file_priv)
733 {
734 	struct radeon_device *rdev = dev->dev_private;
735 
736 	mutex_lock(&rdev->gem.mutex);
737 	if (rdev->hyperz_filp == file_priv)
738 		rdev->hyperz_filp = NULL;
739 	if (rdev->cmask_filp == file_priv)
740 		rdev->cmask_filp = NULL;
741 	mutex_unlock(&rdev->gem.mutex);
742 
743 	radeon_uvd_free_handles(rdev, file_priv);
744 	radeon_vce_free_handles(rdev, file_priv);
745 }
746 
747 /*
748  * VBlank related functions.
749  */
750 /**
751  * radeon_get_vblank_counter_kms - get frame count
752  *
753  * @dev: drm dev pointer
754  * @crtc: crtc to get the frame count from
755  *
756  * Gets the frame count on the requested crtc (all asics).
757  * Returns frame count on success, -EINVAL on failure.
758  */
radeon_get_vblank_counter_kms(struct drm_device * dev,int crtc)759 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
760 {
761 	int vpos, hpos, stat;
762 	u32 count;
763 	struct radeon_device *rdev = dev->dev_private;
764 
765 	if (crtc < 0 || crtc >= rdev->num_crtc) {
766 		DRM_ERROR("Invalid crtc %d\n", crtc);
767 		return -EINVAL;
768 	}
769 
770 	/* The hw increments its frame counter at start of vsync, not at start
771 	 * of vblank, as is required by DRM core vblank counter handling.
772 	 * Cook the hw count here to make it appear to the caller as if it
773 	 * incremented at start of vblank. We measure distance to start of
774 	 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
775 	 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
776 	 * result by 1 to give the proper appearance to caller.
777 	 */
778 	if (rdev->mode_info.crtcs[crtc]) {
779 		/* Repeat readout if needed to provide stable result if
780 		 * we cross start of vsync during the queries.
781 		 */
782 		do {
783 			count = radeon_get_vblank_counter(rdev, crtc);
784 			/* Ask radeon_get_crtc_scanoutpos to return vpos as
785 			 * distance to start of vblank, instead of regular
786 			 * vertical scanout pos.
787 			 */
788 			stat = radeon_get_crtc_scanoutpos(
789 				dev, crtc, GET_DISTANCE_TO_VBLANKSTART,
790 				&vpos, &hpos, NULL, NULL,
791 				&rdev->mode_info.crtcs[crtc]->base.hwmode);
792 		} while (count != radeon_get_vblank_counter(rdev, crtc));
793 
794 		if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
795 		    (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
796 			DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
797 		}
798 		else {
799 			DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
800 				      crtc, vpos);
801 
802 			/* Bump counter if we are at >= leading edge of vblank,
803 			 * but before vsync where vpos would turn negative and
804 			 * the hw counter really increments.
805 			 */
806 			if (vpos >= 0)
807 				count++;
808 		}
809 	}
810 	else {
811 	    /* Fallback to use value as is. */
812 	    count = radeon_get_vblank_counter(rdev, crtc);
813 	    DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
814 	}
815 
816 	return count;
817 }
818 
819 /**
820  * radeon_enable_vblank_kms - enable vblank interrupt
821  *
822  * @dev: drm dev pointer
823  * @crtc: crtc to enable vblank interrupt for
824  *
825  * Enable the interrupt on the requested crtc (all asics).
826  * Returns 0 on success, -EINVAL on failure.
827  */
radeon_enable_vblank_kms(struct drm_device * dev,int crtc)828 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
829 {
830 	struct radeon_device *rdev = dev->dev_private;
831 	unsigned long irqflags;
832 	int r;
833 
834 	if (crtc < 0 || crtc >= rdev->num_crtc) {
835 		DRM_ERROR("Invalid crtc %d\n", crtc);
836 		return -EINVAL;
837 	}
838 
839 	spin_lock_irqsave(&rdev->irq.lock, irqflags);
840 	rdev->irq.crtc_vblank_int[crtc] = true;
841 	r = radeon_irq_set(rdev);
842 	spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
843 	return r;
844 }
845 
846 /**
847  * radeon_disable_vblank_kms - disable vblank interrupt
848  *
849  * @dev: drm dev pointer
850  * @crtc: crtc to disable vblank interrupt for
851  *
852  * Disable the interrupt on the requested crtc (all asics).
853  */
radeon_disable_vblank_kms(struct drm_device * dev,int crtc)854 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
855 {
856 	struct radeon_device *rdev = dev->dev_private;
857 	unsigned long irqflags;
858 
859 	if (crtc < 0 || crtc >= rdev->num_crtc) {
860 		DRM_ERROR("Invalid crtc %d\n", crtc);
861 		return;
862 	}
863 
864 	spin_lock_irqsave(&rdev->irq.lock, irqflags);
865 	rdev->irq.crtc_vblank_int[crtc] = false;
866 	radeon_irq_set(rdev);
867 	spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
868 }
869 
870 /**
871  * radeon_get_vblank_timestamp_kms - get vblank timestamp
872  *
873  * @dev: drm dev pointer
874  * @crtc: crtc to get the timestamp for
875  * @max_error: max error
876  * @vblank_time: time value
877  * @flags: flags passed to the driver
878  *
879  * Gets the timestamp on the requested crtc based on the
880  * scanout position.  (all asics).
881  * Returns postive status flags on success, negative error on failure.
882  */
radeon_get_vblank_timestamp_kms(struct drm_device * dev,int crtc,int * max_error,struct timeval * vblank_time,unsigned flags)883 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
884 				    int *max_error,
885 				    struct timeval *vblank_time,
886 				    unsigned flags)
887 {
888 	struct drm_crtc *drmcrtc;
889 	struct radeon_device *rdev = dev->dev_private;
890 
891 	if (crtc < 0 || crtc >= dev->num_crtcs) {
892 		DRM_ERROR("Invalid crtc %d\n", crtc);
893 		return -EINVAL;
894 	}
895 
896 	/* Get associated drm_crtc: */
897 	drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
898 	if (!drmcrtc)
899 		return -EINVAL;
900 
901 	/* Helper routine in DRM core does all the work: */
902 	return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
903 						     vblank_time, flags,
904 						     &drmcrtc->hwmode);
905 }
906 
907 const struct drm_ioctl_desc radeon_ioctls_kms[] = {
908 	DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
909 	DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
910 	DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
911 	DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
912 	DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
913 	DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
914 	DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
915 	DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
916 	DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
917 	DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
918 	DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
919 	DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
920 	DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
921 	DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
922 	DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
923 	DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
924 	DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
925 	DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
926 	DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
927 	DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
928 	DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
929 	DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
930 	DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
931 	DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
932 	DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
933 	DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
934 	DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
935 	/* KMS */
936 	DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
937 	DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
938 	DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
939 	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
940 	DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
941 	DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
942 	DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
943 	DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
944 	DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
945 	DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
946 	DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
947 	DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
948 	DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
949 	DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
950 	DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
951 };
952 int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);
953