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1 #ifndef __ser_defs_h
2 #define __ser_defs_h
3 
4 /*
5  * This file is autogenerated from
6  *   file:           ../../inst/ser/rtl/ser_regs.r
7  *     id:           ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp
8  *     last modfied: Mon Apr 11 16:09:21 2005
9  *
10  *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r
11  *      id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $
12  * Any changes here will be lost.
13  *
14  * -*- buffer-read-only: t -*-
15  */
16 /* Main access macros */
17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \
19   REG_READ( reg_##scope##_##reg, \
20             (inst) + REG_RD_ADDR_##scope##_##reg )
21 #endif
22 
23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \
25   REG_WRITE( reg_##scope##_##reg, \
26              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #endif
28 
29 #ifndef REG_RD_VECT
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31   REG_READ( reg_##scope##_##reg, \
32             (inst) + REG_RD_ADDR_##scope##_##reg + \
33 	    (index) * STRIDE_##scope##_##reg )
34 #endif
35 
36 #ifndef REG_WR_VECT
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38   REG_WRITE( reg_##scope##_##reg, \
39              (inst) + REG_WR_ADDR_##scope##_##reg + \
40 	     (index) * STRIDE_##scope##_##reg, (val) )
41 #endif
42 
43 #ifndef REG_RD_INT
44 #define REG_RD_INT( scope, inst, reg ) \
45   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #endif
47 
48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \
50   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #endif
52 
53 #ifndef REG_RD_INT_VECT
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 	    (index) * STRIDE_##scope##_##reg )
57 #endif
58 
59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 	     (index) * STRIDE_##scope##_##reg, (val) )
63 #endif
64 
65 #ifndef REG_TYPE_CONV
66 #define REG_TYPE_CONV( type, orgtype, val ) \
67   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68 #endif
69 
70 #ifndef reg_page_size
71 #define reg_page_size 8192
72 #endif
73 
74 #ifndef REG_ADDR
75 #define REG_ADDR( scope, inst, reg ) \
76   ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #endif
78 
79 #ifndef REG_ADDR_VECT
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82     (index) * STRIDE_##scope##_##reg )
83 #endif
84 
85 /* C-code for register scope ser */
86 
87 /* Register rw_tr_ctrl, scope ser, type rw */
88 typedef struct {
89   unsigned int base_freq : 3;
90   unsigned int en        : 1;
91   unsigned int par       : 2;
92   unsigned int par_en    : 1;
93   unsigned int data_bits : 1;
94   unsigned int stop_bits : 1;
95   unsigned int stop      : 1;
96   unsigned int rts_delay : 3;
97   unsigned int rts_setup : 1;
98   unsigned int auto_rts  : 1;
99   unsigned int txd       : 1;
100   unsigned int auto_cts  : 1;
101   unsigned int dummy1    : 15;
102 } reg_ser_rw_tr_ctrl;
103 #define REG_RD_ADDR_ser_rw_tr_ctrl 0
104 #define REG_WR_ADDR_ser_rw_tr_ctrl 0
105 
106 /* Register rw_tr_dma_en, scope ser, type rw */
107 typedef struct {
108   unsigned int en : 1;
109   unsigned int dummy1 : 31;
110 } reg_ser_rw_tr_dma_en;
111 #define REG_RD_ADDR_ser_rw_tr_dma_en 4
112 #define REG_WR_ADDR_ser_rw_tr_dma_en 4
113 
114 /* Register rw_rec_ctrl, scope ser, type rw */
115 typedef struct {
116   unsigned int base_freq   : 3;
117   unsigned int en          : 1;
118   unsigned int par         : 2;
119   unsigned int par_en      : 1;
120   unsigned int data_bits   : 1;
121   unsigned int dma_mode    : 1;
122   unsigned int dma_err     : 1;
123   unsigned int sampling    : 1;
124   unsigned int timeout     : 3;
125   unsigned int auto_eop    : 1;
126   unsigned int half_duplex : 1;
127   unsigned int rts_n       : 1;
128   unsigned int loopback    : 1;
129   unsigned int dummy1      : 14;
130 } reg_ser_rw_rec_ctrl;
131 #define REG_RD_ADDR_ser_rw_rec_ctrl 8
132 #define REG_WR_ADDR_ser_rw_rec_ctrl 8
133 
134 /* Register rw_tr_baud_div, scope ser, type rw */
135 typedef struct {
136   unsigned int div : 16;
137   unsigned int dummy1 : 16;
138 } reg_ser_rw_tr_baud_div;
139 #define REG_RD_ADDR_ser_rw_tr_baud_div 12
140 #define REG_WR_ADDR_ser_rw_tr_baud_div 12
141 
142 /* Register rw_rec_baud_div, scope ser, type rw */
143 typedef struct {
144   unsigned int div : 16;
145   unsigned int dummy1 : 16;
146 } reg_ser_rw_rec_baud_div;
147 #define REG_RD_ADDR_ser_rw_rec_baud_div 16
148 #define REG_WR_ADDR_ser_rw_rec_baud_div 16
149 
150 /* Register rw_xoff, scope ser, type rw */
151 typedef struct {
152   unsigned int chr       : 8;
153   unsigned int automatic : 1;
154   unsigned int dummy1    : 23;
155 } reg_ser_rw_xoff;
156 #define REG_RD_ADDR_ser_rw_xoff 20
157 #define REG_WR_ADDR_ser_rw_xoff 20
158 
159 /* Register rw_xoff_clr, scope ser, type rw */
160 typedef struct {
161   unsigned int clr : 1;
162   unsigned int dummy1 : 31;
163 } reg_ser_rw_xoff_clr;
164 #define REG_RD_ADDR_ser_rw_xoff_clr 24
165 #define REG_WR_ADDR_ser_rw_xoff_clr 24
166 
167 /* Register rw_dout, scope ser, type rw */
168 typedef struct {
169   unsigned int data : 8;
170   unsigned int dummy1 : 24;
171 } reg_ser_rw_dout;
172 #define REG_RD_ADDR_ser_rw_dout 28
173 #define REG_WR_ADDR_ser_rw_dout 28
174 
175 /* Register rs_stat_din, scope ser, type rs */
176 typedef struct {
177   unsigned int data        : 8;
178   unsigned int dummy1      : 8;
179   unsigned int dav         : 1;
180   unsigned int framing_err : 1;
181   unsigned int par_err     : 1;
182   unsigned int orun        : 1;
183   unsigned int rec_err     : 1;
184   unsigned int rxd         : 1;
185   unsigned int tr_idle     : 1;
186   unsigned int tr_empty    : 1;
187   unsigned int tr_rdy      : 1;
188   unsigned int cts_n       : 1;
189   unsigned int xoff_detect : 1;
190   unsigned int rts_n       : 1;
191   unsigned int txd         : 1;
192   unsigned int dummy2      : 3;
193 } reg_ser_rs_stat_din;
194 #define REG_RD_ADDR_ser_rs_stat_din 32
195 
196 /* Register r_stat_din, scope ser, type r */
197 typedef struct {
198   unsigned int data        : 8;
199   unsigned int dummy1      : 8;
200   unsigned int dav         : 1;
201   unsigned int framing_err : 1;
202   unsigned int par_err     : 1;
203   unsigned int orun        : 1;
204   unsigned int rec_err     : 1;
205   unsigned int rxd         : 1;
206   unsigned int tr_idle     : 1;
207   unsigned int tr_empty    : 1;
208   unsigned int tr_rdy      : 1;
209   unsigned int cts_n       : 1;
210   unsigned int xoff_detect : 1;
211   unsigned int rts_n       : 1;
212   unsigned int txd         : 1;
213   unsigned int dummy2      : 3;
214 } reg_ser_r_stat_din;
215 #define REG_RD_ADDR_ser_r_stat_din 36
216 
217 /* Register rw_rec_eop, scope ser, type rw */
218 typedef struct {
219   unsigned int set : 1;
220   unsigned int dummy1 : 31;
221 } reg_ser_rw_rec_eop;
222 #define REG_RD_ADDR_ser_rw_rec_eop 40
223 #define REG_WR_ADDR_ser_rw_rec_eop 40
224 
225 /* Register rw_intr_mask, scope ser, type rw */
226 typedef struct {
227   unsigned int tr_rdy   : 1;
228   unsigned int tr_empty : 1;
229   unsigned int tr_idle  : 1;
230   unsigned int dav      : 1;
231   unsigned int dummy1   : 28;
232 } reg_ser_rw_intr_mask;
233 #define REG_RD_ADDR_ser_rw_intr_mask 44
234 #define REG_WR_ADDR_ser_rw_intr_mask 44
235 
236 /* Register rw_ack_intr, scope ser, type rw */
237 typedef struct {
238   unsigned int tr_rdy   : 1;
239   unsigned int tr_empty : 1;
240   unsigned int tr_idle  : 1;
241   unsigned int dav      : 1;
242   unsigned int dummy1   : 28;
243 } reg_ser_rw_ack_intr;
244 #define REG_RD_ADDR_ser_rw_ack_intr 48
245 #define REG_WR_ADDR_ser_rw_ack_intr 48
246 
247 /* Register r_intr, scope ser, type r */
248 typedef struct {
249   unsigned int tr_rdy   : 1;
250   unsigned int tr_empty : 1;
251   unsigned int tr_idle  : 1;
252   unsigned int dav      : 1;
253   unsigned int dummy1   : 28;
254 } reg_ser_r_intr;
255 #define REG_RD_ADDR_ser_r_intr 52
256 
257 /* Register r_masked_intr, scope ser, type r */
258 typedef struct {
259   unsigned int tr_rdy   : 1;
260   unsigned int tr_empty : 1;
261   unsigned int tr_idle  : 1;
262   unsigned int dav      : 1;
263   unsigned int dummy1   : 28;
264 } reg_ser_r_masked_intr;
265 #define REG_RD_ADDR_ser_r_masked_intr 56
266 
267 
268 /* Constants */
269 enum {
270   regk_ser_active                          = 0x00000000,
271   regk_ser_bits1                           = 0x00000000,
272   regk_ser_bits2                           = 0x00000001,
273   regk_ser_bits7                           = 0x00000001,
274   regk_ser_bits8                           = 0x00000000,
275   regk_ser_del0_5                          = 0x00000000,
276   regk_ser_del1                            = 0x00000001,
277   regk_ser_del1_5                          = 0x00000002,
278   regk_ser_del2                            = 0x00000003,
279   regk_ser_del2_5                          = 0x00000004,
280   regk_ser_del3                            = 0x00000005,
281   regk_ser_del3_5                          = 0x00000006,
282   regk_ser_del4                            = 0x00000007,
283   regk_ser_even                            = 0x00000000,
284   regk_ser_ext                             = 0x00000001,
285   regk_ser_f100                            = 0x00000007,
286   regk_ser_f29_493                         = 0x00000004,
287   regk_ser_f32                             = 0x00000005,
288   regk_ser_f32_768                         = 0x00000006,
289   regk_ser_ignore                          = 0x00000001,
290   regk_ser_inactive                        = 0x00000001,
291   regk_ser_majority                        = 0x00000001,
292   regk_ser_mark                            = 0x00000002,
293   regk_ser_middle                          = 0x00000000,
294   regk_ser_no                              = 0x00000000,
295   regk_ser_odd                             = 0x00000001,
296   regk_ser_off                             = 0x00000000,
297   regk_ser_rw_intr_mask_default            = 0x00000000,
298   regk_ser_rw_rec_baud_div_default         = 0x00000000,
299   regk_ser_rw_rec_ctrl_default             = 0x00010000,
300   regk_ser_rw_tr_baud_div_default          = 0x00000000,
301   regk_ser_rw_tr_ctrl_default              = 0x00008000,
302   regk_ser_rw_tr_dma_en_default            = 0x00000000,
303   regk_ser_rw_xoff_default                 = 0x00000000,
304   regk_ser_space                           = 0x00000003,
305   regk_ser_stop                            = 0x00000000,
306   regk_ser_yes                             = 0x00000001
307 };
308 #endif /* __ser_defs_h */
309