1 /*
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2015 Intel Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * BSD LICENSE
20 *
21 * Copyright(c) 2015 Intel Corporation.
22 *
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions
25 * are met:
26 *
27 * - Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * - Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in
31 * the documentation and/or other materials provided with the
32 * distribution.
33 * - Neither the name of Intel Corporation nor the names of its
34 * contributors may be used to endorse or promote products derived
35 * from this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 */
50
51 #include <linux/spinlock.h>
52 #include <linux/seqlock.h>
53 #include <linux/netdevice.h>
54 #include <linux/moduleparam.h>
55 #include <linux/bitops.h>
56 #include <linux/timer.h>
57 #include <linux/vmalloc.h>
58 #include <linux/highmem.h>
59
60 #include "hfi.h"
61 #include "common.h"
62 #include "qp.h"
63 #include "sdma.h"
64 #include "iowait.h"
65 #include "trace.h"
66
67 /* must be a power of 2 >= 64 <= 32768 */
68 #define SDMA_DESCQ_CNT 2048
69 #define SDMA_DESC_INTR 64
70 #define INVALID_TAIL 0xffff
71
72 static uint sdma_descq_cnt = SDMA_DESCQ_CNT;
73 module_param(sdma_descq_cnt, uint, S_IRUGO);
74 MODULE_PARM_DESC(sdma_descq_cnt, "Number of SDMA descq entries");
75
76 static uint sdma_idle_cnt = 250;
77 module_param(sdma_idle_cnt, uint, S_IRUGO);
78 MODULE_PARM_DESC(sdma_idle_cnt, "sdma interrupt idle delay (ns,default 250)");
79
80 uint mod_num_sdma;
81 module_param_named(num_sdma, mod_num_sdma, uint, S_IRUGO);
82 MODULE_PARM_DESC(num_sdma, "Set max number SDMA engines to use");
83
84 static uint sdma_desct_intr = SDMA_DESC_INTR;
85 module_param_named(desct_intr, sdma_desct_intr, uint, S_IRUGO | S_IWUSR);
86 MODULE_PARM_DESC(desct_intr, "Number of SDMA descriptor before interrupt");
87
88 #define SDMA_WAIT_BATCH_SIZE 20
89 /* max wait time for a SDMA engine to indicate it has halted */
90 #define SDMA_ERR_HALT_TIMEOUT 10 /* ms */
91 /* all SDMA engine errors that cause a halt */
92
93 #define SD(name) SEND_DMA_##name
94 #define ALL_SDMA_ENG_HALT_ERRS \
95 (SD(ENG_ERR_STATUS_SDMA_WRONG_DW_ERR_SMASK) \
96 | SD(ENG_ERR_STATUS_SDMA_GEN_MISMATCH_ERR_SMASK) \
97 | SD(ENG_ERR_STATUS_SDMA_TOO_LONG_ERR_SMASK) \
98 | SD(ENG_ERR_STATUS_SDMA_TAIL_OUT_OF_BOUNDS_ERR_SMASK) \
99 | SD(ENG_ERR_STATUS_SDMA_FIRST_DESC_ERR_SMASK) \
100 | SD(ENG_ERR_STATUS_SDMA_MEM_READ_ERR_SMASK) \
101 | SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK) \
102 | SD(ENG_ERR_STATUS_SDMA_LENGTH_MISMATCH_ERR_SMASK) \
103 | SD(ENG_ERR_STATUS_SDMA_PACKET_DESC_OVERFLOW_ERR_SMASK) \
104 | SD(ENG_ERR_STATUS_SDMA_HEADER_SELECT_ERR_SMASK) \
105 | SD(ENG_ERR_STATUS_SDMA_HEADER_ADDRESS_ERR_SMASK) \
106 | SD(ENG_ERR_STATUS_SDMA_HEADER_LENGTH_ERR_SMASK) \
107 | SD(ENG_ERR_STATUS_SDMA_TIMEOUT_ERR_SMASK) \
108 | SD(ENG_ERR_STATUS_SDMA_DESC_TABLE_UNC_ERR_SMASK) \
109 | SD(ENG_ERR_STATUS_SDMA_ASSEMBLY_UNC_ERR_SMASK) \
110 | SD(ENG_ERR_STATUS_SDMA_PACKET_TRACKING_UNC_ERR_SMASK) \
111 | SD(ENG_ERR_STATUS_SDMA_HEADER_STORAGE_UNC_ERR_SMASK) \
112 | SD(ENG_ERR_STATUS_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SMASK))
113
114 /* sdma_sendctrl operations */
115 #define SDMA_SENDCTRL_OP_ENABLE (1U << 0)
116 #define SDMA_SENDCTRL_OP_INTENABLE (1U << 1)
117 #define SDMA_SENDCTRL_OP_HALT (1U << 2)
118 #define SDMA_SENDCTRL_OP_CLEANUP (1U << 3)
119
120 /* handle long defines */
121 #define SDMA_EGRESS_PACKET_OCCUPANCY_SMASK \
122 SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SMASK
123 #define SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT \
124 SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT
125
126 static const char * const sdma_state_names[] = {
127 [sdma_state_s00_hw_down] = "s00_HwDown",
128 [sdma_state_s10_hw_start_up_halt_wait] = "s10_HwStartUpHaltWait",
129 [sdma_state_s15_hw_start_up_clean_wait] = "s15_HwStartUpCleanWait",
130 [sdma_state_s20_idle] = "s20_Idle",
131 [sdma_state_s30_sw_clean_up_wait] = "s30_SwCleanUpWait",
132 [sdma_state_s40_hw_clean_up_wait] = "s40_HwCleanUpWait",
133 [sdma_state_s50_hw_halt_wait] = "s50_HwHaltWait",
134 [sdma_state_s60_idle_halt_wait] = "s60_IdleHaltWait",
135 [sdma_state_s80_hw_freeze] = "s80_HwFreeze",
136 [sdma_state_s82_freeze_sw_clean] = "s82_FreezeSwClean",
137 [sdma_state_s99_running] = "s99_Running",
138 };
139
140 static const char * const sdma_event_names[] = {
141 [sdma_event_e00_go_hw_down] = "e00_GoHwDown",
142 [sdma_event_e10_go_hw_start] = "e10_GoHwStart",
143 [sdma_event_e15_hw_halt_done] = "e15_HwHaltDone",
144 [sdma_event_e25_hw_clean_up_done] = "e25_HwCleanUpDone",
145 [sdma_event_e30_go_running] = "e30_GoRunning",
146 [sdma_event_e40_sw_cleaned] = "e40_SwCleaned",
147 [sdma_event_e50_hw_cleaned] = "e50_HwCleaned",
148 [sdma_event_e60_hw_halted] = "e60_HwHalted",
149 [sdma_event_e70_go_idle] = "e70_GoIdle",
150 [sdma_event_e80_hw_freeze] = "e80_HwFreeze",
151 [sdma_event_e81_hw_frozen] = "e81_HwFrozen",
152 [sdma_event_e82_hw_unfreeze] = "e82_HwUnfreeze",
153 [sdma_event_e85_link_down] = "e85_LinkDown",
154 [sdma_event_e90_sw_halted] = "e90_SwHalted",
155 };
156
157 static const struct sdma_set_state_action sdma_action_table[] = {
158 [sdma_state_s00_hw_down] = {
159 .go_s99_running_tofalse = 1,
160 .op_enable = 0,
161 .op_intenable = 0,
162 .op_halt = 0,
163 .op_cleanup = 0,
164 },
165 [sdma_state_s10_hw_start_up_halt_wait] = {
166 .op_enable = 0,
167 .op_intenable = 0,
168 .op_halt = 1,
169 .op_cleanup = 0,
170 },
171 [sdma_state_s15_hw_start_up_clean_wait] = {
172 .op_enable = 0,
173 .op_intenable = 1,
174 .op_halt = 0,
175 .op_cleanup = 1,
176 },
177 [sdma_state_s20_idle] = {
178 .op_enable = 0,
179 .op_intenable = 1,
180 .op_halt = 0,
181 .op_cleanup = 0,
182 },
183 [sdma_state_s30_sw_clean_up_wait] = {
184 .op_enable = 0,
185 .op_intenable = 0,
186 .op_halt = 0,
187 .op_cleanup = 0,
188 },
189 [sdma_state_s40_hw_clean_up_wait] = {
190 .op_enable = 0,
191 .op_intenable = 0,
192 .op_halt = 0,
193 .op_cleanup = 1,
194 },
195 [sdma_state_s50_hw_halt_wait] = {
196 .op_enable = 0,
197 .op_intenable = 0,
198 .op_halt = 0,
199 .op_cleanup = 0,
200 },
201 [sdma_state_s60_idle_halt_wait] = {
202 .go_s99_running_tofalse = 1,
203 .op_enable = 0,
204 .op_intenable = 0,
205 .op_halt = 1,
206 .op_cleanup = 0,
207 },
208 [sdma_state_s80_hw_freeze] = {
209 .op_enable = 0,
210 .op_intenable = 0,
211 .op_halt = 0,
212 .op_cleanup = 0,
213 },
214 [sdma_state_s82_freeze_sw_clean] = {
215 .op_enable = 0,
216 .op_intenable = 0,
217 .op_halt = 0,
218 .op_cleanup = 0,
219 },
220 [sdma_state_s99_running] = {
221 .op_enable = 1,
222 .op_intenable = 1,
223 .op_halt = 0,
224 .op_cleanup = 0,
225 .go_s99_running_totrue = 1,
226 },
227 };
228
229 #define SDMA_TAIL_UPDATE_THRESH 0x1F
230
231 /* declare all statics here rather than keep sorting */
232 static void sdma_complete(struct kref *);
233 static void sdma_finalput(struct sdma_state *);
234 static void sdma_get(struct sdma_state *);
235 static void sdma_hw_clean_up_task(unsigned long);
236 static void sdma_put(struct sdma_state *);
237 static void sdma_set_state(struct sdma_engine *, enum sdma_states);
238 static void sdma_start_hw_clean_up(struct sdma_engine *);
239 static void sdma_start_sw_clean_up(struct sdma_engine *);
240 static void sdma_sw_clean_up_task(unsigned long);
241 static void sdma_sendctrl(struct sdma_engine *, unsigned);
242 static void init_sdma_regs(struct sdma_engine *, u32, uint);
243 static void sdma_process_event(
244 struct sdma_engine *sde,
245 enum sdma_events event);
246 static void __sdma_process_event(
247 struct sdma_engine *sde,
248 enum sdma_events event);
249 static void dump_sdma_state(struct sdma_engine *sde);
250 static void sdma_make_progress(struct sdma_engine *sde, u64 status);
251 static void sdma_desc_avail(struct sdma_engine *sde, unsigned avail);
252 static void sdma_flush_descq(struct sdma_engine *sde);
253
254 /**
255 * sdma_state_name() - return state string from enum
256 * @state: state
257 */
sdma_state_name(enum sdma_states state)258 static const char *sdma_state_name(enum sdma_states state)
259 {
260 return sdma_state_names[state];
261 }
262
sdma_get(struct sdma_state * ss)263 static void sdma_get(struct sdma_state *ss)
264 {
265 kref_get(&ss->kref);
266 }
267
sdma_complete(struct kref * kref)268 static void sdma_complete(struct kref *kref)
269 {
270 struct sdma_state *ss =
271 container_of(kref, struct sdma_state, kref);
272
273 complete(&ss->comp);
274 }
275
sdma_put(struct sdma_state * ss)276 static void sdma_put(struct sdma_state *ss)
277 {
278 kref_put(&ss->kref, sdma_complete);
279 }
280
sdma_finalput(struct sdma_state * ss)281 static void sdma_finalput(struct sdma_state *ss)
282 {
283 sdma_put(ss);
284 wait_for_completion(&ss->comp);
285 }
286
write_sde_csr(struct sdma_engine * sde,u32 offset0,u64 value)287 static inline void write_sde_csr(
288 struct sdma_engine *sde,
289 u32 offset0,
290 u64 value)
291 {
292 write_kctxt_csr(sde->dd, sde->this_idx, offset0, value);
293 }
294
read_sde_csr(struct sdma_engine * sde,u32 offset0)295 static inline u64 read_sde_csr(
296 struct sdma_engine *sde,
297 u32 offset0)
298 {
299 return read_kctxt_csr(sde->dd, sde->this_idx, offset0);
300 }
301
302 /*
303 * sdma_wait_for_packet_egress() - wait for the VL FIFO occupancy for
304 * sdma engine 'sde' to drop to 0.
305 */
sdma_wait_for_packet_egress(struct sdma_engine * sde,int pause)306 static void sdma_wait_for_packet_egress(struct sdma_engine *sde,
307 int pause)
308 {
309 u64 off = 8 * sde->this_idx;
310 struct hfi1_devdata *dd = sde->dd;
311 int lcnt = 0;
312 u64 reg_prev;
313 u64 reg = 0;
314
315 while (1) {
316 reg_prev = reg;
317 reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS);
318
319 reg &= SDMA_EGRESS_PACKET_OCCUPANCY_SMASK;
320 reg >>= SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT;
321 if (reg == 0)
322 break;
323 /* counter is reest if accupancy count changes */
324 if (reg != reg_prev)
325 lcnt = 0;
326 if (lcnt++ > 500) {
327 /* timed out - bounce the link */
328 dd_dev_err(dd, "%s: engine %u timeout waiting for packets to egress, remaining count %u, bouncing link\n",
329 __func__, sde->this_idx, (u32)reg);
330 queue_work(dd->pport->hfi1_wq,
331 &dd->pport->link_bounce_work);
332 break;
333 }
334 udelay(1);
335 }
336 }
337
338 /*
339 * sdma_wait() - wait for packet egress to complete for all SDMA engines,
340 * and pause for credit return.
341 */
sdma_wait(struct hfi1_devdata * dd)342 void sdma_wait(struct hfi1_devdata *dd)
343 {
344 int i;
345
346 for (i = 0; i < dd->num_sdma; i++) {
347 struct sdma_engine *sde = &dd->per_sdma[i];
348
349 sdma_wait_for_packet_egress(sde, 0);
350 }
351 }
352
sdma_set_desc_cnt(struct sdma_engine * sde,unsigned cnt)353 static inline void sdma_set_desc_cnt(struct sdma_engine *sde, unsigned cnt)
354 {
355 u64 reg;
356
357 if (!(sde->dd->flags & HFI1_HAS_SDMA_TIMEOUT))
358 return;
359 reg = cnt;
360 reg &= SD(DESC_CNT_CNT_MASK);
361 reg <<= SD(DESC_CNT_CNT_SHIFT);
362 write_sde_csr(sde, SD(DESC_CNT), reg);
363 }
364
365 /*
366 * Complete all the sdma requests with a SDMA_TXREQ_S_ABORTED status
367 *
368 * Depending on timing there can be txreqs in two places:
369 * - in the descq ring
370 * - in the flush list
371 *
372 * To avoid ordering issues the descq ring needs to be flushed
373 * first followed by the flush list.
374 *
375 * This routine is called from two places
376 * - From a work queue item
377 * - Directly from the state machine just before setting the
378 * state to running
379 *
380 * Must be called with head_lock held
381 *
382 */
sdma_flush(struct sdma_engine * sde)383 static void sdma_flush(struct sdma_engine *sde)
384 {
385 struct sdma_txreq *txp, *txp_next;
386 LIST_HEAD(flushlist);
387 unsigned long flags;
388
389 /* flush from head to tail */
390 sdma_flush_descq(sde);
391 spin_lock_irqsave(&sde->flushlist_lock, flags);
392 /* copy flush list */
393 list_for_each_entry_safe(txp, txp_next, &sde->flushlist, list) {
394 list_del_init(&txp->list);
395 list_add_tail(&txp->list, &flushlist);
396 }
397 spin_unlock_irqrestore(&sde->flushlist_lock, flags);
398 /* flush from flush list */
399 list_for_each_entry_safe(txp, txp_next, &flushlist, list) {
400 int drained = 0;
401 /* protect against complete modifying */
402 struct iowait *wait = txp->wait;
403
404 list_del_init(&txp->list);
405 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
406 trace_hfi1_sdma_out_sn(sde, txp->sn);
407 if (WARN_ON_ONCE(sde->head_sn != txp->sn))
408 dd_dev_err(sde->dd, "expected %llu got %llu\n",
409 sde->head_sn, txp->sn);
410 sde->head_sn++;
411 #endif
412 sdma_txclean(sde->dd, txp);
413 if (wait)
414 drained = atomic_dec_and_test(&wait->sdma_busy);
415 if (txp->complete)
416 (*txp->complete)(txp, SDMA_TXREQ_S_ABORTED, drained);
417 if (wait && drained)
418 iowait_drain_wakeup(wait);
419 }
420 }
421
422 /*
423 * Fields a work request for flushing the descq ring
424 * and the flush list
425 *
426 * If the engine has been brought to running during
427 * the scheduling delay, the flush is ignored, assuming
428 * that the process of bringing the engine to running
429 * would have done this flush prior to going to running.
430 *
431 */
sdma_field_flush(struct work_struct * work)432 static void sdma_field_flush(struct work_struct *work)
433 {
434 unsigned long flags;
435 struct sdma_engine *sde =
436 container_of(work, struct sdma_engine, flush_worker);
437
438 write_seqlock_irqsave(&sde->head_lock, flags);
439 if (!__sdma_running(sde))
440 sdma_flush(sde);
441 write_sequnlock_irqrestore(&sde->head_lock, flags);
442 }
443
sdma_err_halt_wait(struct work_struct * work)444 static void sdma_err_halt_wait(struct work_struct *work)
445 {
446 struct sdma_engine *sde = container_of(work, struct sdma_engine,
447 err_halt_worker);
448 u64 statuscsr;
449 unsigned long timeout;
450
451 timeout = jiffies + msecs_to_jiffies(SDMA_ERR_HALT_TIMEOUT);
452 while (1) {
453 statuscsr = read_sde_csr(sde, SD(STATUS));
454 statuscsr &= SD(STATUS_ENG_HALTED_SMASK);
455 if (statuscsr)
456 break;
457 if (time_after(jiffies, timeout)) {
458 dd_dev_err(sde->dd,
459 "SDMA engine %d - timeout waiting for engine to halt\n",
460 sde->this_idx);
461 /*
462 * Continue anyway. This could happen if there was
463 * an uncorrectable error in the wrong spot.
464 */
465 break;
466 }
467 usleep_range(80, 120);
468 }
469
470 sdma_process_event(sde, sdma_event_e15_hw_halt_done);
471 }
472
sdma_start_err_halt_wait(struct sdma_engine * sde)473 static void sdma_start_err_halt_wait(struct sdma_engine *sde)
474 {
475 schedule_work(&sde->err_halt_worker);
476 }
477
478
sdma_err_progress_check_schedule(struct sdma_engine * sde)479 static void sdma_err_progress_check_schedule(struct sdma_engine *sde)
480 {
481 if (!is_bx(sde->dd) && HFI1_CAP_IS_KSET(SDMA_AHG)) {
482
483 unsigned index;
484 struct hfi1_devdata *dd = sde->dd;
485
486 for (index = 0; index < dd->num_sdma; index++) {
487 struct sdma_engine *curr_sdma = &dd->per_sdma[index];
488
489 if (curr_sdma != sde)
490 curr_sdma->progress_check_head =
491 curr_sdma->descq_head;
492 }
493 dd_dev_err(sde->dd,
494 "SDMA engine %d - check scheduled\n",
495 sde->this_idx);
496 mod_timer(&sde->err_progress_check_timer, jiffies + 10);
497 }
498 }
499
sdma_err_progress_check(unsigned long data)500 static void sdma_err_progress_check(unsigned long data)
501 {
502 unsigned index;
503 struct sdma_engine *sde = (struct sdma_engine *)data;
504
505 dd_dev_err(sde->dd, "SDE progress check event\n");
506 for (index = 0; index < sde->dd->num_sdma; index++) {
507 struct sdma_engine *curr_sde = &sde->dd->per_sdma[index];
508 unsigned long flags;
509
510 /* check progress on each engine except the current one */
511 if (curr_sde == sde)
512 continue;
513 /*
514 * We must lock interrupts when acquiring sde->lock,
515 * to avoid a deadlock if interrupt triggers and spins on
516 * the same lock on same CPU
517 */
518 spin_lock_irqsave(&curr_sde->tail_lock, flags);
519 write_seqlock(&curr_sde->head_lock);
520
521 /* skip non-running queues */
522 if (curr_sde->state.current_state != sdma_state_s99_running) {
523 write_sequnlock(&curr_sde->head_lock);
524 spin_unlock_irqrestore(&curr_sde->tail_lock, flags);
525 continue;
526 }
527
528 if ((curr_sde->descq_head != curr_sde->descq_tail) &&
529 (curr_sde->descq_head ==
530 curr_sde->progress_check_head))
531 __sdma_process_event(curr_sde,
532 sdma_event_e90_sw_halted);
533 write_sequnlock(&curr_sde->head_lock);
534 spin_unlock_irqrestore(&curr_sde->tail_lock, flags);
535 }
536 schedule_work(&sde->err_halt_worker);
537 }
538
sdma_hw_clean_up_task(unsigned long opaque)539 static void sdma_hw_clean_up_task(unsigned long opaque)
540 {
541 struct sdma_engine *sde = (struct sdma_engine *) opaque;
542 u64 statuscsr;
543
544 while (1) {
545 #ifdef CONFIG_SDMA_VERBOSITY
546 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
547 sde->this_idx, slashstrip(__FILE__), __LINE__,
548 __func__);
549 #endif
550 statuscsr = read_sde_csr(sde, SD(STATUS));
551 statuscsr &= SD(STATUS_ENG_CLEANED_UP_SMASK);
552 if (statuscsr)
553 break;
554 udelay(10);
555 }
556
557 sdma_process_event(sde, sdma_event_e25_hw_clean_up_done);
558 }
559
get_txhead(struct sdma_engine * sde)560 static inline struct sdma_txreq *get_txhead(struct sdma_engine *sde)
561 {
562 smp_read_barrier_depends(); /* see sdma_update_tail() */
563 return sde->tx_ring[sde->tx_head & sde->sdma_mask];
564 }
565
566 /*
567 * flush ring for recovery
568 */
sdma_flush_descq(struct sdma_engine * sde)569 static void sdma_flush_descq(struct sdma_engine *sde)
570 {
571 u16 head, tail;
572 int progress = 0;
573 struct sdma_txreq *txp = get_txhead(sde);
574
575 /* The reason for some of the complexity of this code is that
576 * not all descriptors have corresponding txps. So, we have to
577 * be able to skip over descs until we wander into the range of
578 * the next txp on the list.
579 */
580 head = sde->descq_head & sde->sdma_mask;
581 tail = sde->descq_tail & sde->sdma_mask;
582 while (head != tail) {
583 /* advance head, wrap if needed */
584 head = ++sde->descq_head & sde->sdma_mask;
585 /* if now past this txp's descs, do the callback */
586 if (txp && txp->next_descq_idx == head) {
587 int drained = 0;
588 /* protect against complete modifying */
589 struct iowait *wait = txp->wait;
590
591 /* remove from list */
592 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL;
593 if (wait)
594 drained = atomic_dec_and_test(&wait->sdma_busy);
595 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
596 trace_hfi1_sdma_out_sn(sde, txp->sn);
597 if (WARN_ON_ONCE(sde->head_sn != txp->sn))
598 dd_dev_err(sde->dd, "expected %llu got %llu\n",
599 sde->head_sn, txp->sn);
600 sde->head_sn++;
601 #endif
602 sdma_txclean(sde->dd, txp);
603 trace_hfi1_sdma_progress(sde, head, tail, txp);
604 if (txp->complete)
605 (*txp->complete)(
606 txp,
607 SDMA_TXREQ_S_ABORTED,
608 drained);
609 if (wait && drained)
610 iowait_drain_wakeup(wait);
611 /* see if there is another txp */
612 txp = get_txhead(sde);
613 }
614 progress++;
615 }
616 if (progress)
617 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
618 }
619
sdma_sw_clean_up_task(unsigned long opaque)620 static void sdma_sw_clean_up_task(unsigned long opaque)
621 {
622 struct sdma_engine *sde = (struct sdma_engine *) opaque;
623 unsigned long flags;
624
625 spin_lock_irqsave(&sde->tail_lock, flags);
626 write_seqlock(&sde->head_lock);
627
628 /*
629 * At this point, the following should always be true:
630 * - We are halted, so no more descriptors are getting retired.
631 * - We are not running, so no one is submitting new work.
632 * - Only we can send the e40_sw_cleaned, so we can't start
633 * running again until we say so. So, the active list and
634 * descq are ours to play with.
635 */
636
637
638 /*
639 * In the error clean up sequence, software clean must be called
640 * before the hardware clean so we can use the hardware head in
641 * the progress routine. A hardware clean or SPC unfreeze will
642 * reset the hardware head.
643 *
644 * Process all retired requests. The progress routine will use the
645 * latest physical hardware head - we are not running so speed does
646 * not matter.
647 */
648 sdma_make_progress(sde, 0);
649
650 sdma_flush(sde);
651
652 /*
653 * Reset our notion of head and tail.
654 * Note that the HW registers have been reset via an earlier
655 * clean up.
656 */
657 sde->descq_tail = 0;
658 sde->descq_head = 0;
659 sde->desc_avail = sdma_descq_freecnt(sde);
660 *sde->head_dma = 0;
661
662 __sdma_process_event(sde, sdma_event_e40_sw_cleaned);
663
664 write_sequnlock(&sde->head_lock);
665 spin_unlock_irqrestore(&sde->tail_lock, flags);
666 }
667
sdma_sw_tear_down(struct sdma_engine * sde)668 static void sdma_sw_tear_down(struct sdma_engine *sde)
669 {
670 struct sdma_state *ss = &sde->state;
671
672 /* Releasing this reference means the state machine has stopped. */
673 sdma_put(ss);
674
675 /* stop waiting for all unfreeze events to complete */
676 atomic_set(&sde->dd->sdma_unfreeze_count, -1);
677 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
678 }
679
sdma_start_hw_clean_up(struct sdma_engine * sde)680 static void sdma_start_hw_clean_up(struct sdma_engine *sde)
681 {
682 tasklet_hi_schedule(&sde->sdma_hw_clean_up_task);
683 }
684
sdma_start_sw_clean_up(struct sdma_engine * sde)685 static void sdma_start_sw_clean_up(struct sdma_engine *sde)
686 {
687 tasklet_hi_schedule(&sde->sdma_sw_clean_up_task);
688 }
689
sdma_set_state(struct sdma_engine * sde,enum sdma_states next_state)690 static void sdma_set_state(struct sdma_engine *sde,
691 enum sdma_states next_state)
692 {
693 struct sdma_state *ss = &sde->state;
694 const struct sdma_set_state_action *action = sdma_action_table;
695 unsigned op = 0;
696
697 trace_hfi1_sdma_state(
698 sde,
699 sdma_state_names[ss->current_state],
700 sdma_state_names[next_state]);
701
702 /* debugging bookkeeping */
703 ss->previous_state = ss->current_state;
704 ss->previous_op = ss->current_op;
705 ss->current_state = next_state;
706
707 if (ss->previous_state != sdma_state_s99_running
708 && next_state == sdma_state_s99_running)
709 sdma_flush(sde);
710
711 if (action[next_state].op_enable)
712 op |= SDMA_SENDCTRL_OP_ENABLE;
713
714 if (action[next_state].op_intenable)
715 op |= SDMA_SENDCTRL_OP_INTENABLE;
716
717 if (action[next_state].op_halt)
718 op |= SDMA_SENDCTRL_OP_HALT;
719
720 if (action[next_state].op_cleanup)
721 op |= SDMA_SENDCTRL_OP_CLEANUP;
722
723 if (action[next_state].go_s99_running_tofalse)
724 ss->go_s99_running = 0;
725
726 if (action[next_state].go_s99_running_totrue)
727 ss->go_s99_running = 1;
728
729 ss->current_op = op;
730 sdma_sendctrl(sde, ss->current_op);
731 }
732
733 /**
734 * sdma_get_descq_cnt() - called when device probed
735 *
736 * Return a validated descq count.
737 *
738 * This is currently only used in the verbs initialization to build the tx
739 * list.
740 *
741 * This will probably be deleted in favor of a more scalable approach to
742 * alloc tx's.
743 *
744 */
sdma_get_descq_cnt(void)745 u16 sdma_get_descq_cnt(void)
746 {
747 u16 count = sdma_descq_cnt;
748
749 if (!count)
750 return SDMA_DESCQ_CNT;
751 /* count must be a power of 2 greater than 64 and less than
752 * 32768. Otherwise return default.
753 */
754 if (!is_power_of_2(count))
755 return SDMA_DESCQ_CNT;
756 if (count < 64 || count > 32768)
757 return SDMA_DESCQ_CNT;
758 return count;
759 }
760
761 /**
762 * sdma_select_engine_vl() - select sdma engine
763 * @dd: devdata
764 * @selector: a spreading factor
765 * @vl: this vl
766 *
767 *
768 * This function returns an engine based on the selector and a vl. The
769 * mapping fields are protected by RCU.
770 */
sdma_select_engine_vl(struct hfi1_devdata * dd,u32 selector,u8 vl)771 struct sdma_engine *sdma_select_engine_vl(
772 struct hfi1_devdata *dd,
773 u32 selector,
774 u8 vl)
775 {
776 struct sdma_vl_map *m;
777 struct sdma_map_elem *e;
778 struct sdma_engine *rval;
779
780 if (WARN_ON(vl > 8))
781 return NULL;
782
783 rcu_read_lock();
784 m = rcu_dereference(dd->sdma_map);
785 if (unlikely(!m)) {
786 rcu_read_unlock();
787 return NULL;
788 }
789 e = m->map[vl & m->mask];
790 rval = e->sde[selector & e->mask];
791 rcu_read_unlock();
792
793 trace_hfi1_sdma_engine_select(dd, selector, vl, rval->this_idx);
794 return rval;
795 }
796
797 /**
798 * sdma_select_engine_sc() - select sdma engine
799 * @dd: devdata
800 * @selector: a spreading factor
801 * @sc5: the 5 bit sc
802 *
803 *
804 * This function returns an engine based on the selector and an sc.
805 */
sdma_select_engine_sc(struct hfi1_devdata * dd,u32 selector,u8 sc5)806 struct sdma_engine *sdma_select_engine_sc(
807 struct hfi1_devdata *dd,
808 u32 selector,
809 u8 sc5)
810 {
811 u8 vl = sc_to_vlt(dd, sc5);
812
813 return sdma_select_engine_vl(dd, selector, vl);
814 }
815
816 /*
817 * Free the indicated map struct
818 */
sdma_map_free(struct sdma_vl_map * m)819 static void sdma_map_free(struct sdma_vl_map *m)
820 {
821 int i;
822
823 for (i = 0; m && i < m->actual_vls; i++)
824 kfree(m->map[i]);
825 kfree(m);
826 }
827
828 /*
829 * Handle RCU callback
830 */
sdma_map_rcu_callback(struct rcu_head * list)831 static void sdma_map_rcu_callback(struct rcu_head *list)
832 {
833 struct sdma_vl_map *m = container_of(list, struct sdma_vl_map, list);
834
835 sdma_map_free(m);
836 }
837
838 /**
839 * sdma_map_init - called when # vls change
840 * @dd: hfi1_devdata
841 * @port: port number
842 * @num_vls: number of vls
843 * @vl_engines: per vl engine mapping (optional)
844 *
845 * This routine changes the mapping based on the number of vls.
846 *
847 * vl_engines is used to specify a non-uniform vl/engine loading. NULL
848 * implies auto computing the loading and giving each VLs a uniform
849 * distribution of engines per VL.
850 *
851 * The auto algorithm computes the sde_per_vl and the number of extra
852 * engines. Any extra engines are added from the last VL on down.
853 *
854 * rcu locking is used here to control access to the mapping fields.
855 *
856 * If either the num_vls or num_sdma are non-power of 2, the array sizes
857 * in the struct sdma_vl_map and the struct sdma_map_elem are rounded
858 * up to the next highest power of 2 and the first entry is reused
859 * in a round robin fashion.
860 *
861 * If an error occurs the map change is not done and the mapping is
862 * not changed.
863 *
864 */
sdma_map_init(struct hfi1_devdata * dd,u8 port,u8 num_vls,u8 * vl_engines)865 int sdma_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, u8 *vl_engines)
866 {
867 int i, j;
868 int extra, sde_per_vl;
869 int engine = 0;
870 u8 lvl_engines[OPA_MAX_VLS];
871 struct sdma_vl_map *oldmap, *newmap;
872
873 if (!(dd->flags & HFI1_HAS_SEND_DMA))
874 return 0;
875
876 if (!vl_engines) {
877 /* truncate divide */
878 sde_per_vl = dd->num_sdma / num_vls;
879 /* extras */
880 extra = dd->num_sdma % num_vls;
881 vl_engines = lvl_engines;
882 /* add extras from last vl down */
883 for (i = num_vls - 1; i >= 0; i--, extra--)
884 vl_engines[i] = sde_per_vl + (extra > 0 ? 1 : 0);
885 }
886 /* build new map */
887 newmap = kzalloc(
888 sizeof(struct sdma_vl_map) +
889 roundup_pow_of_two(num_vls) *
890 sizeof(struct sdma_map_elem *),
891 GFP_KERNEL);
892 if (!newmap)
893 goto bail;
894 newmap->actual_vls = num_vls;
895 newmap->vls = roundup_pow_of_two(num_vls);
896 newmap->mask = (1 << ilog2(newmap->vls)) - 1;
897 for (i = 0; i < newmap->vls; i++) {
898 /* save for wrap around */
899 int first_engine = engine;
900
901 if (i < newmap->actual_vls) {
902 int sz = roundup_pow_of_two(vl_engines[i]);
903
904 /* only allocate once */
905 newmap->map[i] = kzalloc(
906 sizeof(struct sdma_map_elem) +
907 sz * sizeof(struct sdma_engine *),
908 GFP_KERNEL);
909 if (!newmap->map[i])
910 goto bail;
911 newmap->map[i]->mask = (1 << ilog2(sz)) - 1;
912 /* assign engines */
913 for (j = 0; j < sz; j++) {
914 newmap->map[i]->sde[j] =
915 &dd->per_sdma[engine];
916 if (++engine >= first_engine + vl_engines[i])
917 /* wrap back to first engine */
918 engine = first_engine;
919 }
920 } else {
921 /* just re-use entry without allocating */
922 newmap->map[i] = newmap->map[i % num_vls];
923 }
924 engine = first_engine + vl_engines[i];
925 }
926 /* newmap in hand, save old map */
927 spin_lock_irq(&dd->sde_map_lock);
928 oldmap = rcu_dereference_protected(dd->sdma_map,
929 lockdep_is_held(&dd->sde_map_lock));
930
931 /* publish newmap */
932 rcu_assign_pointer(dd->sdma_map, newmap);
933
934 spin_unlock_irq(&dd->sde_map_lock);
935 /* success, free any old map after grace period */
936 if (oldmap)
937 call_rcu(&oldmap->list, sdma_map_rcu_callback);
938 return 0;
939 bail:
940 /* free any partial allocation */
941 sdma_map_free(newmap);
942 return -ENOMEM;
943 }
944
945 /*
946 * Clean up allocated memory.
947 *
948 * This routine is can be called regardless of the success of sdma_init()
949 *
950 */
sdma_clean(struct hfi1_devdata * dd,size_t num_engines)951 static void sdma_clean(struct hfi1_devdata *dd, size_t num_engines)
952 {
953 size_t i;
954 struct sdma_engine *sde;
955
956 if (dd->sdma_pad_dma) {
957 dma_free_coherent(&dd->pcidev->dev, 4,
958 (void *)dd->sdma_pad_dma,
959 dd->sdma_pad_phys);
960 dd->sdma_pad_dma = NULL;
961 dd->sdma_pad_phys = 0;
962 }
963 if (dd->sdma_heads_dma) {
964 dma_free_coherent(&dd->pcidev->dev, dd->sdma_heads_size,
965 (void *)dd->sdma_heads_dma,
966 dd->sdma_heads_phys);
967 dd->sdma_heads_dma = NULL;
968 dd->sdma_heads_phys = 0;
969 }
970 for (i = 0; dd->per_sdma && i < num_engines; ++i) {
971 sde = &dd->per_sdma[i];
972
973 sde->head_dma = NULL;
974 sde->head_phys = 0;
975
976 if (sde->descq) {
977 dma_free_coherent(
978 &dd->pcidev->dev,
979 sde->descq_cnt * sizeof(u64[2]),
980 sde->descq,
981 sde->descq_phys
982 );
983 sde->descq = NULL;
984 sde->descq_phys = 0;
985 }
986 kvfree(sde->tx_ring);
987 sde->tx_ring = NULL;
988 }
989 spin_lock_irq(&dd->sde_map_lock);
990 kfree(rcu_access_pointer(dd->sdma_map));
991 RCU_INIT_POINTER(dd->sdma_map, NULL);
992 spin_unlock_irq(&dd->sde_map_lock);
993 synchronize_rcu();
994 kfree(dd->per_sdma);
995 dd->per_sdma = NULL;
996 }
997
998 /**
999 * sdma_init() - called when device probed
1000 * @dd: hfi1_devdata
1001 * @port: port number (currently only zero)
1002 *
1003 * sdma_init initializes the specified number of engines.
1004 *
1005 * The code initializes each sde, its csrs. Interrupts
1006 * are not required to be enabled.
1007 *
1008 * Returns:
1009 * 0 - success, -errno on failure
1010 */
sdma_init(struct hfi1_devdata * dd,u8 port)1011 int sdma_init(struct hfi1_devdata *dd, u8 port)
1012 {
1013 unsigned this_idx;
1014 struct sdma_engine *sde;
1015 u16 descq_cnt;
1016 void *curr_head;
1017 struct hfi1_pportdata *ppd = dd->pport + port;
1018 u32 per_sdma_credits;
1019 uint idle_cnt = sdma_idle_cnt;
1020 size_t num_engines = dd->chip_sdma_engines;
1021
1022 if (!HFI1_CAP_IS_KSET(SDMA)) {
1023 HFI1_CAP_CLEAR(SDMA_AHG);
1024 return 0;
1025 }
1026 if (mod_num_sdma &&
1027 /* can't exceed chip support */
1028 mod_num_sdma <= dd->chip_sdma_engines &&
1029 /* count must be >= vls */
1030 mod_num_sdma >= num_vls)
1031 num_engines = mod_num_sdma;
1032
1033 dd_dev_info(dd, "SDMA mod_num_sdma: %u\n", mod_num_sdma);
1034 dd_dev_info(dd, "SDMA chip_sdma_engines: %u\n", dd->chip_sdma_engines);
1035 dd_dev_info(dd, "SDMA chip_sdma_mem_size: %u\n",
1036 dd->chip_sdma_mem_size);
1037
1038 per_sdma_credits =
1039 dd->chip_sdma_mem_size/(num_engines * SDMA_BLOCK_SIZE);
1040
1041 /* set up freeze waitqueue */
1042 init_waitqueue_head(&dd->sdma_unfreeze_wq);
1043 atomic_set(&dd->sdma_unfreeze_count, 0);
1044
1045 descq_cnt = sdma_get_descq_cnt();
1046 dd_dev_info(dd, "SDMA engines %zu descq_cnt %u\n",
1047 num_engines, descq_cnt);
1048
1049 /* alloc memory for array of send engines */
1050 dd->per_sdma = kcalloc(num_engines, sizeof(*dd->per_sdma), GFP_KERNEL);
1051 if (!dd->per_sdma)
1052 return -ENOMEM;
1053
1054 idle_cnt = ns_to_cclock(dd, idle_cnt);
1055 if (!sdma_desct_intr)
1056 sdma_desct_intr = SDMA_DESC_INTR;
1057
1058 /* Allocate memory for SendDMA descriptor FIFOs */
1059 for (this_idx = 0; this_idx < num_engines; ++this_idx) {
1060 sde = &dd->per_sdma[this_idx];
1061 sde->dd = dd;
1062 sde->ppd = ppd;
1063 sde->this_idx = this_idx;
1064 sde->descq_cnt = descq_cnt;
1065 sde->desc_avail = sdma_descq_freecnt(sde);
1066 sde->sdma_shift = ilog2(descq_cnt);
1067 sde->sdma_mask = (1 << sde->sdma_shift) - 1;
1068 sde->descq_full_count = 0;
1069
1070 /* Create a mask for all 3 chip interrupt sources */
1071 sde->imask = (u64)1 << (0*TXE_NUM_SDMA_ENGINES + this_idx)
1072 | (u64)1 << (1*TXE_NUM_SDMA_ENGINES + this_idx)
1073 | (u64)1 << (2*TXE_NUM_SDMA_ENGINES + this_idx);
1074 /* Create a mask specifically for sdma_idle */
1075 sde->idle_mask =
1076 (u64)1 << (2*TXE_NUM_SDMA_ENGINES + this_idx);
1077 /* Create a mask specifically for sdma_progress */
1078 sde->progress_mask =
1079 (u64)1 << (TXE_NUM_SDMA_ENGINES + this_idx);
1080 spin_lock_init(&sde->tail_lock);
1081 seqlock_init(&sde->head_lock);
1082 spin_lock_init(&sde->senddmactrl_lock);
1083 spin_lock_init(&sde->flushlist_lock);
1084 /* insure there is always a zero bit */
1085 sde->ahg_bits = 0xfffffffe00000000ULL;
1086
1087 sdma_set_state(sde, sdma_state_s00_hw_down);
1088
1089 /* set up reference counting */
1090 kref_init(&sde->state.kref);
1091 init_completion(&sde->state.comp);
1092
1093 INIT_LIST_HEAD(&sde->flushlist);
1094 INIT_LIST_HEAD(&sde->dmawait);
1095
1096 sde->tail_csr =
1097 get_kctxt_csr_addr(dd, this_idx, SD(TAIL));
1098
1099 if (idle_cnt)
1100 dd->default_desc1 =
1101 SDMA_DESC1_HEAD_TO_HOST_FLAG;
1102 else
1103 dd->default_desc1 =
1104 SDMA_DESC1_INT_REQ_FLAG;
1105
1106 tasklet_init(&sde->sdma_hw_clean_up_task, sdma_hw_clean_up_task,
1107 (unsigned long)sde);
1108
1109 tasklet_init(&sde->sdma_sw_clean_up_task, sdma_sw_clean_up_task,
1110 (unsigned long)sde);
1111 INIT_WORK(&sde->err_halt_worker, sdma_err_halt_wait);
1112 INIT_WORK(&sde->flush_worker, sdma_field_flush);
1113
1114 sde->progress_check_head = 0;
1115
1116 setup_timer(&sde->err_progress_check_timer,
1117 sdma_err_progress_check, (unsigned long)sde);
1118
1119 sde->descq = dma_zalloc_coherent(
1120 &dd->pcidev->dev,
1121 descq_cnt * sizeof(u64[2]),
1122 &sde->descq_phys,
1123 GFP_KERNEL
1124 );
1125 if (!sde->descq)
1126 goto bail;
1127 sde->tx_ring =
1128 kcalloc(descq_cnt, sizeof(struct sdma_txreq *),
1129 GFP_KERNEL);
1130 if (!sde->tx_ring)
1131 sde->tx_ring =
1132 vzalloc(
1133 sizeof(struct sdma_txreq *) *
1134 descq_cnt);
1135 if (!sde->tx_ring)
1136 goto bail;
1137 }
1138
1139 dd->sdma_heads_size = L1_CACHE_BYTES * num_engines;
1140 /* Allocate memory for DMA of head registers to memory */
1141 dd->sdma_heads_dma = dma_zalloc_coherent(
1142 &dd->pcidev->dev,
1143 dd->sdma_heads_size,
1144 &dd->sdma_heads_phys,
1145 GFP_KERNEL
1146 );
1147 if (!dd->sdma_heads_dma) {
1148 dd_dev_err(dd, "failed to allocate SendDMA head memory\n");
1149 goto bail;
1150 }
1151
1152 /* Allocate memory for pad */
1153 dd->sdma_pad_dma = dma_zalloc_coherent(
1154 &dd->pcidev->dev,
1155 sizeof(u32),
1156 &dd->sdma_pad_phys,
1157 GFP_KERNEL
1158 );
1159 if (!dd->sdma_pad_dma) {
1160 dd_dev_err(dd, "failed to allocate SendDMA pad memory\n");
1161 goto bail;
1162 }
1163
1164 /* assign each engine to different cacheline and init registers */
1165 curr_head = (void *)dd->sdma_heads_dma;
1166 for (this_idx = 0; this_idx < num_engines; ++this_idx) {
1167 unsigned long phys_offset;
1168
1169 sde = &dd->per_sdma[this_idx];
1170
1171 sde->head_dma = curr_head;
1172 curr_head += L1_CACHE_BYTES;
1173 phys_offset = (unsigned long)sde->head_dma -
1174 (unsigned long)dd->sdma_heads_dma;
1175 sde->head_phys = dd->sdma_heads_phys + phys_offset;
1176 init_sdma_regs(sde, per_sdma_credits, idle_cnt);
1177 }
1178 dd->flags |= HFI1_HAS_SEND_DMA;
1179 dd->flags |= idle_cnt ? HFI1_HAS_SDMA_TIMEOUT : 0;
1180 dd->num_sdma = num_engines;
1181 if (sdma_map_init(dd, port, ppd->vls_operational, NULL))
1182 goto bail;
1183 dd_dev_info(dd, "SDMA num_sdma: %u\n", dd->num_sdma);
1184 return 0;
1185
1186 bail:
1187 sdma_clean(dd, num_engines);
1188 return -ENOMEM;
1189 }
1190
1191 /**
1192 * sdma_all_running() - called when the link goes up
1193 * @dd: hfi1_devdata
1194 *
1195 * This routine moves all engines to the running state.
1196 */
sdma_all_running(struct hfi1_devdata * dd)1197 void sdma_all_running(struct hfi1_devdata *dd)
1198 {
1199 struct sdma_engine *sde;
1200 unsigned int i;
1201
1202 /* move all engines to running */
1203 for (i = 0; i < dd->num_sdma; ++i) {
1204 sde = &dd->per_sdma[i];
1205 sdma_process_event(sde, sdma_event_e30_go_running);
1206 }
1207 }
1208
1209 /**
1210 * sdma_all_idle() - called when the link goes down
1211 * @dd: hfi1_devdata
1212 *
1213 * This routine moves all engines to the idle state.
1214 */
sdma_all_idle(struct hfi1_devdata * dd)1215 void sdma_all_idle(struct hfi1_devdata *dd)
1216 {
1217 struct sdma_engine *sde;
1218 unsigned int i;
1219
1220 /* idle all engines */
1221 for (i = 0; i < dd->num_sdma; ++i) {
1222 sde = &dd->per_sdma[i];
1223 sdma_process_event(sde, sdma_event_e70_go_idle);
1224 }
1225 }
1226
1227 /**
1228 * sdma_start() - called to kick off state processing for all engines
1229 * @dd: hfi1_devdata
1230 *
1231 * This routine is for kicking off the state processing for all required
1232 * sdma engines. Interrupts need to be working at this point.
1233 *
1234 */
sdma_start(struct hfi1_devdata * dd)1235 void sdma_start(struct hfi1_devdata *dd)
1236 {
1237 unsigned i;
1238 struct sdma_engine *sde;
1239
1240 /* kick off the engines state processing */
1241 for (i = 0; i < dd->num_sdma; ++i) {
1242 sde = &dd->per_sdma[i];
1243 sdma_process_event(sde, sdma_event_e10_go_hw_start);
1244 }
1245 }
1246
1247 /**
1248 * sdma_exit() - used when module is removed
1249 * @dd: hfi1_devdata
1250 */
sdma_exit(struct hfi1_devdata * dd)1251 void sdma_exit(struct hfi1_devdata *dd)
1252 {
1253 unsigned this_idx;
1254 struct sdma_engine *sde;
1255
1256 for (this_idx = 0; dd->per_sdma && this_idx < dd->num_sdma;
1257 ++this_idx) {
1258
1259 sde = &dd->per_sdma[this_idx];
1260 if (!list_empty(&sde->dmawait))
1261 dd_dev_err(dd, "sde %u: dmawait list not empty!\n",
1262 sde->this_idx);
1263 sdma_process_event(sde, sdma_event_e00_go_hw_down);
1264
1265 del_timer_sync(&sde->err_progress_check_timer);
1266
1267 /*
1268 * This waits for the state machine to exit so it is not
1269 * necessary to kill the sdma_sw_clean_up_task to make sure
1270 * it is not running.
1271 */
1272 sdma_finalput(&sde->state);
1273 }
1274 sdma_clean(dd, dd->num_sdma);
1275 }
1276
1277 /*
1278 * unmap the indicated descriptor
1279 */
sdma_unmap_desc(struct hfi1_devdata * dd,struct sdma_desc * descp)1280 static inline void sdma_unmap_desc(
1281 struct hfi1_devdata *dd,
1282 struct sdma_desc *descp)
1283 {
1284 switch (sdma_mapping_type(descp)) {
1285 case SDMA_MAP_SINGLE:
1286 dma_unmap_single(
1287 &dd->pcidev->dev,
1288 sdma_mapping_addr(descp),
1289 sdma_mapping_len(descp),
1290 DMA_TO_DEVICE);
1291 break;
1292 case SDMA_MAP_PAGE:
1293 dma_unmap_page(
1294 &dd->pcidev->dev,
1295 sdma_mapping_addr(descp),
1296 sdma_mapping_len(descp),
1297 DMA_TO_DEVICE);
1298 break;
1299 }
1300 }
1301
1302 /*
1303 * return the mode as indicated by the first
1304 * descriptor in the tx.
1305 */
ahg_mode(struct sdma_txreq * tx)1306 static inline u8 ahg_mode(struct sdma_txreq *tx)
1307 {
1308 return (tx->descp[0].qw[1] & SDMA_DESC1_HEADER_MODE_SMASK)
1309 >> SDMA_DESC1_HEADER_MODE_SHIFT;
1310 }
1311
1312 /**
1313 * sdma_txclean() - clean tx of mappings, descp *kmalloc's
1314 * @dd: hfi1_devdata for unmapping
1315 * @tx: tx request to clean
1316 *
1317 * This is used in the progress routine to clean the tx or
1318 * by the ULP to toss an in-process tx build.
1319 *
1320 * The code can be called multiple times without issue.
1321 *
1322 */
sdma_txclean(struct hfi1_devdata * dd,struct sdma_txreq * tx)1323 void sdma_txclean(
1324 struct hfi1_devdata *dd,
1325 struct sdma_txreq *tx)
1326 {
1327 u16 i;
1328
1329 if (tx->num_desc) {
1330 u8 skip = 0, mode = ahg_mode(tx);
1331
1332 /* unmap first */
1333 sdma_unmap_desc(dd, &tx->descp[0]);
1334 /* determine number of AHG descriptors to skip */
1335 if (mode > SDMA_AHG_APPLY_UPDATE1)
1336 skip = mode >> 1;
1337 for (i = 1 + skip; i < tx->num_desc; i++)
1338 sdma_unmap_desc(dd, &tx->descp[i]);
1339 tx->num_desc = 0;
1340 }
1341 kfree(tx->coalesce_buf);
1342 tx->coalesce_buf = NULL;
1343 /* kmalloc'ed descp */
1344 if (unlikely(tx->desc_limit > ARRAY_SIZE(tx->descs))) {
1345 tx->desc_limit = ARRAY_SIZE(tx->descs);
1346 kfree(tx->descp);
1347 }
1348 }
1349
sdma_gethead(struct sdma_engine * sde)1350 static inline u16 sdma_gethead(struct sdma_engine *sde)
1351 {
1352 struct hfi1_devdata *dd = sde->dd;
1353 int use_dmahead;
1354 u16 hwhead;
1355
1356 #ifdef CONFIG_SDMA_VERBOSITY
1357 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1358 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1359 #endif
1360
1361 retry:
1362 use_dmahead = HFI1_CAP_IS_KSET(USE_SDMA_HEAD) && __sdma_running(sde) &&
1363 (dd->flags & HFI1_HAS_SDMA_TIMEOUT);
1364 hwhead = use_dmahead ?
1365 (u16) le64_to_cpu(*sde->head_dma) :
1366 (u16) read_sde_csr(sde, SD(HEAD));
1367
1368 if (unlikely(HFI1_CAP_IS_KSET(SDMA_HEAD_CHECK))) {
1369 u16 cnt;
1370 u16 swtail;
1371 u16 swhead;
1372 int sane;
1373
1374 swhead = sde->descq_head & sde->sdma_mask;
1375 /* this code is really bad for cache line trading */
1376 swtail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask;
1377 cnt = sde->descq_cnt;
1378
1379 if (swhead < swtail)
1380 /* not wrapped */
1381 sane = (hwhead >= swhead) & (hwhead <= swtail);
1382 else if (swhead > swtail)
1383 /* wrapped around */
1384 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
1385 (hwhead <= swtail);
1386 else
1387 /* empty */
1388 sane = (hwhead == swhead);
1389
1390 if (unlikely(!sane)) {
1391 dd_dev_err(dd, "SDMA(%u) bad head (%s) hwhd=%hu swhd=%hu swtl=%hu cnt=%hu\n",
1392 sde->this_idx,
1393 use_dmahead ? "dma" : "kreg",
1394 hwhead, swhead, swtail, cnt);
1395 if (use_dmahead) {
1396 /* try one more time, using csr */
1397 use_dmahead = 0;
1398 goto retry;
1399 }
1400 /* proceed as if no progress */
1401 hwhead = swhead;
1402 }
1403 }
1404 return hwhead;
1405 }
1406
1407 /*
1408 * This is called when there are send DMA descriptors that might be
1409 * available.
1410 *
1411 * This is called with head_lock held.
1412 */
sdma_desc_avail(struct sdma_engine * sde,unsigned avail)1413 static void sdma_desc_avail(struct sdma_engine *sde, unsigned avail)
1414 {
1415 struct iowait *wait, *nw;
1416 struct iowait *waits[SDMA_WAIT_BATCH_SIZE];
1417 unsigned i, n = 0, seq;
1418 struct sdma_txreq *stx;
1419 struct hfi1_ibdev *dev = &sde->dd->verbs_dev;
1420
1421 #ifdef CONFIG_SDMA_VERBOSITY
1422 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n", sde->this_idx,
1423 slashstrip(__FILE__), __LINE__, __func__);
1424 dd_dev_err(sde->dd, "avail: %u\n", avail);
1425 #endif
1426
1427 do {
1428 seq = read_seqbegin(&dev->iowait_lock);
1429 if (!list_empty(&sde->dmawait)) {
1430 /* at least one item */
1431 write_seqlock(&dev->iowait_lock);
1432 /* Harvest waiters wanting DMA descriptors */
1433 list_for_each_entry_safe(
1434 wait,
1435 nw,
1436 &sde->dmawait,
1437 list) {
1438 u16 num_desc = 0;
1439
1440 if (!wait->wakeup)
1441 continue;
1442 if (n == ARRAY_SIZE(waits))
1443 break;
1444 if (!list_empty(&wait->tx_head)) {
1445 stx = list_first_entry(
1446 &wait->tx_head,
1447 struct sdma_txreq,
1448 list);
1449 num_desc = stx->num_desc;
1450 }
1451 if (num_desc > avail)
1452 break;
1453 avail -= num_desc;
1454 list_del_init(&wait->list);
1455 waits[n++] = wait;
1456 }
1457 write_sequnlock(&dev->iowait_lock);
1458 break;
1459 }
1460 } while (read_seqretry(&dev->iowait_lock, seq));
1461
1462 for (i = 0; i < n; i++)
1463 waits[i]->wakeup(waits[i], SDMA_AVAIL_REASON);
1464 }
1465
1466 /* head_lock must be held */
sdma_make_progress(struct sdma_engine * sde,u64 status)1467 static void sdma_make_progress(struct sdma_engine *sde, u64 status)
1468 {
1469 struct sdma_txreq *txp = NULL;
1470 int progress = 0;
1471 u16 hwhead, swhead, swtail;
1472 int idle_check_done = 0;
1473
1474 hwhead = sdma_gethead(sde);
1475
1476 /* The reason for some of the complexity of this code is that
1477 * not all descriptors have corresponding txps. So, we have to
1478 * be able to skip over descs until we wander into the range of
1479 * the next txp on the list.
1480 */
1481
1482 retry:
1483 txp = get_txhead(sde);
1484 swhead = sde->descq_head & sde->sdma_mask;
1485 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp);
1486 while (swhead != hwhead) {
1487 /* advance head, wrap if needed */
1488 swhead = ++sde->descq_head & sde->sdma_mask;
1489
1490 /* if now past this txp's descs, do the callback */
1491 if (txp && txp->next_descq_idx == swhead) {
1492 int drained = 0;
1493 /* protect against complete modifying */
1494 struct iowait *wait = txp->wait;
1495
1496 /* remove from list */
1497 sde->tx_ring[sde->tx_head++ & sde->sdma_mask] = NULL;
1498 if (wait)
1499 drained = atomic_dec_and_test(&wait->sdma_busy);
1500 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
1501 trace_hfi1_sdma_out_sn(sde, txp->sn);
1502 if (WARN_ON_ONCE(sde->head_sn != txp->sn))
1503 dd_dev_err(sde->dd, "expected %llu got %llu\n",
1504 sde->head_sn, txp->sn);
1505 sde->head_sn++;
1506 #endif
1507 sdma_txclean(sde->dd, txp);
1508 if (txp->complete)
1509 (*txp->complete)(
1510 txp,
1511 SDMA_TXREQ_S_OK,
1512 drained);
1513 if (wait && drained)
1514 iowait_drain_wakeup(wait);
1515 /* see if there is another txp */
1516 txp = get_txhead(sde);
1517 }
1518 trace_hfi1_sdma_progress(sde, hwhead, swhead, txp);
1519 progress++;
1520 }
1521
1522 /*
1523 * The SDMA idle interrupt is not guaranteed to be ordered with respect
1524 * to updates to the the dma_head location in host memory. The head
1525 * value read might not be fully up to date. If there are pending
1526 * descriptors and the SDMA idle interrupt fired then read from the
1527 * CSR SDMA head instead to get the latest value from the hardware.
1528 * The hardware SDMA head should be read at most once in this invocation
1529 * of sdma_make_progress(..) which is ensured by idle_check_done flag
1530 */
1531 if ((status & sde->idle_mask) && !idle_check_done) {
1532 swtail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask;
1533 if (swtail != hwhead) {
1534 hwhead = (u16)read_sde_csr(sde, SD(HEAD));
1535 idle_check_done = 1;
1536 goto retry;
1537 }
1538 }
1539
1540 sde->last_status = status;
1541 if (progress)
1542 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
1543 }
1544
1545 /*
1546 * sdma_engine_interrupt() - interrupt handler for engine
1547 * @sde: sdma engine
1548 * @status: sdma interrupt reason
1549 *
1550 * Status is a mask of the 3 possible interrupts for this engine. It will
1551 * contain bits _only_ for this SDMA engine. It will contain at least one
1552 * bit, it may contain more.
1553 */
sdma_engine_interrupt(struct sdma_engine * sde,u64 status)1554 void sdma_engine_interrupt(struct sdma_engine *sde, u64 status)
1555 {
1556 trace_hfi1_sdma_engine_interrupt(sde, status);
1557 write_seqlock(&sde->head_lock);
1558 sdma_set_desc_cnt(sde, sdma_desct_intr);
1559 sdma_make_progress(sde, status);
1560 write_sequnlock(&sde->head_lock);
1561 }
1562
1563 /**
1564 * sdma_engine_error() - error handler for engine
1565 * @sde: sdma engine
1566 * @status: sdma interrupt reason
1567 */
sdma_engine_error(struct sdma_engine * sde,u64 status)1568 void sdma_engine_error(struct sdma_engine *sde, u64 status)
1569 {
1570 unsigned long flags;
1571
1572 #ifdef CONFIG_SDMA_VERBOSITY
1573 dd_dev_err(sde->dd, "CONFIG SDMA(%u) error status 0x%llx state %s\n",
1574 sde->this_idx,
1575 (unsigned long long)status,
1576 sdma_state_names[sde->state.current_state]);
1577 #endif
1578 spin_lock_irqsave(&sde->tail_lock, flags);
1579 write_seqlock(&sde->head_lock);
1580 if (status & ALL_SDMA_ENG_HALT_ERRS)
1581 __sdma_process_event(sde, sdma_event_e60_hw_halted);
1582 if (status & ~SD(ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK)) {
1583 dd_dev_err(sde->dd,
1584 "SDMA (%u) engine error: 0x%llx state %s\n",
1585 sde->this_idx,
1586 (unsigned long long)status,
1587 sdma_state_names[sde->state.current_state]);
1588 dump_sdma_state(sde);
1589 }
1590 write_sequnlock(&sde->head_lock);
1591 spin_unlock_irqrestore(&sde->tail_lock, flags);
1592 }
1593
sdma_sendctrl(struct sdma_engine * sde,unsigned op)1594 static void sdma_sendctrl(struct sdma_engine *sde, unsigned op)
1595 {
1596 u64 set_senddmactrl = 0;
1597 u64 clr_senddmactrl = 0;
1598 unsigned long flags;
1599
1600 #ifdef CONFIG_SDMA_VERBOSITY
1601 dd_dev_err(sde->dd, "CONFIG SDMA(%u) senddmactrl E=%d I=%d H=%d C=%d\n",
1602 sde->this_idx,
1603 (op & SDMA_SENDCTRL_OP_ENABLE) ? 1 : 0,
1604 (op & SDMA_SENDCTRL_OP_INTENABLE) ? 1 : 0,
1605 (op & SDMA_SENDCTRL_OP_HALT) ? 1 : 0,
1606 (op & SDMA_SENDCTRL_OP_CLEANUP) ? 1 : 0);
1607 #endif
1608
1609 if (op & SDMA_SENDCTRL_OP_ENABLE)
1610 set_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK);
1611 else
1612 clr_senddmactrl |= SD(CTRL_SDMA_ENABLE_SMASK);
1613
1614 if (op & SDMA_SENDCTRL_OP_INTENABLE)
1615 set_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK);
1616 else
1617 clr_senddmactrl |= SD(CTRL_SDMA_INT_ENABLE_SMASK);
1618
1619 if (op & SDMA_SENDCTRL_OP_HALT)
1620 set_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK);
1621 else
1622 clr_senddmactrl |= SD(CTRL_SDMA_HALT_SMASK);
1623
1624 spin_lock_irqsave(&sde->senddmactrl_lock, flags);
1625
1626 sde->p_senddmactrl |= set_senddmactrl;
1627 sde->p_senddmactrl &= ~clr_senddmactrl;
1628
1629 if (op & SDMA_SENDCTRL_OP_CLEANUP)
1630 write_sde_csr(sde, SD(CTRL),
1631 sde->p_senddmactrl |
1632 SD(CTRL_SDMA_CLEANUP_SMASK));
1633 else
1634 write_sde_csr(sde, SD(CTRL), sde->p_senddmactrl);
1635
1636 spin_unlock_irqrestore(&sde->senddmactrl_lock, flags);
1637
1638 #ifdef CONFIG_SDMA_VERBOSITY
1639 sdma_dumpstate(sde);
1640 #endif
1641 }
1642
sdma_setlengen(struct sdma_engine * sde)1643 static void sdma_setlengen(struct sdma_engine *sde)
1644 {
1645 #ifdef CONFIG_SDMA_VERBOSITY
1646 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1647 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1648 #endif
1649
1650 /*
1651 * Set SendDmaLenGen and clear-then-set the MSB of the generation
1652 * count to enable generation checking and load the internal
1653 * generation counter.
1654 */
1655 write_sde_csr(sde, SD(LEN_GEN),
1656 (sde->descq_cnt/64) << SD(LEN_GEN_LENGTH_SHIFT)
1657 );
1658 write_sde_csr(sde, SD(LEN_GEN),
1659 ((sde->descq_cnt/64) << SD(LEN_GEN_LENGTH_SHIFT))
1660 | (4ULL << SD(LEN_GEN_GENERATION_SHIFT))
1661 );
1662 }
1663
sdma_update_tail(struct sdma_engine * sde,u16 tail)1664 static inline void sdma_update_tail(struct sdma_engine *sde, u16 tail)
1665 {
1666 /* Commit writes to memory and advance the tail on the chip */
1667 smp_wmb(); /* see get_txhead() */
1668 writeq(tail, sde->tail_csr);
1669 }
1670
1671 /*
1672 * This is called when changing to state s10_hw_start_up_halt_wait as
1673 * a result of send buffer errors or send DMA descriptor errors.
1674 */
sdma_hw_start_up(struct sdma_engine * sde)1675 static void sdma_hw_start_up(struct sdma_engine *sde)
1676 {
1677 u64 reg;
1678
1679 #ifdef CONFIG_SDMA_VERBOSITY
1680 dd_dev_err(sde->dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1681 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1682 #endif
1683
1684 sdma_setlengen(sde);
1685 sdma_update_tail(sde, 0); /* Set SendDmaTail */
1686 *sde->head_dma = 0;
1687
1688 reg = SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_MASK) <<
1689 SD(ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SHIFT);
1690 write_sde_csr(sde, SD(ENG_ERR_CLEAR), reg);
1691 }
1692
1693 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
1694 (r &= ~SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
1695
1696 #define SET_STATIC_RATE_CONTROL_SMASK(r) \
1697 (r |= SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
1698 /*
1699 * set_sdma_integrity
1700 *
1701 * Set the SEND_DMA_CHECK_ENABLE register for send DMA engine 'sde'.
1702 */
set_sdma_integrity(struct sdma_engine * sde)1703 static void set_sdma_integrity(struct sdma_engine *sde)
1704 {
1705 struct hfi1_devdata *dd = sde->dd;
1706 u64 reg;
1707
1708 if (unlikely(HFI1_CAP_IS_KSET(NO_INTEGRITY)))
1709 return;
1710
1711 reg = hfi1_pkt_base_sdma_integrity(dd);
1712
1713 if (HFI1_CAP_IS_KSET(STATIC_RATE_CTRL))
1714 CLEAR_STATIC_RATE_CONTROL_SMASK(reg);
1715 else
1716 SET_STATIC_RATE_CONTROL_SMASK(reg);
1717
1718 write_sde_csr(sde, SD(CHECK_ENABLE), reg);
1719 }
1720
1721
init_sdma_regs(struct sdma_engine * sde,u32 credits,uint idle_cnt)1722 static void init_sdma_regs(
1723 struct sdma_engine *sde,
1724 u32 credits,
1725 uint idle_cnt)
1726 {
1727 u8 opval, opmask;
1728 #ifdef CONFIG_SDMA_VERBOSITY
1729 struct hfi1_devdata *dd = sde->dd;
1730
1731 dd_dev_err(dd, "CONFIG SDMA(%u) %s:%d %s()\n",
1732 sde->this_idx, slashstrip(__FILE__), __LINE__, __func__);
1733 #endif
1734
1735 write_sde_csr(sde, SD(BASE_ADDR), sde->descq_phys);
1736 sdma_setlengen(sde);
1737 sdma_update_tail(sde, 0); /* Set SendDmaTail */
1738 write_sde_csr(sde, SD(RELOAD_CNT), idle_cnt);
1739 write_sde_csr(sde, SD(DESC_CNT), 0);
1740 write_sde_csr(sde, SD(HEAD_ADDR), sde->head_phys);
1741 write_sde_csr(sde, SD(MEMORY),
1742 ((u64)credits <<
1743 SD(MEMORY_SDMA_MEMORY_CNT_SHIFT)) |
1744 ((u64)(credits * sde->this_idx) <<
1745 SD(MEMORY_SDMA_MEMORY_INDEX_SHIFT)));
1746 write_sde_csr(sde, SD(ENG_ERR_MASK), ~0ull);
1747 set_sdma_integrity(sde);
1748 opmask = OPCODE_CHECK_MASK_DISABLED;
1749 opval = OPCODE_CHECK_VAL_DISABLED;
1750 write_sde_csr(sde, SD(CHECK_OPCODE),
1751 (opmask << SEND_CTXT_CHECK_OPCODE_MASK_SHIFT) |
1752 (opval << SEND_CTXT_CHECK_OPCODE_VALUE_SHIFT));
1753 }
1754
1755 #ifdef CONFIG_SDMA_VERBOSITY
1756
1757 #define sdma_dumpstate_helper0(reg) do { \
1758 csr = read_csr(sde->dd, reg); \
1759 dd_dev_err(sde->dd, "%36s 0x%016llx\n", #reg, csr); \
1760 } while (0)
1761
1762 #define sdma_dumpstate_helper(reg) do { \
1763 csr = read_sde_csr(sde, reg); \
1764 dd_dev_err(sde->dd, "%36s[%02u] 0x%016llx\n", \
1765 #reg, sde->this_idx, csr); \
1766 } while (0)
1767
1768 #define sdma_dumpstate_helper2(reg) do { \
1769 csr = read_csr(sde->dd, reg + (8 * i)); \
1770 dd_dev_err(sde->dd, "%33s_%02u 0x%016llx\n", \
1771 #reg, i, csr); \
1772 } while (0)
1773
sdma_dumpstate(struct sdma_engine * sde)1774 void sdma_dumpstate(struct sdma_engine *sde)
1775 {
1776 u64 csr;
1777 unsigned i;
1778
1779 sdma_dumpstate_helper(SD(CTRL));
1780 sdma_dumpstate_helper(SD(STATUS));
1781 sdma_dumpstate_helper0(SD(ERR_STATUS));
1782 sdma_dumpstate_helper0(SD(ERR_MASK));
1783 sdma_dumpstate_helper(SD(ENG_ERR_STATUS));
1784 sdma_dumpstate_helper(SD(ENG_ERR_MASK));
1785
1786 for (i = 0; i < CCE_NUM_INT_CSRS; ++i) {
1787 sdma_dumpstate_helper2(CCE_INT_STATUS);
1788 sdma_dumpstate_helper2(CCE_INT_MASK);
1789 sdma_dumpstate_helper2(CCE_INT_BLOCKED);
1790 }
1791
1792 sdma_dumpstate_helper(SD(TAIL));
1793 sdma_dumpstate_helper(SD(HEAD));
1794 sdma_dumpstate_helper(SD(PRIORITY_THLD));
1795 sdma_dumpstate_helper(SD(IDLE_CNT));
1796 sdma_dumpstate_helper(SD(RELOAD_CNT));
1797 sdma_dumpstate_helper(SD(DESC_CNT));
1798 sdma_dumpstate_helper(SD(DESC_FETCHED_CNT));
1799 sdma_dumpstate_helper(SD(MEMORY));
1800 sdma_dumpstate_helper0(SD(ENGINES));
1801 sdma_dumpstate_helper0(SD(MEM_SIZE));
1802 /* sdma_dumpstate_helper(SEND_EGRESS_SEND_DMA_STATUS); */
1803 sdma_dumpstate_helper(SD(BASE_ADDR));
1804 sdma_dumpstate_helper(SD(LEN_GEN));
1805 sdma_dumpstate_helper(SD(HEAD_ADDR));
1806 sdma_dumpstate_helper(SD(CHECK_ENABLE));
1807 sdma_dumpstate_helper(SD(CHECK_VL));
1808 sdma_dumpstate_helper(SD(CHECK_JOB_KEY));
1809 sdma_dumpstate_helper(SD(CHECK_PARTITION_KEY));
1810 sdma_dumpstate_helper(SD(CHECK_SLID));
1811 sdma_dumpstate_helper(SD(CHECK_OPCODE));
1812 }
1813 #endif
1814
dump_sdma_state(struct sdma_engine * sde)1815 static void dump_sdma_state(struct sdma_engine *sde)
1816 {
1817 struct hw_sdma_desc *descq;
1818 struct hw_sdma_desc *descqp;
1819 u64 desc[2];
1820 u64 addr;
1821 u8 gen;
1822 u16 len;
1823 u16 head, tail, cnt;
1824
1825 head = sde->descq_head & sde->sdma_mask;
1826 tail = sde->descq_tail & sde->sdma_mask;
1827 cnt = sdma_descq_freecnt(sde);
1828 descq = sde->descq;
1829
1830 dd_dev_err(sde->dd,
1831 "SDMA (%u) descq_head: %u descq_tail: %u freecnt: %u FLE %d\n",
1832 sde->this_idx,
1833 head,
1834 tail,
1835 cnt,
1836 !list_empty(&sde->flushlist));
1837
1838 /* print info for each entry in the descriptor queue */
1839 while (head != tail) {
1840 char flags[6] = { 'x', 'x', 'x', 'x', 0 };
1841
1842 descqp = &sde->descq[head];
1843 desc[0] = le64_to_cpu(descqp->qw[0]);
1844 desc[1] = le64_to_cpu(descqp->qw[1]);
1845 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-';
1846 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ?
1847 'H' : '-';
1848 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-';
1849 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-';
1850 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT)
1851 & SDMA_DESC0_PHY_ADDR_MASK;
1852 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT)
1853 & SDMA_DESC1_GENERATION_MASK;
1854 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT)
1855 & SDMA_DESC0_BYTE_COUNT_MASK;
1856 dd_dev_err(sde->dd,
1857 "SDMA sdmadesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
1858 head, flags, addr, gen, len);
1859 dd_dev_err(sde->dd,
1860 "\tdesc0:0x%016llx desc1 0x%016llx\n",
1861 desc[0], desc[1]);
1862 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG)
1863 dd_dev_err(sde->dd,
1864 "\taidx: %u amode: %u alen: %u\n",
1865 (u8)((desc[1] & SDMA_DESC1_HEADER_INDEX_SMASK)
1866 >> SDMA_DESC1_HEADER_INDEX_SHIFT),
1867 (u8)((desc[1] & SDMA_DESC1_HEADER_MODE_SMASK)
1868 >> SDMA_DESC1_HEADER_MODE_SHIFT),
1869 (u8)((desc[1] & SDMA_DESC1_HEADER_DWS_SMASK)
1870 >> SDMA_DESC1_HEADER_DWS_SHIFT));
1871 head++;
1872 head &= sde->sdma_mask;
1873 }
1874 }
1875
1876 #define SDE_FMT \
1877 "SDE %u STE %s C 0x%llx S 0x%016llx E 0x%llx T(HW) 0x%llx T(SW) 0x%x H(HW) 0x%llx H(SW) 0x%x H(D) 0x%llx DM 0x%llx GL 0x%llx R 0x%llx LIS 0x%llx AHGI 0x%llx TXT %u TXH %u DT %u DH %u FLNE %d DQF %u SLC 0x%llx\n"
1878 /**
1879 * sdma_seqfile_dump_sde() - debugfs dump of sde
1880 * @s: seq file
1881 * @sde: send dma engine to dump
1882 *
1883 * This routine dumps the sde to the indicated seq file.
1884 */
sdma_seqfile_dump_sde(struct seq_file * s,struct sdma_engine * sde)1885 void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *sde)
1886 {
1887 u16 head, tail;
1888 struct hw_sdma_desc *descqp;
1889 u64 desc[2];
1890 u64 addr;
1891 u8 gen;
1892 u16 len;
1893
1894 head = sde->descq_head & sde->sdma_mask;
1895 tail = ACCESS_ONCE(sde->descq_tail) & sde->sdma_mask;
1896 seq_printf(s, SDE_FMT, sde->this_idx,
1897 sdma_state_name(sde->state.current_state),
1898 (unsigned long long)read_sde_csr(sde, SD(CTRL)),
1899 (unsigned long long)read_sde_csr(sde, SD(STATUS)),
1900 (unsigned long long)read_sde_csr(sde,
1901 SD(ENG_ERR_STATUS)),
1902 (unsigned long long)read_sde_csr(sde, SD(TAIL)),
1903 tail,
1904 (unsigned long long)read_sde_csr(sde, SD(HEAD)),
1905 head,
1906 (unsigned long long)le64_to_cpu(*sde->head_dma),
1907 (unsigned long long)read_sde_csr(sde, SD(MEMORY)),
1908 (unsigned long long)read_sde_csr(sde, SD(LEN_GEN)),
1909 (unsigned long long)read_sde_csr(sde, SD(RELOAD_CNT)),
1910 (unsigned long long)sde->last_status,
1911 (unsigned long long)sde->ahg_bits,
1912 sde->tx_tail,
1913 sde->tx_head,
1914 sde->descq_tail,
1915 sde->descq_head,
1916 !list_empty(&sde->flushlist),
1917 sde->descq_full_count,
1918 (unsigned long long)read_sde_csr(sde, SEND_DMA_CHECK_SLID));
1919
1920 /* print info for each entry in the descriptor queue */
1921 while (head != tail) {
1922 char flags[6] = { 'x', 'x', 'x', 'x', 0 };
1923
1924 descqp = &sde->descq[head];
1925 desc[0] = le64_to_cpu(descqp->qw[0]);
1926 desc[1] = le64_to_cpu(descqp->qw[1]);
1927 flags[0] = (desc[1] & SDMA_DESC1_INT_REQ_FLAG) ? 'I' : '-';
1928 flags[1] = (desc[1] & SDMA_DESC1_HEAD_TO_HOST_FLAG) ?
1929 'H' : '-';
1930 flags[2] = (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG) ? 'F' : '-';
1931 flags[3] = (desc[0] & SDMA_DESC0_LAST_DESC_FLAG) ? 'L' : '-';
1932 addr = (desc[0] >> SDMA_DESC0_PHY_ADDR_SHIFT)
1933 & SDMA_DESC0_PHY_ADDR_MASK;
1934 gen = (desc[1] >> SDMA_DESC1_GENERATION_SHIFT)
1935 & SDMA_DESC1_GENERATION_MASK;
1936 len = (desc[0] >> SDMA_DESC0_BYTE_COUNT_SHIFT)
1937 & SDMA_DESC0_BYTE_COUNT_MASK;
1938 seq_printf(s,
1939 "\tdesc[%u]: flags:%s addr:0x%016llx gen:%u len:%u bytes\n",
1940 head, flags, addr, gen, len);
1941 if (desc[0] & SDMA_DESC0_FIRST_DESC_FLAG)
1942 seq_printf(s, "\t\tahgidx: %u ahgmode: %u\n",
1943 (u8)((desc[1] & SDMA_DESC1_HEADER_INDEX_SMASK)
1944 >> SDMA_DESC1_HEADER_INDEX_SHIFT),
1945 (u8)((desc[1] & SDMA_DESC1_HEADER_MODE_SMASK)
1946 >> SDMA_DESC1_HEADER_MODE_SHIFT));
1947 head = (head + 1) & sde->sdma_mask;
1948 }
1949 }
1950
1951 /*
1952 * add the generation number into
1953 * the qw1 and return
1954 */
add_gen(struct sdma_engine * sde,u64 qw1)1955 static inline u64 add_gen(struct sdma_engine *sde, u64 qw1)
1956 {
1957 u8 generation = (sde->descq_tail >> sde->sdma_shift) & 3;
1958
1959 qw1 &= ~SDMA_DESC1_GENERATION_SMASK;
1960 qw1 |= ((u64)generation & SDMA_DESC1_GENERATION_MASK)
1961 << SDMA_DESC1_GENERATION_SHIFT;
1962 return qw1;
1963 }
1964
1965 /*
1966 * This routine submits the indicated tx
1967 *
1968 * Space has already been guaranteed and
1969 * tail side of ring is locked.
1970 *
1971 * The hardware tail update is done
1972 * in the caller and that is facilitated
1973 * by returning the new tail.
1974 *
1975 * There is special case logic for ahg
1976 * to not add the generation number for
1977 * up to 2 descriptors that follow the
1978 * first descriptor.
1979 *
1980 */
submit_tx(struct sdma_engine * sde,struct sdma_txreq * tx)1981 static inline u16 submit_tx(struct sdma_engine *sde, struct sdma_txreq *tx)
1982 {
1983 int i;
1984 u16 tail;
1985 struct sdma_desc *descp = tx->descp;
1986 u8 skip = 0, mode = ahg_mode(tx);
1987
1988 tail = sde->descq_tail & sde->sdma_mask;
1989 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]);
1990 sde->descq[tail].qw[1] = cpu_to_le64(add_gen(sde, descp->qw[1]));
1991 trace_hfi1_sdma_descriptor(sde, descp->qw[0], descp->qw[1],
1992 tail, &sde->descq[tail]);
1993 tail = ++sde->descq_tail & sde->sdma_mask;
1994 descp++;
1995 if (mode > SDMA_AHG_APPLY_UPDATE1)
1996 skip = mode >> 1;
1997 for (i = 1; i < tx->num_desc; i++, descp++) {
1998 u64 qw1;
1999
2000 sde->descq[tail].qw[0] = cpu_to_le64(descp->qw[0]);
2001 if (skip) {
2002 /* edits don't have generation */
2003 qw1 = descp->qw[1];
2004 skip--;
2005 } else {
2006 /* replace generation with real one for non-edits */
2007 qw1 = add_gen(sde, descp->qw[1]);
2008 }
2009 sde->descq[tail].qw[1] = cpu_to_le64(qw1);
2010 trace_hfi1_sdma_descriptor(sde, descp->qw[0], qw1,
2011 tail, &sde->descq[tail]);
2012 tail = ++sde->descq_tail & sde->sdma_mask;
2013 }
2014 tx->next_descq_idx = tail;
2015 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2016 tx->sn = sde->tail_sn++;
2017 trace_hfi1_sdma_in_sn(sde, tx->sn);
2018 WARN_ON_ONCE(sde->tx_ring[sde->tx_tail & sde->sdma_mask]);
2019 #endif
2020 sde->tx_ring[sde->tx_tail++ & sde->sdma_mask] = tx;
2021 sde->desc_avail -= tx->num_desc;
2022 return tail;
2023 }
2024
2025 /*
2026 * Check for progress
2027 */
sdma_check_progress(struct sdma_engine * sde,struct iowait * wait,struct sdma_txreq * tx)2028 static int sdma_check_progress(
2029 struct sdma_engine *sde,
2030 struct iowait *wait,
2031 struct sdma_txreq *tx)
2032 {
2033 int ret;
2034
2035 sde->desc_avail = sdma_descq_freecnt(sde);
2036 if (tx->num_desc <= sde->desc_avail)
2037 return -EAGAIN;
2038 /* pulse the head_lock */
2039 if (wait && wait->sleep) {
2040 unsigned seq;
2041
2042 seq = raw_seqcount_begin(
2043 (const seqcount_t *)&sde->head_lock.seqcount);
2044 ret = wait->sleep(sde, wait, tx, seq);
2045 if (ret == -EAGAIN)
2046 sde->desc_avail = sdma_descq_freecnt(sde);
2047 } else
2048 ret = -EBUSY;
2049 return ret;
2050 }
2051
2052 /**
2053 * sdma_send_txreq() - submit a tx req to ring
2054 * @sde: sdma engine to use
2055 * @wait: wait structure to use when full (may be NULL)
2056 * @tx: sdma_txreq to submit
2057 *
2058 * The call submits the tx into the ring. If a iowait structure is non-NULL
2059 * the packet will be queued to the list in wait.
2060 *
2061 * Return:
2062 * 0 - Success, -EINVAL - sdma_txreq incomplete, -EBUSY - no space in
2063 * ring (wait == NULL)
2064 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state
2065 */
sdma_send_txreq(struct sdma_engine * sde,struct iowait * wait,struct sdma_txreq * tx)2066 int sdma_send_txreq(struct sdma_engine *sde,
2067 struct iowait *wait,
2068 struct sdma_txreq *tx)
2069 {
2070 int ret = 0;
2071 u16 tail;
2072 unsigned long flags;
2073
2074 /* user should have supplied entire packet */
2075 if (unlikely(tx->tlen))
2076 return -EINVAL;
2077 tx->wait = wait;
2078 spin_lock_irqsave(&sde->tail_lock, flags);
2079 retry:
2080 if (unlikely(!__sdma_running(sde)))
2081 goto unlock_noconn;
2082 if (unlikely(tx->num_desc > sde->desc_avail))
2083 goto nodesc;
2084 tail = submit_tx(sde, tx);
2085 if (wait)
2086 atomic_inc(&wait->sdma_busy);
2087 sdma_update_tail(sde, tail);
2088 unlock:
2089 spin_unlock_irqrestore(&sde->tail_lock, flags);
2090 return ret;
2091 unlock_noconn:
2092 if (wait)
2093 atomic_inc(&wait->sdma_busy);
2094 tx->next_descq_idx = 0;
2095 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2096 tx->sn = sde->tail_sn++;
2097 trace_hfi1_sdma_in_sn(sde, tx->sn);
2098 #endif
2099 spin_lock(&sde->flushlist_lock);
2100 list_add_tail(&tx->list, &sde->flushlist);
2101 spin_unlock(&sde->flushlist_lock);
2102 if (wait) {
2103 wait->tx_count++;
2104 wait->count += tx->num_desc;
2105 }
2106 schedule_work(&sde->flush_worker);
2107 ret = -ECOMM;
2108 goto unlock;
2109 nodesc:
2110 ret = sdma_check_progress(sde, wait, tx);
2111 if (ret == -EAGAIN) {
2112 ret = 0;
2113 goto retry;
2114 }
2115 sde->descq_full_count++;
2116 goto unlock;
2117 }
2118
2119 /**
2120 * sdma_send_txlist() - submit a list of tx req to ring
2121 * @sde: sdma engine to use
2122 * @wait: wait structure to use when full (may be NULL)
2123 * @tx_list: list of sdma_txreqs to submit
2124 *
2125 * The call submits the list into the ring.
2126 *
2127 * If the iowait structure is non-NULL and not equal to the iowait list
2128 * the unprocessed part of the list will be appended to the list in wait.
2129 *
2130 * In all cases, the tx_list will be updated so the head of the tx_list is
2131 * the list of descriptors that have yet to be transmitted.
2132 *
2133 * The intent of this call is to provide a more efficient
2134 * way of submitting multiple packets to SDMA while holding the tail
2135 * side locking.
2136 *
2137 * Return:
2138 * 0 - Success, -EINVAL - sdma_txreq incomplete, -EBUSY - no space in ring
2139 * (wait == NULL)
2140 * -EIOCBQUEUED - tx queued to iowait, -ECOMM bad sdma state
2141 */
sdma_send_txlist(struct sdma_engine * sde,struct iowait * wait,struct list_head * tx_list)2142 int sdma_send_txlist(struct sdma_engine *sde,
2143 struct iowait *wait,
2144 struct list_head *tx_list)
2145 {
2146 struct sdma_txreq *tx, *tx_next;
2147 int ret = 0;
2148 unsigned long flags;
2149 u16 tail = INVALID_TAIL;
2150 int count = 0;
2151
2152 spin_lock_irqsave(&sde->tail_lock, flags);
2153 retry:
2154 list_for_each_entry_safe(tx, tx_next, tx_list, list) {
2155 tx->wait = wait;
2156 if (unlikely(!__sdma_running(sde)))
2157 goto unlock_noconn;
2158 if (unlikely(tx->num_desc > sde->desc_avail))
2159 goto nodesc;
2160 if (unlikely(tx->tlen)) {
2161 ret = -EINVAL;
2162 goto update_tail;
2163 }
2164 list_del_init(&tx->list);
2165 tail = submit_tx(sde, tx);
2166 count++;
2167 if (tail != INVALID_TAIL &&
2168 (count & SDMA_TAIL_UPDATE_THRESH) == 0) {
2169 sdma_update_tail(sde, tail);
2170 tail = INVALID_TAIL;
2171 }
2172 }
2173 update_tail:
2174 if (wait)
2175 atomic_add(count, &wait->sdma_busy);
2176 if (tail != INVALID_TAIL)
2177 sdma_update_tail(sde, tail);
2178 spin_unlock_irqrestore(&sde->tail_lock, flags);
2179 return ret;
2180 unlock_noconn:
2181 spin_lock(&sde->flushlist_lock);
2182 list_for_each_entry_safe(tx, tx_next, tx_list, list) {
2183 tx->wait = wait;
2184 list_del_init(&tx->list);
2185 if (wait)
2186 atomic_inc(&wait->sdma_busy);
2187 tx->next_descq_idx = 0;
2188 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
2189 tx->sn = sde->tail_sn++;
2190 trace_hfi1_sdma_in_sn(sde, tx->sn);
2191 #endif
2192 list_add_tail(&tx->list, &sde->flushlist);
2193 if (wait) {
2194 wait->tx_count++;
2195 wait->count += tx->num_desc;
2196 }
2197 }
2198 spin_unlock(&sde->flushlist_lock);
2199 schedule_work(&sde->flush_worker);
2200 ret = -ECOMM;
2201 goto update_tail;
2202 nodesc:
2203 ret = sdma_check_progress(sde, wait, tx);
2204 if (ret == -EAGAIN) {
2205 ret = 0;
2206 goto retry;
2207 }
2208 sde->descq_full_count++;
2209 goto update_tail;
2210 }
2211
sdma_process_event(struct sdma_engine * sde,enum sdma_events event)2212 static void sdma_process_event(struct sdma_engine *sde,
2213 enum sdma_events event)
2214 {
2215 unsigned long flags;
2216
2217 spin_lock_irqsave(&sde->tail_lock, flags);
2218 write_seqlock(&sde->head_lock);
2219
2220 __sdma_process_event(sde, event);
2221
2222 if (sde->state.current_state == sdma_state_s99_running)
2223 sdma_desc_avail(sde, sdma_descq_freecnt(sde));
2224
2225 write_sequnlock(&sde->head_lock);
2226 spin_unlock_irqrestore(&sde->tail_lock, flags);
2227 }
2228
__sdma_process_event(struct sdma_engine * sde,enum sdma_events event)2229 static void __sdma_process_event(struct sdma_engine *sde,
2230 enum sdma_events event)
2231 {
2232 struct sdma_state *ss = &sde->state;
2233 int need_progress = 0;
2234
2235 /* CONFIG SDMA temporary */
2236 #ifdef CONFIG_SDMA_VERBOSITY
2237 dd_dev_err(sde->dd, "CONFIG SDMA(%u) [%s] %s\n", sde->this_idx,
2238 sdma_state_names[ss->current_state],
2239 sdma_event_names[event]);
2240 #endif
2241
2242 switch (ss->current_state) {
2243 case sdma_state_s00_hw_down:
2244 switch (event) {
2245 case sdma_event_e00_go_hw_down:
2246 break;
2247 case sdma_event_e30_go_running:
2248 /*
2249 * If down, but running requested (usually result
2250 * of link up, then we need to start up.
2251 * This can happen when hw down is requested while
2252 * bringing the link up with traffic active on
2253 * 7220, e.g. */
2254 ss->go_s99_running = 1;
2255 /* fall through and start dma engine */
2256 case sdma_event_e10_go_hw_start:
2257 /* This reference means the state machine is started */
2258 sdma_get(&sde->state);
2259 sdma_set_state(sde,
2260 sdma_state_s10_hw_start_up_halt_wait);
2261 break;
2262 case sdma_event_e15_hw_halt_done:
2263 break;
2264 case sdma_event_e25_hw_clean_up_done:
2265 break;
2266 case sdma_event_e40_sw_cleaned:
2267 sdma_sw_tear_down(sde);
2268 break;
2269 case sdma_event_e50_hw_cleaned:
2270 break;
2271 case sdma_event_e60_hw_halted:
2272 break;
2273 case sdma_event_e70_go_idle:
2274 break;
2275 case sdma_event_e80_hw_freeze:
2276 break;
2277 case sdma_event_e81_hw_frozen:
2278 break;
2279 case sdma_event_e82_hw_unfreeze:
2280 break;
2281 case sdma_event_e85_link_down:
2282 break;
2283 case sdma_event_e90_sw_halted:
2284 break;
2285 }
2286 break;
2287
2288 case sdma_state_s10_hw_start_up_halt_wait:
2289 switch (event) {
2290 case sdma_event_e00_go_hw_down:
2291 sdma_set_state(sde, sdma_state_s00_hw_down);
2292 sdma_sw_tear_down(sde);
2293 break;
2294 case sdma_event_e10_go_hw_start:
2295 break;
2296 case sdma_event_e15_hw_halt_done:
2297 sdma_set_state(sde,
2298 sdma_state_s15_hw_start_up_clean_wait);
2299 sdma_start_hw_clean_up(sde);
2300 break;
2301 case sdma_event_e25_hw_clean_up_done:
2302 break;
2303 case sdma_event_e30_go_running:
2304 ss->go_s99_running = 1;
2305 break;
2306 case sdma_event_e40_sw_cleaned:
2307 break;
2308 case sdma_event_e50_hw_cleaned:
2309 break;
2310 case sdma_event_e60_hw_halted:
2311 sdma_start_err_halt_wait(sde);
2312 break;
2313 case sdma_event_e70_go_idle:
2314 ss->go_s99_running = 0;
2315 break;
2316 case sdma_event_e80_hw_freeze:
2317 break;
2318 case sdma_event_e81_hw_frozen:
2319 break;
2320 case sdma_event_e82_hw_unfreeze:
2321 break;
2322 case sdma_event_e85_link_down:
2323 break;
2324 case sdma_event_e90_sw_halted:
2325 break;
2326 }
2327 break;
2328
2329 case sdma_state_s15_hw_start_up_clean_wait:
2330 switch (event) {
2331 case sdma_event_e00_go_hw_down:
2332 sdma_set_state(sde, sdma_state_s00_hw_down);
2333 sdma_sw_tear_down(sde);
2334 break;
2335 case sdma_event_e10_go_hw_start:
2336 break;
2337 case sdma_event_e15_hw_halt_done:
2338 break;
2339 case sdma_event_e25_hw_clean_up_done:
2340 sdma_hw_start_up(sde);
2341 sdma_set_state(sde, ss->go_s99_running ?
2342 sdma_state_s99_running :
2343 sdma_state_s20_idle);
2344 break;
2345 case sdma_event_e30_go_running:
2346 ss->go_s99_running = 1;
2347 break;
2348 case sdma_event_e40_sw_cleaned:
2349 break;
2350 case sdma_event_e50_hw_cleaned:
2351 break;
2352 case sdma_event_e60_hw_halted:
2353 break;
2354 case sdma_event_e70_go_idle:
2355 ss->go_s99_running = 0;
2356 break;
2357 case sdma_event_e80_hw_freeze:
2358 break;
2359 case sdma_event_e81_hw_frozen:
2360 break;
2361 case sdma_event_e82_hw_unfreeze:
2362 break;
2363 case sdma_event_e85_link_down:
2364 break;
2365 case sdma_event_e90_sw_halted:
2366 break;
2367 }
2368 break;
2369
2370 case sdma_state_s20_idle:
2371 switch (event) {
2372 case sdma_event_e00_go_hw_down:
2373 sdma_set_state(sde, sdma_state_s00_hw_down);
2374 sdma_sw_tear_down(sde);
2375 break;
2376 case sdma_event_e10_go_hw_start:
2377 break;
2378 case sdma_event_e15_hw_halt_done:
2379 break;
2380 case sdma_event_e25_hw_clean_up_done:
2381 break;
2382 case sdma_event_e30_go_running:
2383 sdma_set_state(sde, sdma_state_s99_running);
2384 ss->go_s99_running = 1;
2385 break;
2386 case sdma_event_e40_sw_cleaned:
2387 break;
2388 case sdma_event_e50_hw_cleaned:
2389 break;
2390 case sdma_event_e60_hw_halted:
2391 sdma_set_state(sde, sdma_state_s50_hw_halt_wait);
2392 sdma_start_err_halt_wait(sde);
2393 break;
2394 case sdma_event_e70_go_idle:
2395 break;
2396 case sdma_event_e85_link_down:
2397 /* fall through */
2398 case sdma_event_e80_hw_freeze:
2399 sdma_set_state(sde, sdma_state_s80_hw_freeze);
2400 atomic_dec(&sde->dd->sdma_unfreeze_count);
2401 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2402 break;
2403 case sdma_event_e81_hw_frozen:
2404 break;
2405 case sdma_event_e82_hw_unfreeze:
2406 break;
2407 case sdma_event_e90_sw_halted:
2408 break;
2409 }
2410 break;
2411
2412 case sdma_state_s30_sw_clean_up_wait:
2413 switch (event) {
2414 case sdma_event_e00_go_hw_down:
2415 sdma_set_state(sde, sdma_state_s00_hw_down);
2416 break;
2417 case sdma_event_e10_go_hw_start:
2418 break;
2419 case sdma_event_e15_hw_halt_done:
2420 break;
2421 case sdma_event_e25_hw_clean_up_done:
2422 break;
2423 case sdma_event_e30_go_running:
2424 ss->go_s99_running = 1;
2425 break;
2426 case sdma_event_e40_sw_cleaned:
2427 sdma_set_state(sde, sdma_state_s40_hw_clean_up_wait);
2428 sdma_start_hw_clean_up(sde);
2429 break;
2430 case sdma_event_e50_hw_cleaned:
2431 break;
2432 case sdma_event_e60_hw_halted:
2433 break;
2434 case sdma_event_e70_go_idle:
2435 ss->go_s99_running = 0;
2436 break;
2437 case sdma_event_e80_hw_freeze:
2438 break;
2439 case sdma_event_e81_hw_frozen:
2440 break;
2441 case sdma_event_e82_hw_unfreeze:
2442 break;
2443 case sdma_event_e85_link_down:
2444 ss->go_s99_running = 0;
2445 break;
2446 case sdma_event_e90_sw_halted:
2447 break;
2448 }
2449 break;
2450
2451 case sdma_state_s40_hw_clean_up_wait:
2452 switch (event) {
2453 case sdma_event_e00_go_hw_down:
2454 sdma_set_state(sde, sdma_state_s00_hw_down);
2455 sdma_start_sw_clean_up(sde);
2456 break;
2457 case sdma_event_e10_go_hw_start:
2458 break;
2459 case sdma_event_e15_hw_halt_done:
2460 break;
2461 case sdma_event_e25_hw_clean_up_done:
2462 sdma_hw_start_up(sde);
2463 sdma_set_state(sde, ss->go_s99_running ?
2464 sdma_state_s99_running :
2465 sdma_state_s20_idle);
2466 break;
2467 case sdma_event_e30_go_running:
2468 ss->go_s99_running = 1;
2469 break;
2470 case sdma_event_e40_sw_cleaned:
2471 break;
2472 case sdma_event_e50_hw_cleaned:
2473 break;
2474 case sdma_event_e60_hw_halted:
2475 break;
2476 case sdma_event_e70_go_idle:
2477 ss->go_s99_running = 0;
2478 break;
2479 case sdma_event_e80_hw_freeze:
2480 break;
2481 case sdma_event_e81_hw_frozen:
2482 break;
2483 case sdma_event_e82_hw_unfreeze:
2484 break;
2485 case sdma_event_e85_link_down:
2486 ss->go_s99_running = 0;
2487 break;
2488 case sdma_event_e90_sw_halted:
2489 break;
2490 }
2491 break;
2492
2493 case sdma_state_s50_hw_halt_wait:
2494 switch (event) {
2495 case sdma_event_e00_go_hw_down:
2496 sdma_set_state(sde, sdma_state_s00_hw_down);
2497 sdma_start_sw_clean_up(sde);
2498 break;
2499 case sdma_event_e10_go_hw_start:
2500 break;
2501 case sdma_event_e15_hw_halt_done:
2502 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait);
2503 sdma_start_sw_clean_up(sde);
2504 break;
2505 case sdma_event_e25_hw_clean_up_done:
2506 break;
2507 case sdma_event_e30_go_running:
2508 ss->go_s99_running = 1;
2509 break;
2510 case sdma_event_e40_sw_cleaned:
2511 break;
2512 case sdma_event_e50_hw_cleaned:
2513 break;
2514 case sdma_event_e60_hw_halted:
2515 sdma_start_err_halt_wait(sde);
2516 break;
2517 case sdma_event_e70_go_idle:
2518 ss->go_s99_running = 0;
2519 break;
2520 case sdma_event_e80_hw_freeze:
2521 break;
2522 case sdma_event_e81_hw_frozen:
2523 break;
2524 case sdma_event_e82_hw_unfreeze:
2525 break;
2526 case sdma_event_e85_link_down:
2527 ss->go_s99_running = 0;
2528 break;
2529 case sdma_event_e90_sw_halted:
2530 break;
2531 }
2532 break;
2533
2534 case sdma_state_s60_idle_halt_wait:
2535 switch (event) {
2536 case sdma_event_e00_go_hw_down:
2537 sdma_set_state(sde, sdma_state_s00_hw_down);
2538 sdma_start_sw_clean_up(sde);
2539 break;
2540 case sdma_event_e10_go_hw_start:
2541 break;
2542 case sdma_event_e15_hw_halt_done:
2543 sdma_set_state(sde, sdma_state_s30_sw_clean_up_wait);
2544 sdma_start_sw_clean_up(sde);
2545 break;
2546 case sdma_event_e25_hw_clean_up_done:
2547 break;
2548 case sdma_event_e30_go_running:
2549 ss->go_s99_running = 1;
2550 break;
2551 case sdma_event_e40_sw_cleaned:
2552 break;
2553 case sdma_event_e50_hw_cleaned:
2554 break;
2555 case sdma_event_e60_hw_halted:
2556 sdma_start_err_halt_wait(sde);
2557 break;
2558 case sdma_event_e70_go_idle:
2559 ss->go_s99_running = 0;
2560 break;
2561 case sdma_event_e80_hw_freeze:
2562 break;
2563 case sdma_event_e81_hw_frozen:
2564 break;
2565 case sdma_event_e82_hw_unfreeze:
2566 break;
2567 case sdma_event_e85_link_down:
2568 break;
2569 case sdma_event_e90_sw_halted:
2570 break;
2571 }
2572 break;
2573
2574 case sdma_state_s80_hw_freeze:
2575 switch (event) {
2576 case sdma_event_e00_go_hw_down:
2577 sdma_set_state(sde, sdma_state_s00_hw_down);
2578 sdma_start_sw_clean_up(sde);
2579 break;
2580 case sdma_event_e10_go_hw_start:
2581 break;
2582 case sdma_event_e15_hw_halt_done:
2583 break;
2584 case sdma_event_e25_hw_clean_up_done:
2585 break;
2586 case sdma_event_e30_go_running:
2587 ss->go_s99_running = 1;
2588 break;
2589 case sdma_event_e40_sw_cleaned:
2590 break;
2591 case sdma_event_e50_hw_cleaned:
2592 break;
2593 case sdma_event_e60_hw_halted:
2594 break;
2595 case sdma_event_e70_go_idle:
2596 ss->go_s99_running = 0;
2597 break;
2598 case sdma_event_e80_hw_freeze:
2599 break;
2600 case sdma_event_e81_hw_frozen:
2601 sdma_set_state(sde, sdma_state_s82_freeze_sw_clean);
2602 sdma_start_sw_clean_up(sde);
2603 break;
2604 case sdma_event_e82_hw_unfreeze:
2605 break;
2606 case sdma_event_e85_link_down:
2607 break;
2608 case sdma_event_e90_sw_halted:
2609 break;
2610 }
2611 break;
2612
2613 case sdma_state_s82_freeze_sw_clean:
2614 switch (event) {
2615 case sdma_event_e00_go_hw_down:
2616 sdma_set_state(sde, sdma_state_s00_hw_down);
2617 sdma_start_sw_clean_up(sde);
2618 break;
2619 case sdma_event_e10_go_hw_start:
2620 break;
2621 case sdma_event_e15_hw_halt_done:
2622 break;
2623 case sdma_event_e25_hw_clean_up_done:
2624 break;
2625 case sdma_event_e30_go_running:
2626 ss->go_s99_running = 1;
2627 break;
2628 case sdma_event_e40_sw_cleaned:
2629 /* notify caller this engine is done cleaning */
2630 atomic_dec(&sde->dd->sdma_unfreeze_count);
2631 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2632 break;
2633 case sdma_event_e50_hw_cleaned:
2634 break;
2635 case sdma_event_e60_hw_halted:
2636 break;
2637 case sdma_event_e70_go_idle:
2638 ss->go_s99_running = 0;
2639 break;
2640 case sdma_event_e80_hw_freeze:
2641 break;
2642 case sdma_event_e81_hw_frozen:
2643 break;
2644 case sdma_event_e82_hw_unfreeze:
2645 sdma_hw_start_up(sde);
2646 sdma_set_state(sde, ss->go_s99_running ?
2647 sdma_state_s99_running :
2648 sdma_state_s20_idle);
2649 break;
2650 case sdma_event_e85_link_down:
2651 break;
2652 case sdma_event_e90_sw_halted:
2653 break;
2654 }
2655 break;
2656
2657 case sdma_state_s99_running:
2658 switch (event) {
2659 case sdma_event_e00_go_hw_down:
2660 sdma_set_state(sde, sdma_state_s00_hw_down);
2661 sdma_start_sw_clean_up(sde);
2662 break;
2663 case sdma_event_e10_go_hw_start:
2664 break;
2665 case sdma_event_e15_hw_halt_done:
2666 break;
2667 case sdma_event_e25_hw_clean_up_done:
2668 break;
2669 case sdma_event_e30_go_running:
2670 break;
2671 case sdma_event_e40_sw_cleaned:
2672 break;
2673 case sdma_event_e50_hw_cleaned:
2674 break;
2675 case sdma_event_e60_hw_halted:
2676 need_progress = 1;
2677 sdma_err_progress_check_schedule(sde);
2678 case sdma_event_e90_sw_halted:
2679 /*
2680 * SW initiated halt does not perform engines
2681 * progress check
2682 */
2683 sdma_set_state(sde, sdma_state_s50_hw_halt_wait);
2684 sdma_start_err_halt_wait(sde);
2685 break;
2686 case sdma_event_e70_go_idle:
2687 sdma_set_state(sde, sdma_state_s60_idle_halt_wait);
2688 break;
2689 case sdma_event_e85_link_down:
2690 ss->go_s99_running = 0;
2691 /* fall through */
2692 case sdma_event_e80_hw_freeze:
2693 sdma_set_state(sde, sdma_state_s80_hw_freeze);
2694 atomic_dec(&sde->dd->sdma_unfreeze_count);
2695 wake_up_interruptible(&sde->dd->sdma_unfreeze_wq);
2696 break;
2697 case sdma_event_e81_hw_frozen:
2698 break;
2699 case sdma_event_e82_hw_unfreeze:
2700 break;
2701 }
2702 break;
2703 }
2704
2705 ss->last_event = event;
2706 if (need_progress)
2707 sdma_make_progress(sde, 0);
2708 }
2709
2710 /*
2711 * _extend_sdma_tx_descs() - helper to extend txreq
2712 *
2713 * This is called once the initial nominal allocation
2714 * of descriptors in the sdma_txreq is exhausted.
2715 *
2716 * The code will bump the allocation up to the max
2717 * of MAX_DESC (64) descriptors. There doesn't seem
2718 * much point in an interim step. The last descriptor
2719 * is reserved for coalesce buffer in order to support
2720 * cases where input packet has >MAX_DESC iovecs.
2721 *
2722 */
_extend_sdma_tx_descs(struct hfi1_devdata * dd,struct sdma_txreq * tx)2723 static int _extend_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx)
2724 {
2725 int i;
2726
2727 /* Handle last descriptor */
2728 if (unlikely((tx->num_desc == (MAX_DESC - 1)))) {
2729 /* if tlen is 0, it is for padding, release last descriptor */
2730 if (!tx->tlen) {
2731 tx->desc_limit = MAX_DESC;
2732 } else if (!tx->coalesce_buf) {
2733 /* allocate coalesce buffer with space for padding */
2734 tx->coalesce_buf = kmalloc(tx->tlen + sizeof(u32),
2735 GFP_ATOMIC);
2736 if (!tx->coalesce_buf)
2737 return -ENOMEM;
2738
2739 tx->coalesce_idx = 0;
2740 }
2741 return 0;
2742 }
2743
2744 if (unlikely(tx->num_desc == MAX_DESC))
2745 return -ENOMEM;
2746
2747 tx->descp = kmalloc_array(
2748 MAX_DESC,
2749 sizeof(struct sdma_desc),
2750 GFP_ATOMIC);
2751 if (!tx->descp)
2752 return -ENOMEM;
2753
2754 /* reserve last descriptor for coalescing */
2755 tx->desc_limit = MAX_DESC - 1;
2756 /* copy ones already built */
2757 for (i = 0; i < tx->num_desc; i++)
2758 tx->descp[i] = tx->descs[i];
2759 return 0;
2760 }
2761
2762 /*
2763 * ext_coal_sdma_tx_descs() - extend or coalesce sdma tx descriptors
2764 *
2765 * This is called once the initial nominal allocation of descriptors
2766 * in the sdma_txreq is exhausted.
2767 *
2768 * This function calls _extend_sdma_tx_descs to extend or allocate
2769 * coalesce buffer. If there is a allocated coalesce buffer, it will
2770 * copy the input packet data into the coalesce buffer. It also adds
2771 * coalesce buffer descriptor once whe whole packet is received.
2772 *
2773 * Return:
2774 * <0 - error
2775 * 0 - coalescing, don't populate descriptor
2776 * 1 - continue with populating descriptor
2777 */
ext_coal_sdma_tx_descs(struct hfi1_devdata * dd,struct sdma_txreq * tx,int type,void * kvaddr,struct page * page,unsigned long offset,u16 len)2778 int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx,
2779 int type, void *kvaddr, struct page *page,
2780 unsigned long offset, u16 len)
2781 {
2782 int pad_len, rval;
2783 dma_addr_t addr;
2784
2785 rval = _extend_sdma_tx_descs(dd, tx);
2786 if (rval) {
2787 sdma_txclean(dd, tx);
2788 return rval;
2789 }
2790
2791 /* If coalesce buffer is allocated, copy data into it */
2792 if (tx->coalesce_buf) {
2793 if (type == SDMA_MAP_NONE) {
2794 sdma_txclean(dd, tx);
2795 return -EINVAL;
2796 }
2797
2798 if (type == SDMA_MAP_PAGE) {
2799 kvaddr = kmap(page);
2800 kvaddr += offset;
2801 } else if (WARN_ON(!kvaddr)) {
2802 sdma_txclean(dd, tx);
2803 return -EINVAL;
2804 }
2805
2806 memcpy(tx->coalesce_buf + tx->coalesce_idx, kvaddr, len);
2807 tx->coalesce_idx += len;
2808 if (type == SDMA_MAP_PAGE)
2809 kunmap(page);
2810
2811 /* If there is more data, return */
2812 if (tx->tlen - tx->coalesce_idx)
2813 return 0;
2814
2815 /* Whole packet is received; add any padding */
2816 pad_len = tx->packet_len & (sizeof(u32) - 1);
2817 if (pad_len) {
2818 pad_len = sizeof(u32) - pad_len;
2819 memset(tx->coalesce_buf + tx->coalesce_idx, 0, pad_len);
2820 /* padding is taken care of for coalescing case */
2821 tx->packet_len += pad_len;
2822 tx->tlen += pad_len;
2823 }
2824
2825 /* dma map the coalesce buffer */
2826 addr = dma_map_single(&dd->pcidev->dev,
2827 tx->coalesce_buf,
2828 tx->tlen,
2829 DMA_TO_DEVICE);
2830
2831 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) {
2832 sdma_txclean(dd, tx);
2833 return -ENOSPC;
2834 }
2835
2836 /* Add descriptor for coalesce buffer */
2837 tx->desc_limit = MAX_DESC;
2838 return _sdma_txadd_daddr(dd, SDMA_MAP_SINGLE, tx,
2839 addr, tx->tlen);
2840 }
2841
2842 return 1;
2843 }
2844
2845 /* Update sdes when the lmc changes */
sdma_update_lmc(struct hfi1_devdata * dd,u64 mask,u32 lid)2846 void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid)
2847 {
2848 struct sdma_engine *sde;
2849 int i;
2850 u64 sreg;
2851
2852 sreg = ((mask & SD(CHECK_SLID_MASK_MASK)) <<
2853 SD(CHECK_SLID_MASK_SHIFT)) |
2854 (((lid & mask) & SD(CHECK_SLID_VALUE_MASK)) <<
2855 SD(CHECK_SLID_VALUE_SHIFT));
2856
2857 for (i = 0; i < dd->num_sdma; i++) {
2858 hfi1_cdbg(LINKVERB, "SendDmaEngine[%d].SLID_CHECK = 0x%x",
2859 i, (u32)sreg);
2860 sde = &dd->per_sdma[i];
2861 write_sde_csr(sde, SD(CHECK_SLID), sreg);
2862 }
2863 }
2864
2865 /* tx not dword sized - pad */
_pad_sdma_tx_descs(struct hfi1_devdata * dd,struct sdma_txreq * tx)2866 int _pad_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx)
2867 {
2868 int rval = 0;
2869
2870 tx->num_desc++;
2871 if ((unlikely(tx->num_desc == tx->desc_limit))) {
2872 rval = _extend_sdma_tx_descs(dd, tx);
2873 if (rval) {
2874 sdma_txclean(dd, tx);
2875 return rval;
2876 }
2877 }
2878 /* finish the one just added */
2879 make_tx_sdma_desc(
2880 tx,
2881 SDMA_MAP_NONE,
2882 dd->sdma_pad_phys,
2883 sizeof(u32) - (tx->packet_len & (sizeof(u32) - 1)));
2884 _sdma_close_tx(dd, tx);
2885 return rval;
2886 }
2887
2888 /*
2889 * Add ahg to the sdma_txreq
2890 *
2891 * The logic will consume up to 3
2892 * descriptors at the beginning of
2893 * sdma_txreq.
2894 */
_sdma_txreq_ahgadd(struct sdma_txreq * tx,u8 num_ahg,u8 ahg_entry,u32 * ahg,u8 ahg_hlen)2895 void _sdma_txreq_ahgadd(
2896 struct sdma_txreq *tx,
2897 u8 num_ahg,
2898 u8 ahg_entry,
2899 u32 *ahg,
2900 u8 ahg_hlen)
2901 {
2902 u32 i, shift = 0, desc = 0;
2903 u8 mode;
2904
2905 WARN_ON_ONCE(num_ahg > 9 || (ahg_hlen & 3) || ahg_hlen == 4);
2906 /* compute mode */
2907 if (num_ahg == 1)
2908 mode = SDMA_AHG_APPLY_UPDATE1;
2909 else if (num_ahg <= 5)
2910 mode = SDMA_AHG_APPLY_UPDATE2;
2911 else
2912 mode = SDMA_AHG_APPLY_UPDATE3;
2913 tx->num_desc++;
2914 /* initialize to consumed descriptors to zero */
2915 switch (mode) {
2916 case SDMA_AHG_APPLY_UPDATE3:
2917 tx->num_desc++;
2918 tx->descs[2].qw[0] = 0;
2919 tx->descs[2].qw[1] = 0;
2920 /* FALLTHROUGH */
2921 case SDMA_AHG_APPLY_UPDATE2:
2922 tx->num_desc++;
2923 tx->descs[1].qw[0] = 0;
2924 tx->descs[1].qw[1] = 0;
2925 break;
2926 }
2927 ahg_hlen >>= 2;
2928 tx->descs[0].qw[1] |=
2929 (((u64)ahg_entry & SDMA_DESC1_HEADER_INDEX_MASK)
2930 << SDMA_DESC1_HEADER_INDEX_SHIFT) |
2931 (((u64)ahg_hlen & SDMA_DESC1_HEADER_DWS_MASK)
2932 << SDMA_DESC1_HEADER_DWS_SHIFT) |
2933 (((u64)mode & SDMA_DESC1_HEADER_MODE_MASK)
2934 << SDMA_DESC1_HEADER_MODE_SHIFT) |
2935 (((u64)ahg[0] & SDMA_DESC1_HEADER_UPDATE1_MASK)
2936 << SDMA_DESC1_HEADER_UPDATE1_SHIFT);
2937 for (i = 0; i < (num_ahg - 1); i++) {
2938 if (!shift && !(i & 2))
2939 desc++;
2940 tx->descs[desc].qw[!!(i & 2)] |=
2941 (((u64)ahg[i + 1])
2942 << shift);
2943 shift = (shift + 32) & 63;
2944 }
2945 }
2946
2947 /**
2948 * sdma_ahg_alloc - allocate an AHG entry
2949 * @sde: engine to allocate from
2950 *
2951 * Return:
2952 * 0-31 when successful, -EOPNOTSUPP if AHG is not enabled,
2953 * -ENOSPC if an entry is not available
2954 */
sdma_ahg_alloc(struct sdma_engine * sde)2955 int sdma_ahg_alloc(struct sdma_engine *sde)
2956 {
2957 int nr;
2958 int oldbit;
2959
2960 if (!sde) {
2961 trace_hfi1_ahg_allocate(sde, -EINVAL);
2962 return -EINVAL;
2963 }
2964 while (1) {
2965 nr = ffz(ACCESS_ONCE(sde->ahg_bits));
2966 if (nr > 31) {
2967 trace_hfi1_ahg_allocate(sde, -ENOSPC);
2968 return -ENOSPC;
2969 }
2970 oldbit = test_and_set_bit(nr, &sde->ahg_bits);
2971 if (!oldbit)
2972 break;
2973 cpu_relax();
2974 }
2975 trace_hfi1_ahg_allocate(sde, nr);
2976 return nr;
2977 }
2978
2979 /**
2980 * sdma_ahg_free - free an AHG entry
2981 * @sde: engine to return AHG entry
2982 * @ahg_index: index to free
2983 *
2984 * This routine frees the indicate AHG entry.
2985 */
sdma_ahg_free(struct sdma_engine * sde,int ahg_index)2986 void sdma_ahg_free(struct sdma_engine *sde, int ahg_index)
2987 {
2988 if (!sde)
2989 return;
2990 trace_hfi1_ahg_deallocate(sde, ahg_index);
2991 if (ahg_index < 0 || ahg_index > 31)
2992 return;
2993 clear_bit(ahg_index, &sde->ahg_bits);
2994 }
2995
2996 /*
2997 * SPC freeze handling for SDMA engines. Called when the driver knows
2998 * the SPC is going into a freeze but before the freeze is fully
2999 * settled. Generally an error interrupt.
3000 *
3001 * This event will pull the engine out of running so no more entries can be
3002 * added to the engine's queue.
3003 */
sdma_freeze_notify(struct hfi1_devdata * dd,int link_down)3004 void sdma_freeze_notify(struct hfi1_devdata *dd, int link_down)
3005 {
3006 int i;
3007 enum sdma_events event = link_down ? sdma_event_e85_link_down :
3008 sdma_event_e80_hw_freeze;
3009
3010 /* set up the wait but do not wait here */
3011 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma);
3012
3013 /* tell all engines to stop running and wait */
3014 for (i = 0; i < dd->num_sdma; i++)
3015 sdma_process_event(&dd->per_sdma[i], event);
3016
3017 /* sdma_freeze() will wait for all engines to have stopped */
3018 }
3019
3020 /*
3021 * SPC freeze handling for SDMA engines. Called when the driver knows
3022 * the SPC is fully frozen.
3023 */
sdma_freeze(struct hfi1_devdata * dd)3024 void sdma_freeze(struct hfi1_devdata *dd)
3025 {
3026 int i;
3027 int ret;
3028
3029 /*
3030 * Make sure all engines have moved out of the running state before
3031 * continuing.
3032 */
3033 ret = wait_event_interruptible(dd->sdma_unfreeze_wq,
3034 atomic_read(&dd->sdma_unfreeze_count) <= 0);
3035 /* interrupted or count is negative, then unloading - just exit */
3036 if (ret || atomic_read(&dd->sdma_unfreeze_count) < 0)
3037 return;
3038
3039 /* set up the count for the next wait */
3040 atomic_set(&dd->sdma_unfreeze_count, dd->num_sdma);
3041
3042 /* tell all engines that the SPC is frozen, they can start cleaning */
3043 for (i = 0; i < dd->num_sdma; i++)
3044 sdma_process_event(&dd->per_sdma[i], sdma_event_e81_hw_frozen);
3045
3046 /*
3047 * Wait for everyone to finish software clean before exiting. The
3048 * software clean will read engine CSRs, so must be completed before
3049 * the next step, which will clear the engine CSRs.
3050 */
3051 (void) wait_event_interruptible(dd->sdma_unfreeze_wq,
3052 atomic_read(&dd->sdma_unfreeze_count) <= 0);
3053 /* no need to check results - done no matter what */
3054 }
3055
3056 /*
3057 * SPC freeze handling for the SDMA engines. Called after the SPC is unfrozen.
3058 *
3059 * The SPC freeze acts like a SDMA halt and a hardware clean combined. All
3060 * that is left is a software clean. We could do it after the SPC is fully
3061 * frozen, but then we'd have to add another state to wait for the unfreeze.
3062 * Instead, just defer the software clean until the unfreeze step.
3063 */
sdma_unfreeze(struct hfi1_devdata * dd)3064 void sdma_unfreeze(struct hfi1_devdata *dd)
3065 {
3066 int i;
3067
3068 /* tell all engines start freeze clean up */
3069 for (i = 0; i < dd->num_sdma; i++)
3070 sdma_process_event(&dd->per_sdma[i],
3071 sdma_event_e82_hw_unfreeze);
3072 }
3073
3074 /**
3075 * _sdma_engine_progress_schedule() - schedule progress on engine
3076 * @sde: sdma_engine to schedule progress
3077 *
3078 */
_sdma_engine_progress_schedule(struct sdma_engine * sde)3079 void _sdma_engine_progress_schedule(
3080 struct sdma_engine *sde)
3081 {
3082 trace_hfi1_sdma_engine_progress(sde, sde->progress_mask);
3083 /* assume we have selected a good cpu */
3084 write_csr(sde->dd,
3085 CCE_INT_FORCE + (8*(IS_SDMA_START/64)), sde->progress_mask);
3086 }
3087