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1 /*
2  * Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP
3  * platforms.
4  *
5  * Copyright (C) 2012 Marvell
6  *
7  * Yehuda Yitschak <yehuday@marvell.com>
8  * Gregory Clement <gregory.clement@free-electrons.com>
9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10  *
11  * This file is licensed under the terms of the GNU General Public
12  * License version 2.  This program is licensed "as is" without any
13  * warranty of any kind, whether express or implied.
14  *
15  * The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is
16  * responsible for ensuring hardware coherency between all CPUs and between
17  * CPUs and I/O masters. This file initializes the coherency fabric and
18  * supplies basic routines for configuring and controlling hardware coherency
19  */
20 
21 #define pr_fmt(fmt) "mvebu-coherency: " fmt
22 
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/of_address.h>
26 #include <linux/io.h>
27 #include <linux/smp.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
31 #include <linux/mbus.h>
32 #include <linux/pci.h>
33 #include <asm/smp_plat.h>
34 #include <asm/cacheflush.h>
35 #include <asm/mach/map.h>
36 #include <asm/dma-mapping.h>
37 #include "coherency.h"
38 #include "mvebu-soc-id.h"
39 
40 unsigned long coherency_phys_base;
41 void __iomem *coherency_base;
42 static void __iomem *coherency_cpu_base;
43 static void __iomem *cpu_config_base;
44 
45 /* Coherency fabric registers */
46 #define IO_SYNC_BARRIER_CTL_OFFSET		   0x0
47 
48 enum {
49 	COHERENCY_FABRIC_TYPE_NONE,
50 	COHERENCY_FABRIC_TYPE_ARMADA_370_XP,
51 	COHERENCY_FABRIC_TYPE_ARMADA_375,
52 	COHERENCY_FABRIC_TYPE_ARMADA_380,
53 };
54 
55 static const struct of_device_id of_coherency_table[] = {
56 	{.compatible = "marvell,coherency-fabric",
57 	 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
58 	{.compatible = "marvell,armada-375-coherency-fabric",
59 	 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 },
60 	{.compatible = "marvell,armada-380-coherency-fabric",
61 	 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 },
62 	{ /* end of list */ },
63 };
64 
65 /* Functions defined in coherency_ll.S */
66 int ll_enable_coherency(void);
67 void ll_add_cpu_to_smp_group(void);
68 
69 #define CPU_CONFIG_SHARED_L2 BIT(16)
70 
71 /*
72  * Disable the "Shared L2 Present" bit in CPU Configuration register
73  * on Armada XP.
74  *
75  * The "Shared L2 Present" bit affects the "level of coherence" value
76  * in the clidr CP15 register.  Cache operation functions such as
77  * "flush all" and "invalidate all" operate on all the cache levels
78  * that included in the defined level of coherence. When HW I/O
79  * coherency is used, this bit causes unnecessary flushes of the L2
80  * cache.
81  */
armada_xp_clear_shared_l2(void)82 static void armada_xp_clear_shared_l2(void)
83 {
84 	u32 reg;
85 
86 	if (!cpu_config_base)
87 		return;
88 
89 	reg = readl(cpu_config_base);
90 	reg &= ~CPU_CONFIG_SHARED_L2;
91 	writel(reg, cpu_config_base);
92 }
93 
mvebu_hwcc_notifier(struct notifier_block * nb,unsigned long event,void * __dev)94 static int mvebu_hwcc_notifier(struct notifier_block *nb,
95 			       unsigned long event, void *__dev)
96 {
97 	struct device *dev = __dev;
98 
99 	if (event != BUS_NOTIFY_ADD_DEVICE)
100 		return NOTIFY_DONE;
101 	set_dma_ops(dev, &arm_coherent_dma_ops);
102 
103 	return NOTIFY_OK;
104 }
105 
106 static struct notifier_block mvebu_hwcc_nb = {
107 	.notifier_call = mvebu_hwcc_notifier,
108 };
109 
110 static struct notifier_block mvebu_hwcc_pci_nb = {
111 	.notifier_call = mvebu_hwcc_notifier,
112 };
113 
armada_xp_clear_shared_l2_notifier_func(struct notifier_block * nfb,unsigned long action,void * hcpu)114 static int armada_xp_clear_shared_l2_notifier_func(struct notifier_block *nfb,
115 					unsigned long action, void *hcpu)
116 {
117 	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
118 		armada_xp_clear_shared_l2();
119 
120 	return NOTIFY_OK;
121 }
122 
123 static struct notifier_block armada_xp_clear_shared_l2_notifier = {
124 	.notifier_call = armada_xp_clear_shared_l2_notifier_func,
125 	.priority = 100,
126 };
127 
armada_370_coherency_init(struct device_node * np)128 static void __init armada_370_coherency_init(struct device_node *np)
129 {
130 	struct resource res;
131 	struct device_node *cpu_config_np;
132 
133 	of_address_to_resource(np, 0, &res);
134 	coherency_phys_base = res.start;
135 	/*
136 	 * Ensure secondary CPUs will see the updated value,
137 	 * which they read before they join the coherency
138 	 * fabric, and therefore before they are coherent with
139 	 * the boot CPU cache.
140 	 */
141 	sync_cache_w(&coherency_phys_base);
142 	coherency_base = of_iomap(np, 0);
143 	coherency_cpu_base = of_iomap(np, 1);
144 
145 	cpu_config_np = of_find_compatible_node(NULL, NULL,
146 						"marvell,armada-xp-cpu-config");
147 	if (!cpu_config_np)
148 		goto exit;
149 
150 	cpu_config_base = of_iomap(cpu_config_np, 0);
151 	if (!cpu_config_base) {
152 		of_node_put(cpu_config_np);
153 		goto exit;
154 	}
155 
156 	of_node_put(cpu_config_np);
157 
158 	register_cpu_notifier(&armada_xp_clear_shared_l2_notifier);
159 
160 exit:
161 	set_cpu_coherent();
162 }
163 
164 /*
165  * This ioremap hook is used on Armada 375/38x to ensure that all MMIO
166  * areas are mapped as MT_UNCACHED instead of MT_DEVICE. This is
167  * needed for the HW I/O coherency mechanism to work properly without
168  * deadlock.
169  */
170 static void __iomem *
armada_wa_ioremap_caller(phys_addr_t phys_addr,size_t size,unsigned int mtype,void * caller)171 armada_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
172 			 unsigned int mtype, void *caller)
173 {
174 	mtype = MT_UNCACHED;
175 	return __arm_ioremap_caller(phys_addr, size, mtype, caller);
176 }
177 
armada_375_380_coherency_init(struct device_node * np)178 static void __init armada_375_380_coherency_init(struct device_node *np)
179 {
180 	struct device_node *cache_dn;
181 
182 	coherency_cpu_base = of_iomap(np, 0);
183 	arch_ioremap_caller = armada_wa_ioremap_caller;
184 
185 	/*
186 	 * We should switch the PL310 to I/O coherency mode only if
187 	 * I/O coherency is actually enabled.
188 	 */
189 	if (!coherency_available())
190 		return;
191 
192 	/*
193 	 * Add the PL310 property "arm,io-coherent". This makes sure the
194 	 * outer sync operation is not used, which allows to
195 	 * workaround the system erratum that causes deadlocks when
196 	 * doing PCIe in an SMP situation on Armada 375 and Armada
197 	 * 38x.
198 	 */
199 	for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") {
200 		struct property *p;
201 
202 		p = kzalloc(sizeof(*p), GFP_KERNEL);
203 		p->name = kstrdup("arm,io-coherent", GFP_KERNEL);
204 		of_add_property(cache_dn, p);
205 	}
206 }
207 
coherency_type(void)208 static int coherency_type(void)
209 {
210 	struct device_node *np;
211 	const struct of_device_id *match;
212 	int type;
213 
214 	/*
215 	 * The coherency fabric is needed:
216 	 * - For coherency between processors on Armada XP, so only
217 	 *   when SMP is enabled.
218 	 * - For coherency between the processor and I/O devices, but
219 	 *   this coherency requires many pre-requisites (write
220 	 *   allocate cache policy, shareable pages, SMP bit set) that
221 	 *   are only meant in SMP situations.
222 	 *
223 	 * Note that this means that on Armada 370, there is currently
224 	 * no way to use hardware I/O coherency, because even when
225 	 * CONFIG_SMP is enabled, is_smp() returns false due to the
226 	 * Armada 370 being a single-core processor. To lift this
227 	 * limitation, we would have to find a way to make the cache
228 	 * policy set to write-allocate (on all Armada SoCs), and to
229 	 * set the shareable attribute in page tables (on all Armada
230 	 * SoCs except the Armada 370). Unfortunately, such decisions
231 	 * are taken very early in the kernel boot process, at a point
232 	 * where we don't know yet on which SoC we are running.
233 
234 	 */
235 	if (!is_smp())
236 		return COHERENCY_FABRIC_TYPE_NONE;
237 
238 	np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
239 	if (!np)
240 		return COHERENCY_FABRIC_TYPE_NONE;
241 
242 	type = (int) match->data;
243 
244 	of_node_put(np);
245 
246 	return type;
247 }
248 
set_cpu_coherent(void)249 int set_cpu_coherent(void)
250 {
251 	int type = coherency_type();
252 
253 	if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) {
254 		if (!coherency_base) {
255 			pr_warn("Can't make current CPU cache coherent.\n");
256 			pr_warn("Coherency fabric is not initialized\n");
257 			return 1;
258 		}
259 
260 		armada_xp_clear_shared_l2();
261 		ll_add_cpu_to_smp_group();
262 		return ll_enable_coherency();
263 	}
264 
265 	return 0;
266 }
267 
coherency_available(void)268 int coherency_available(void)
269 {
270 	return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
271 }
272 
coherency_init(void)273 int __init coherency_init(void)
274 {
275 	int type = coherency_type();
276 	struct device_node *np;
277 
278 	np = of_find_matching_node(NULL, of_coherency_table);
279 
280 	if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
281 		armada_370_coherency_init(np);
282 	else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 ||
283 		 type == COHERENCY_FABRIC_TYPE_ARMADA_380)
284 		armada_375_380_coherency_init(np);
285 
286 	of_node_put(np);
287 
288 	return 0;
289 }
290 
coherency_late_init(void)291 static int __init coherency_late_init(void)
292 {
293 	if (coherency_available())
294 		bus_register_notifier(&platform_bus_type,
295 				      &mvebu_hwcc_nb);
296 	return 0;
297 }
298 
299 postcore_initcall(coherency_late_init);
300 
301 #if IS_ENABLED(CONFIG_PCI)
coherency_pci_init(void)302 static int __init coherency_pci_init(void)
303 {
304 	if (coherency_available())
305 		bus_register_notifier(&pci_bus_type,
306 				       &mvebu_hwcc_pci_nb);
307 	return 0;
308 }
309 
310 arch_initcall(coherency_pci_init);
311 #endif
312