1 /*
2 * Time related functions for Hexagon architecture
3 *
4 * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 * 02110-1301, USA.
19 */
20
21 #include <linux/init.h>
22 #include <linux/clockchips.h>
23 #include <linux/clocksource.h>
24 #include <linux/interrupt.h>
25 #include <linux/err.h>
26 #include <linux/platform_device.h>
27 #include <linux/ioport.h>
28 #include <linux/of.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/module.h>
32
33 #include <asm/timer-regs.h>
34 #include <asm/hexagon_vm.h>
35
36 /*
37 * For the clocksource we need:
38 * pcycle frequency (600MHz)
39 * For the loops_per_jiffy we need:
40 * thread/cpu frequency (100MHz)
41 * And for the timer, we need:
42 * sleep clock rate
43 */
44
45 cycles_t pcycle_freq_mhz;
46 cycles_t thread_freq_mhz;
47 cycles_t sleep_clk_freq;
48
49 static struct resource rtos_timer_resources[] = {
50 {
51 .start = RTOS_TIMER_REGS_ADDR,
52 .end = RTOS_TIMER_REGS_ADDR+PAGE_SIZE-1,
53 .flags = IORESOURCE_MEM,
54 },
55 };
56
57 static struct platform_device rtos_timer_device = {
58 .name = "rtos_timer",
59 .id = -1,
60 .num_resources = ARRAY_SIZE(rtos_timer_resources),
61 .resource = rtos_timer_resources,
62 };
63
64 /* A lot of this stuff should move into a platform specific section. */
65 struct adsp_hw_timer_struct {
66 u32 match; /* Match value */
67 u32 count;
68 u32 enable; /* [1] - CLR_ON_MATCH_EN, [0] - EN */
69 u32 clear; /* one-shot register that clears the count */
70 };
71
72 /* Look for "TCX0" for related constants. */
73 static __iomem struct adsp_hw_timer_struct *rtos_timer;
74
timer_get_cycles(struct clocksource * cs)75 static cycle_t timer_get_cycles(struct clocksource *cs)
76 {
77 return (cycle_t) __vmgettime();
78 }
79
80 static struct clocksource hexagon_clocksource = {
81 .name = "pcycles",
82 .rating = 250,
83 .read = timer_get_cycles,
84 .mask = CLOCKSOURCE_MASK(64),
85 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
86 };
87
set_next_event(unsigned long delta,struct clock_event_device * evt)88 static int set_next_event(unsigned long delta, struct clock_event_device *evt)
89 {
90 /* Assuming the timer will be disabled when we enter here. */
91
92 iowrite32(1, &rtos_timer->clear);
93 iowrite32(0, &rtos_timer->clear);
94
95 iowrite32(delta, &rtos_timer->match);
96 iowrite32(1 << TIMER_ENABLE, &rtos_timer->enable);
97 return 0;
98 }
99
100 #ifdef CONFIG_SMP
101 /* Broadcast mechanism */
broadcast(const struct cpumask * mask)102 static void broadcast(const struct cpumask *mask)
103 {
104 send_ipi(mask, IPI_TIMER);
105 }
106 #endif
107
108 /* XXX Implement set_state_shutdown() */
109 static struct clock_event_device hexagon_clockevent_dev = {
110 .name = "clockevent",
111 .features = CLOCK_EVT_FEAT_ONESHOT,
112 .rating = 400,
113 .irq = RTOS_TIMER_INT,
114 .set_next_event = set_next_event,
115 #ifdef CONFIG_SMP
116 .broadcast = broadcast,
117 #endif
118 };
119
120 #ifdef CONFIG_SMP
121 static DEFINE_PER_CPU(struct clock_event_device, clock_events);
122
setup_percpu_clockdev(void)123 void setup_percpu_clockdev(void)
124 {
125 int cpu = smp_processor_id();
126 struct clock_event_device *ce_dev = &hexagon_clockevent_dev;
127 struct clock_event_device *dummy_clock_dev =
128 &per_cpu(clock_events, cpu);
129
130 memcpy(dummy_clock_dev, ce_dev, sizeof(*dummy_clock_dev));
131 INIT_LIST_HEAD(&dummy_clock_dev->list);
132
133 dummy_clock_dev->features = CLOCK_EVT_FEAT_DUMMY;
134 dummy_clock_dev->cpumask = cpumask_of(cpu);
135
136 clockevents_register_device(dummy_clock_dev);
137 }
138
139 /* Called from smp.c for each CPU's timer ipi call */
ipi_timer(void)140 void ipi_timer(void)
141 {
142 int cpu = smp_processor_id();
143 struct clock_event_device *ce_dev = &per_cpu(clock_events, cpu);
144
145 ce_dev->event_handler(ce_dev);
146 }
147 #endif /* CONFIG_SMP */
148
timer_interrupt(int irq,void * devid)149 static irqreturn_t timer_interrupt(int irq, void *devid)
150 {
151 struct clock_event_device *ce_dev = &hexagon_clockevent_dev;
152
153 iowrite32(0, &rtos_timer->enable);
154 ce_dev->event_handler(ce_dev);
155
156 return IRQ_HANDLED;
157 }
158
159 /* This should also be pulled from devtree */
160 static struct irqaction rtos_timer_intdesc = {
161 .handler = timer_interrupt,
162 .flags = IRQF_TIMER | IRQF_TRIGGER_RISING,
163 .name = "rtos_timer"
164 };
165
166 /*
167 * time_init_deferred - called by start_kernel to set up timer/clock source
168 *
169 * Install the IRQ handler for the clock, setup timers.
170 * This is done late, as that way, we can use ioremap().
171 *
172 * This runs just before the delay loop is calibrated, and
173 * is used for delay calibration.
174 */
time_init_deferred(void)175 void __init time_init_deferred(void)
176 {
177 struct resource *resource = NULL;
178 struct clock_event_device *ce_dev = &hexagon_clockevent_dev;
179
180 ce_dev->cpumask = cpu_all_mask;
181
182 if (!resource)
183 resource = rtos_timer_device.resource;
184
185 /* ioremap here means this has to run later, after paging init */
186 rtos_timer = ioremap(resource->start, resource_size(resource));
187
188 if (!rtos_timer) {
189 release_mem_region(resource->start, resource_size(resource));
190 }
191 clocksource_register_khz(&hexagon_clocksource, pcycle_freq_mhz * 1000);
192
193 /* Note: the sim generic RTOS clock is apparently really 18750Hz */
194
195 /*
196 * Last arg is some guaranteed seconds for which the conversion will
197 * work without overflow.
198 */
199 clockevents_calc_mult_shift(ce_dev, sleep_clk_freq, 4);
200
201 ce_dev->max_delta_ns = clockevent_delta2ns(0x7fffffff, ce_dev);
202 ce_dev->min_delta_ns = clockevent_delta2ns(0xf, ce_dev);
203
204 #ifdef CONFIG_SMP
205 setup_percpu_clockdev();
206 #endif
207
208 clockevents_register_device(ce_dev);
209 setup_irq(ce_dev->irq, &rtos_timer_intdesc);
210 }
211
time_init(void)212 void __init time_init(void)
213 {
214 late_time_init = time_init_deferred;
215 }
216
__delay(unsigned long cycles)217 void __delay(unsigned long cycles)
218 {
219 unsigned long long start = __vmgettime();
220
221 while ((__vmgettime() - start) < cycles)
222 cpu_relax();
223 }
224 EXPORT_SYMBOL(__delay);
225
226 /*
227 * This could become parametric or perhaps even computed at run-time,
228 * but for now we take the observed simulator jitter.
229 */
230 static long long fudgefactor = 350; /* Maybe lower if kernel optimized. */
231
__udelay(unsigned long usecs)232 void __udelay(unsigned long usecs)
233 {
234 unsigned long long start = __vmgettime();
235 unsigned long long finish = (pcycle_freq_mhz * usecs) - fudgefactor;
236
237 while ((__vmgettime() - start) < finish)
238 cpu_relax(); /* not sure how this improves readability */
239 }
240 EXPORT_SYMBOL(__udelay);
241