1 /*
2 * HD-audio controller helpers
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/export.h>
8 #include <sound/core.h>
9 #include <sound/hdaudio.h>
10 #include <sound/hda_register.h>
11
12 /* clear CORB read pointer properly */
azx_clear_corbrp(struct hdac_bus * bus)13 static void azx_clear_corbrp(struct hdac_bus *bus)
14 {
15 int timeout;
16
17 for (timeout = 1000; timeout > 0; timeout--) {
18 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
19 break;
20 udelay(1);
21 }
22 if (timeout <= 0)
23 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
24 snd_hdac_chip_readw(bus, CORBRP));
25
26 snd_hdac_chip_writew(bus, CORBRP, 0);
27 for (timeout = 1000; timeout > 0; timeout--) {
28 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
29 break;
30 udelay(1);
31 }
32 if (timeout <= 0)
33 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
34 snd_hdac_chip_readw(bus, CORBRP));
35 }
36
37 /**
38 * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
39 * @bus: HD-audio core bus
40 */
snd_hdac_bus_init_cmd_io(struct hdac_bus * bus)41 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
42 {
43 WARN_ON_ONCE(!bus->rb.area);
44
45 spin_lock_irq(&bus->reg_lock);
46 /* CORB set up */
47 bus->corb.addr = bus->rb.addr;
48 bus->corb.buf = (__le32 *)bus->rb.area;
49 snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
50 snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
51
52 /* set the corb size to 256 entries (ULI requires explicitly) */
53 snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
54 /* set the corb write pointer to 0 */
55 snd_hdac_chip_writew(bus, CORBWP, 0);
56
57 /* reset the corb hw read pointer */
58 snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
59 if (!bus->corbrp_self_clear)
60 azx_clear_corbrp(bus);
61
62 /* enable corb dma */
63 snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
64
65 /* RIRB set up */
66 bus->rirb.addr = bus->rb.addr + 2048;
67 bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
68 bus->rirb.wp = bus->rirb.rp = 0;
69 memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
70 snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
71 snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
72
73 /* set the rirb size to 256 entries (ULI requires explicitly) */
74 snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
75 /* reset the rirb hw write pointer */
76 snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
77 /* set N=1, get RIRB response interrupt for new entry */
78 snd_hdac_chip_writew(bus, RINTCNT, 1);
79 /* enable rirb dma and response irq */
80 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
81 spin_unlock_irq(&bus->reg_lock);
82 }
83 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io);
84
85 /**
86 * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers
87 * @bus: HD-audio core bus
88 */
snd_hdac_bus_stop_cmd_io(struct hdac_bus * bus)89 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
90 {
91 spin_lock_irq(&bus->reg_lock);
92 /* disable ringbuffer DMAs */
93 snd_hdac_chip_writeb(bus, RIRBCTL, 0);
94 snd_hdac_chip_writeb(bus, CORBCTL, 0);
95 /* disable unsolicited responses */
96 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
97 spin_unlock_irq(&bus->reg_lock);
98 }
99 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io);
100
azx_command_addr(u32 cmd)101 static unsigned int azx_command_addr(u32 cmd)
102 {
103 unsigned int addr = cmd >> 28;
104
105 if (snd_BUG_ON(addr >= HDA_MAX_CODECS))
106 addr = 0;
107 return addr;
108 }
109
110 /**
111 * snd_hdac_bus_send_cmd - send a command verb via CORB
112 * @bus: HD-audio core bus
113 * @val: encoded verb value to send
114 *
115 * Returns zero for success or a negative error code.
116 */
snd_hdac_bus_send_cmd(struct hdac_bus * bus,unsigned int val)117 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
118 {
119 unsigned int addr = azx_command_addr(val);
120 unsigned int wp, rp;
121
122 spin_lock_irq(&bus->reg_lock);
123
124 bus->last_cmd[azx_command_addr(val)] = val;
125
126 /* add command to corb */
127 wp = snd_hdac_chip_readw(bus, CORBWP);
128 if (wp == 0xffff) {
129 /* something wrong, controller likely turned to D3 */
130 spin_unlock_irq(&bus->reg_lock);
131 return -EIO;
132 }
133 wp++;
134 wp %= AZX_MAX_CORB_ENTRIES;
135
136 rp = snd_hdac_chip_readw(bus, CORBRP);
137 if (wp == rp) {
138 /* oops, it's full */
139 spin_unlock_irq(&bus->reg_lock);
140 return -EAGAIN;
141 }
142
143 bus->rirb.cmds[addr]++;
144 bus->corb.buf[wp] = cpu_to_le32(val);
145 snd_hdac_chip_writew(bus, CORBWP, wp);
146
147 spin_unlock_irq(&bus->reg_lock);
148
149 return 0;
150 }
151 EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd);
152
153 #define AZX_RIRB_EX_UNSOL_EV (1<<4)
154
155 /**
156 * snd_hdac_bus_update_rirb - retrieve RIRB entries
157 * @bus: HD-audio core bus
158 *
159 * Usually called from interrupt handler.
160 */
snd_hdac_bus_update_rirb(struct hdac_bus * bus)161 void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
162 {
163 unsigned int rp, wp;
164 unsigned int addr;
165 u32 res, res_ex;
166
167 wp = snd_hdac_chip_readw(bus, RIRBWP);
168 if (wp == 0xffff) {
169 /* something wrong, controller likely turned to D3 */
170 return;
171 }
172
173 if (wp == bus->rirb.wp)
174 return;
175 bus->rirb.wp = wp;
176
177 while (bus->rirb.rp != wp) {
178 bus->rirb.rp++;
179 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
180
181 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
182 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
183 res = le32_to_cpu(bus->rirb.buf[rp]);
184 addr = res_ex & 0xf;
185 if (addr >= HDA_MAX_CODECS) {
186 dev_err(bus->dev,
187 "spurious response %#x:%#x, rp = %d, wp = %d",
188 res, res_ex, bus->rirb.rp, wp);
189 snd_BUG();
190 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
191 snd_hdac_bus_queue_event(bus, res, res_ex);
192 else if (bus->rirb.cmds[addr]) {
193 bus->rirb.res[addr] = res;
194 bus->rirb.cmds[addr]--;
195 } else {
196 dev_err_ratelimited(bus->dev,
197 "spurious response %#x:%#x, last cmd=%#08x\n",
198 res, res_ex, bus->last_cmd[addr]);
199 }
200 }
201 }
202 EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb);
203
204 /**
205 * snd_hdac_bus_get_response - receive a response via RIRB
206 * @bus: HD-audio core bus
207 * @addr: codec address
208 * @res: pointer to store the value, NULL when not needed
209 *
210 * Returns zero if a value is read, or a negative error code.
211 */
snd_hdac_bus_get_response(struct hdac_bus * bus,unsigned int addr,unsigned int * res)212 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
213 unsigned int *res)
214 {
215 unsigned long timeout;
216 unsigned long loopcounter;
217
218 timeout = jiffies + msecs_to_jiffies(1000);
219
220 for (loopcounter = 0;; loopcounter++) {
221 spin_lock_irq(&bus->reg_lock);
222 if (!bus->rirb.cmds[addr]) {
223 if (res)
224 *res = bus->rirb.res[addr]; /* the last value */
225 spin_unlock_irq(&bus->reg_lock);
226 return 0;
227 }
228 spin_unlock_irq(&bus->reg_lock);
229 if (time_after(jiffies, timeout))
230 break;
231 if (loopcounter > 3000)
232 msleep(2); /* temporary workaround */
233 else {
234 udelay(10);
235 cond_resched();
236 }
237 }
238
239 return -EIO;
240 }
241 EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response);
242
243 /*
244 * Lowlevel interface
245 */
246
247 /**
248 * snd_hdac_bus_enter_link_reset - enter link reset
249 * @bus: HD-audio core bus
250 *
251 * Enter to the link reset state.
252 */
snd_hdac_bus_enter_link_reset(struct hdac_bus * bus)253 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
254 {
255 unsigned long timeout;
256
257 /* reset controller */
258 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
259
260 timeout = jiffies + msecs_to_jiffies(100);
261 while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
262 time_before(jiffies, timeout))
263 usleep_range(500, 1000);
264 }
265 EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset);
266
267 /**
268 * snd_hdac_bus_exit_link_reset - exit link reset
269 * @bus: HD-audio core bus
270 *
271 * Exit from the link reset state.
272 */
snd_hdac_bus_exit_link_reset(struct hdac_bus * bus)273 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
274 {
275 unsigned long timeout;
276
277 snd_hdac_chip_updateb(bus, GCTL, 0, AZX_GCTL_RESET);
278
279 timeout = jiffies + msecs_to_jiffies(100);
280 while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
281 usleep_range(500, 1000);
282 }
283 EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset);
284
285 /* reset codec link */
azx_reset(struct hdac_bus * bus,bool full_reset)286 static int azx_reset(struct hdac_bus *bus, bool full_reset)
287 {
288 if (!full_reset)
289 goto skip_reset;
290
291 /* clear STATESTS if not in reset */
292 if (snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)
293 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
294
295 /* reset controller */
296 snd_hdac_bus_enter_link_reset(bus);
297
298 /* delay for >= 100us for codec PLL to settle per spec
299 * Rev 0.9 section 5.5.1
300 */
301 usleep_range(500, 1000);
302
303 /* Bring controller out of reset */
304 snd_hdac_bus_exit_link_reset(bus);
305
306 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
307 usleep_range(1000, 1200);
308
309 skip_reset:
310 /* check to see if controller is ready */
311 if (!snd_hdac_chip_readb(bus, GCTL)) {
312 dev_dbg(bus->dev, "azx_reset: controller not ready!\n");
313 return -EBUSY;
314 }
315
316 /* Accept unsolicited responses */
317 snd_hdac_chip_updatel(bus, GCTL, 0, AZX_GCTL_UNSOL);
318
319 /* detect codecs */
320 if (!bus->codec_mask) {
321 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
322 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
323 }
324
325 return 0;
326 }
327
328 /* enable interrupts */
azx_int_enable(struct hdac_bus * bus)329 static void azx_int_enable(struct hdac_bus *bus)
330 {
331 /* enable controller CIE and GIE */
332 snd_hdac_chip_updatel(bus, INTCTL, 0, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
333 }
334
335 /* disable interrupts */
azx_int_disable(struct hdac_bus * bus)336 static void azx_int_disable(struct hdac_bus *bus)
337 {
338 struct hdac_stream *azx_dev;
339
340 /* disable interrupts in stream descriptor */
341 list_for_each_entry(azx_dev, &bus->stream_list, list)
342 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0);
343
344 /* disable SIE for all streams */
345 snd_hdac_chip_writeb(bus, INTCTL, 0);
346
347 /* disable controller CIE and GIE */
348 snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0);
349 }
350
351 /* clear interrupts */
azx_int_clear(struct hdac_bus * bus)352 static void azx_int_clear(struct hdac_bus *bus)
353 {
354 struct hdac_stream *azx_dev;
355
356 /* clear stream status */
357 list_for_each_entry(azx_dev, &bus->stream_list, list)
358 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
359
360 /* clear STATESTS */
361 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
362
363 /* clear rirb status */
364 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
365
366 /* clear int status */
367 snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
368 }
369
370 /**
371 * snd_hdac_bus_init_chip - reset and start the controller registers
372 * @bus: HD-audio core bus
373 * @full_reset: Do full reset
374 */
snd_hdac_bus_init_chip(struct hdac_bus * bus,bool full_reset)375 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
376 {
377 if (bus->chip_init)
378 return false;
379
380 /* reset controller */
381 azx_reset(bus, full_reset);
382
383 /* clear interrupts */
384 azx_int_clear(bus);
385
386 /* initialize the codec command I/O */
387 snd_hdac_bus_init_cmd_io(bus);
388
389 /* enable interrupts after CORB/RIRB buffers are initialized above */
390 azx_int_enable(bus);
391
392 /* program the position buffer */
393 if (bus->use_posbuf && bus->posbuf.addr) {
394 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
395 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
396 }
397
398 bus->chip_init = true;
399 return true;
400 }
401 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip);
402
403 /**
404 * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os
405 * @bus: HD-audio core bus
406 */
snd_hdac_bus_stop_chip(struct hdac_bus * bus)407 void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
408 {
409 if (!bus->chip_init)
410 return;
411
412 /* disable interrupts */
413 azx_int_disable(bus);
414 azx_int_clear(bus);
415
416 /* disable CORB/RIRB */
417 snd_hdac_bus_stop_cmd_io(bus);
418
419 /* disable position buffer */
420 if (bus->posbuf.addr) {
421 snd_hdac_chip_writel(bus, DPLBASE, 0);
422 snd_hdac_chip_writel(bus, DPUBASE, 0);
423 }
424
425 bus->chip_init = false;
426 }
427 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip);
428
429 /**
430 * snd_hdac_bus_handle_stream_irq - interrupt handler for streams
431 * @bus: HD-audio core bus
432 * @status: INTSTS register value
433 * @ask: callback to be called for woken streams
434 */
snd_hdac_bus_handle_stream_irq(struct hdac_bus * bus,unsigned int status,void (* ack)(struct hdac_bus *,struct hdac_stream *))435 void snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
436 void (*ack)(struct hdac_bus *,
437 struct hdac_stream *))
438 {
439 struct hdac_stream *azx_dev;
440 u8 sd_status;
441
442 list_for_each_entry(azx_dev, &bus->stream_list, list) {
443 if (status & azx_dev->sd_int_sta_mask) {
444 sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
445 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
446 if (!azx_dev->substream || !azx_dev->running ||
447 !(sd_status & SD_INT_COMPLETE))
448 continue;
449 if (ack)
450 ack(bus, azx_dev);
451 }
452 }
453 }
454 EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq);
455
456 /**
457 * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers
458 * @bus: HD-audio core bus
459 *
460 * Call this after assigning the all streams.
461 * Returns zero for success, or a negative error code.
462 */
snd_hdac_bus_alloc_stream_pages(struct hdac_bus * bus)463 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
464 {
465 struct hdac_stream *s;
466 int num_streams = 0;
467 int err;
468
469 list_for_each_entry(s, &bus->stream_list, list) {
470 /* allocate memory for the BDL for each stream */
471 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
472 BDL_SIZE, &s->bdl);
473 num_streams++;
474 if (err < 0)
475 return -ENOMEM;
476 }
477
478 if (WARN_ON(!num_streams))
479 return -EINVAL;
480 /* allocate memory for the position buffer */
481 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
482 num_streams * 8, &bus->posbuf);
483 if (err < 0)
484 return -ENOMEM;
485 list_for_each_entry(s, &bus->stream_list, list)
486 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
487
488 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
489 return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
490 PAGE_SIZE, &bus->rb);
491 }
492 EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages);
493
494 /**
495 * snd_hdac_bus_free_stream_pages - release BDL and other buffers
496 * @bus: HD-audio core bus
497 */
snd_hdac_bus_free_stream_pages(struct hdac_bus * bus)498 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
499 {
500 struct hdac_stream *s;
501
502 list_for_each_entry(s, &bus->stream_list, list) {
503 if (s->bdl.area)
504 bus->io_ops->dma_free_pages(bus, &s->bdl);
505 }
506
507 if (bus->rb.area)
508 bus->io_ops->dma_free_pages(bus, &bus->rb);
509 if (bus->posbuf.area)
510 bus->io_ops->dma_free_pages(bus, &bus->posbuf);
511 }
512 EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages);
513