1 /*
2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
4 * Copyright (C) 2011 Don Zickus Red Hat, Inc.
5 *
6 * Pentium III FXSR, SSE support
7 * Gareth Hughes <gareth@valinux.com>, May 2000
8 */
9
10 /*
11 * Handle hardware traps and faults.
12 */
13 #include <linux/spinlock.h>
14 #include <linux/kprobes.h>
15 #include <linux/kdebug.h>
16 #include <linux/nmi.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/hardirq.h>
20 #include <linux/slab.h>
21 #include <linux/export.h>
22
23 #if defined(CONFIG_EDAC)
24 #include <linux/edac.h>
25 #endif
26
27 #include <linux/atomic.h>
28 #include <asm/traps.h>
29 #include <asm/mach_traps.h>
30 #include <asm/nmi.h>
31 #include <asm/x86_init.h>
32 #include <asm/nospec-branch.h>
33
34 #define CREATE_TRACE_POINTS
35 #include <trace/events/nmi.h>
36
37 struct nmi_desc {
38 spinlock_t lock;
39 struct list_head head;
40 };
41
42 static struct nmi_desc nmi_desc[NMI_MAX] =
43 {
44 {
45 .lock = __SPIN_LOCK_UNLOCKED(&nmi_desc[0].lock),
46 .head = LIST_HEAD_INIT(nmi_desc[0].head),
47 },
48 {
49 .lock = __SPIN_LOCK_UNLOCKED(&nmi_desc[1].lock),
50 .head = LIST_HEAD_INIT(nmi_desc[1].head),
51 },
52 {
53 .lock = __SPIN_LOCK_UNLOCKED(&nmi_desc[2].lock),
54 .head = LIST_HEAD_INIT(nmi_desc[2].head),
55 },
56 {
57 .lock = __SPIN_LOCK_UNLOCKED(&nmi_desc[3].lock),
58 .head = LIST_HEAD_INIT(nmi_desc[3].head),
59 },
60
61 };
62
63 struct nmi_stats {
64 unsigned int normal;
65 unsigned int unknown;
66 unsigned int external;
67 unsigned int swallow;
68 };
69
70 static DEFINE_PER_CPU(struct nmi_stats, nmi_stats);
71
72 static int ignore_nmis;
73
74 int unknown_nmi_panic;
75 /*
76 * Prevent NMI reason port (0x61) being accessed simultaneously, can
77 * only be used in NMI handler.
78 */
79 static DEFINE_RAW_SPINLOCK(nmi_reason_lock);
80
setup_unknown_nmi_panic(char * str)81 static int __init setup_unknown_nmi_panic(char *str)
82 {
83 unknown_nmi_panic = 1;
84 return 1;
85 }
86 __setup("unknown_nmi_panic", setup_unknown_nmi_panic);
87
88 #define nmi_to_desc(type) (&nmi_desc[type])
89
90 static u64 nmi_longest_ns = 1 * NSEC_PER_MSEC;
91
nmi_warning_debugfs(void)92 static int __init nmi_warning_debugfs(void)
93 {
94 debugfs_create_u64("nmi_longest_ns", 0644,
95 arch_debugfs_dir, &nmi_longest_ns);
96 return 0;
97 }
98 fs_initcall(nmi_warning_debugfs);
99
nmi_max_handler(struct irq_work * w)100 static void nmi_max_handler(struct irq_work *w)
101 {
102 struct nmiaction *a = container_of(w, struct nmiaction, irq_work);
103 int remainder_ns, decimal_msecs;
104 u64 whole_msecs = ACCESS_ONCE(a->max_duration);
105
106 remainder_ns = do_div(whole_msecs, (1000 * 1000));
107 decimal_msecs = remainder_ns / 1000;
108
109 printk_ratelimited(KERN_INFO
110 "INFO: NMI handler (%ps) took too long to run: %lld.%03d msecs\n",
111 a->handler, whole_msecs, decimal_msecs);
112 }
113
nmi_handle(unsigned int type,struct pt_regs * regs)114 static int nmi_handle(unsigned int type, struct pt_regs *regs)
115 {
116 struct nmi_desc *desc = nmi_to_desc(type);
117 struct nmiaction *a;
118 int handled=0;
119
120 rcu_read_lock();
121
122 /*
123 * NMIs are edge-triggered, which means if you have enough
124 * of them concurrently, you can lose some because only one
125 * can be latched at any given time. Walk the whole list
126 * to handle those situations.
127 */
128 list_for_each_entry_rcu(a, &desc->head, list) {
129 int thishandled;
130 u64 delta;
131
132 delta = sched_clock();
133 thishandled = a->handler(type, regs);
134 handled += thishandled;
135 delta = sched_clock() - delta;
136 trace_nmi_handler(a->handler, (int)delta, thishandled);
137
138 if (delta < nmi_longest_ns || delta < a->max_duration)
139 continue;
140
141 a->max_duration = delta;
142 irq_work_queue(&a->irq_work);
143 }
144
145 rcu_read_unlock();
146
147 /* return total number of NMI events handled */
148 return handled;
149 }
150 NOKPROBE_SYMBOL(nmi_handle);
151
__register_nmi_handler(unsigned int type,struct nmiaction * action)152 int __register_nmi_handler(unsigned int type, struct nmiaction *action)
153 {
154 struct nmi_desc *desc = nmi_to_desc(type);
155 unsigned long flags;
156
157 if (!action->handler)
158 return -EINVAL;
159
160 init_irq_work(&action->irq_work, nmi_max_handler);
161
162 spin_lock_irqsave(&desc->lock, flags);
163
164 /*
165 * most handlers of type NMI_UNKNOWN never return because
166 * they just assume the NMI is theirs. Just a sanity check
167 * to manage expectations
168 */
169 WARN_ON_ONCE(type == NMI_UNKNOWN && !list_empty(&desc->head));
170 WARN_ON_ONCE(type == NMI_SERR && !list_empty(&desc->head));
171 WARN_ON_ONCE(type == NMI_IO_CHECK && !list_empty(&desc->head));
172
173 /*
174 * some handlers need to be executed first otherwise a fake
175 * event confuses some handlers (kdump uses this flag)
176 */
177 if (action->flags & NMI_FLAG_FIRST)
178 list_add_rcu(&action->list, &desc->head);
179 else
180 list_add_tail_rcu(&action->list, &desc->head);
181
182 spin_unlock_irqrestore(&desc->lock, flags);
183 return 0;
184 }
185 EXPORT_SYMBOL(__register_nmi_handler);
186
unregister_nmi_handler(unsigned int type,const char * name)187 void unregister_nmi_handler(unsigned int type, const char *name)
188 {
189 struct nmi_desc *desc = nmi_to_desc(type);
190 struct nmiaction *n;
191 unsigned long flags;
192
193 spin_lock_irqsave(&desc->lock, flags);
194
195 list_for_each_entry_rcu(n, &desc->head, list) {
196 /*
197 * the name passed in to describe the nmi handler
198 * is used as the lookup key
199 */
200 if (!strcmp(n->name, name)) {
201 WARN(in_nmi(),
202 "Trying to free NMI (%s) from NMI context!\n", n->name);
203 list_del_rcu(&n->list);
204 break;
205 }
206 }
207
208 spin_unlock_irqrestore(&desc->lock, flags);
209 synchronize_rcu();
210 }
211 EXPORT_SYMBOL_GPL(unregister_nmi_handler);
212
213 static void
pci_serr_error(unsigned char reason,struct pt_regs * regs)214 pci_serr_error(unsigned char reason, struct pt_regs *regs)
215 {
216 /* check to see if anyone registered against these types of errors */
217 if (nmi_handle(NMI_SERR, regs))
218 return;
219
220 pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n",
221 reason, smp_processor_id());
222
223 /*
224 * On some machines, PCI SERR line is used to report memory
225 * errors. EDAC makes use of it.
226 */
227 #if defined(CONFIG_EDAC)
228 if (edac_handler_set()) {
229 edac_atomic_assert_error();
230 return;
231 }
232 #endif
233
234 if (panic_on_unrecovered_nmi)
235 panic("NMI: Not continuing");
236
237 pr_emerg("Dazed and confused, but trying to continue\n");
238
239 /* Clear and disable the PCI SERR error line. */
240 reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_SERR;
241 outb(reason, NMI_REASON_PORT);
242 }
243 NOKPROBE_SYMBOL(pci_serr_error);
244
245 static void
io_check_error(unsigned char reason,struct pt_regs * regs)246 io_check_error(unsigned char reason, struct pt_regs *regs)
247 {
248 unsigned long i;
249
250 /* check to see if anyone registered against these types of errors */
251 if (nmi_handle(NMI_IO_CHECK, regs))
252 return;
253
254 pr_emerg(
255 "NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n",
256 reason, smp_processor_id());
257 show_regs(regs);
258
259 if (panic_on_io_nmi)
260 panic("NMI IOCK error: Not continuing");
261
262 /* Re-enable the IOCK line, wait for a few seconds */
263 reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_IOCHK;
264 outb(reason, NMI_REASON_PORT);
265
266 i = 20000;
267 while (--i) {
268 touch_nmi_watchdog();
269 udelay(100);
270 }
271
272 reason &= ~NMI_REASON_CLEAR_IOCHK;
273 outb(reason, NMI_REASON_PORT);
274 }
275 NOKPROBE_SYMBOL(io_check_error);
276
277 static void
unknown_nmi_error(unsigned char reason,struct pt_regs * regs)278 unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
279 {
280 int handled;
281
282 /*
283 * Use 'false' as back-to-back NMIs are dealt with one level up.
284 * Of course this makes having multiple 'unknown' handlers useless
285 * as only the first one is ever run (unless it can actually determine
286 * if it caused the NMI)
287 */
288 handled = nmi_handle(NMI_UNKNOWN, regs);
289 if (handled) {
290 __this_cpu_add(nmi_stats.unknown, handled);
291 return;
292 }
293
294 __this_cpu_add(nmi_stats.unknown, 1);
295
296 pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
297 reason, smp_processor_id());
298
299 pr_emerg("Do you have a strange power saving mode enabled?\n");
300 if (unknown_nmi_panic || panic_on_unrecovered_nmi)
301 panic("NMI: Not continuing");
302
303 pr_emerg("Dazed and confused, but trying to continue\n");
304 }
305 NOKPROBE_SYMBOL(unknown_nmi_error);
306
307 static DEFINE_PER_CPU(bool, swallow_nmi);
308 static DEFINE_PER_CPU(unsigned long, last_nmi_rip);
309
default_do_nmi(struct pt_regs * regs)310 static void default_do_nmi(struct pt_regs *regs)
311 {
312 unsigned char reason = 0;
313 int handled;
314 bool b2b = false;
315
316 /*
317 * CPU-specific NMI must be processed before non-CPU-specific
318 * NMI, otherwise we may lose it, because the CPU-specific
319 * NMI can not be detected/processed on other CPUs.
320 */
321
322 /*
323 * Back-to-back NMIs are interesting because they can either
324 * be two NMI or more than two NMIs (any thing over two is dropped
325 * due to NMI being edge-triggered). If this is the second half
326 * of the back-to-back NMI, assume we dropped things and process
327 * more handlers. Otherwise reset the 'swallow' NMI behaviour
328 */
329 if (regs->ip == __this_cpu_read(last_nmi_rip))
330 b2b = true;
331 else
332 __this_cpu_write(swallow_nmi, false);
333
334 __this_cpu_write(last_nmi_rip, regs->ip);
335
336 handled = nmi_handle(NMI_LOCAL, regs);
337 __this_cpu_add(nmi_stats.normal, handled);
338 if (handled) {
339 /*
340 * There are cases when a NMI handler handles multiple
341 * events in the current NMI. One of these events may
342 * be queued for in the next NMI. Because the event is
343 * already handled, the next NMI will result in an unknown
344 * NMI. Instead lets flag this for a potential NMI to
345 * swallow.
346 */
347 if (handled > 1)
348 __this_cpu_write(swallow_nmi, true);
349 return;
350 }
351
352 /* Non-CPU-specific NMI: NMI sources can be processed on any CPU */
353 raw_spin_lock(&nmi_reason_lock);
354 reason = x86_platform.get_nmi_reason();
355
356 if (reason & NMI_REASON_MASK) {
357 if (reason & NMI_REASON_SERR)
358 pci_serr_error(reason, regs);
359 else if (reason & NMI_REASON_IOCHK)
360 io_check_error(reason, regs);
361 #ifdef CONFIG_X86_32
362 /*
363 * Reassert NMI in case it became active
364 * meanwhile as it's edge-triggered:
365 */
366 reassert_nmi();
367 #endif
368 __this_cpu_add(nmi_stats.external, 1);
369 raw_spin_unlock(&nmi_reason_lock);
370 return;
371 }
372 raw_spin_unlock(&nmi_reason_lock);
373
374 /*
375 * Only one NMI can be latched at a time. To handle
376 * this we may process multiple nmi handlers at once to
377 * cover the case where an NMI is dropped. The downside
378 * to this approach is we may process an NMI prematurely,
379 * while its real NMI is sitting latched. This will cause
380 * an unknown NMI on the next run of the NMI processing.
381 *
382 * We tried to flag that condition above, by setting the
383 * swallow_nmi flag when we process more than one event.
384 * This condition is also only present on the second half
385 * of a back-to-back NMI, so we flag that condition too.
386 *
387 * If both are true, we assume we already processed this
388 * NMI previously and we swallow it. Otherwise we reset
389 * the logic.
390 *
391 * There are scenarios where we may accidentally swallow
392 * a 'real' unknown NMI. For example, while processing
393 * a perf NMI another perf NMI comes in along with a
394 * 'real' unknown NMI. These two NMIs get combined into
395 * one (as descibed above). When the next NMI gets
396 * processed, it will be flagged by perf as handled, but
397 * noone will know that there was a 'real' unknown NMI sent
398 * also. As a result it gets swallowed. Or if the first
399 * perf NMI returns two events handled then the second
400 * NMI will get eaten by the logic below, again losing a
401 * 'real' unknown NMI. But this is the best we can do
402 * for now.
403 */
404 if (b2b && __this_cpu_read(swallow_nmi))
405 __this_cpu_add(nmi_stats.swallow, 1);
406 else
407 unknown_nmi_error(reason, regs);
408 }
409 NOKPROBE_SYMBOL(default_do_nmi);
410
411 /*
412 * NMIs can page fault or hit breakpoints which will cause it to lose
413 * its NMI context with the CPU when the breakpoint or page fault does an IRET.
414 *
415 * As a result, NMIs can nest if NMIs get unmasked due an IRET during
416 * NMI processing. On x86_64, the asm glue protects us from nested NMIs
417 * if the outer NMI came from kernel mode, but we can still nest if the
418 * outer NMI came from user mode.
419 *
420 * To handle these nested NMIs, we have three states:
421 *
422 * 1) not running
423 * 2) executing
424 * 3) latched
425 *
426 * When no NMI is in progress, it is in the "not running" state.
427 * When an NMI comes in, it goes into the "executing" state.
428 * Normally, if another NMI is triggered, it does not interrupt
429 * the running NMI and the HW will simply latch it so that when
430 * the first NMI finishes, it will restart the second NMI.
431 * (Note, the latch is binary, thus multiple NMIs triggering,
432 * when one is running, are ignored. Only one NMI is restarted.)
433 *
434 * If an NMI executes an iret, another NMI can preempt it. We do not
435 * want to allow this new NMI to run, but we want to execute it when the
436 * first one finishes. We set the state to "latched", and the exit of
437 * the first NMI will perform a dec_return, if the result is zero
438 * (NOT_RUNNING), then it will simply exit the NMI handler. If not, the
439 * dec_return would have set the state to NMI_EXECUTING (what we want it
440 * to be when we are running). In this case, we simply jump back to
441 * rerun the NMI handler again, and restart the 'latched' NMI.
442 *
443 * No trap (breakpoint or page fault) should be hit before nmi_restart,
444 * thus there is no race between the first check of state for NOT_RUNNING
445 * and setting it to NMI_EXECUTING. The HW will prevent nested NMIs
446 * at this point.
447 *
448 * In case the NMI takes a page fault, we need to save off the CR2
449 * because the NMI could have preempted another page fault and corrupt
450 * the CR2 that is about to be read. As nested NMIs must be restarted
451 * and they can not take breakpoints or page faults, the update of the
452 * CR2 must be done before converting the nmi state back to NOT_RUNNING.
453 * Otherwise, there would be a race of another nested NMI coming in
454 * after setting state to NOT_RUNNING but before updating the nmi_cr2.
455 */
456 enum nmi_states {
457 NMI_NOT_RUNNING = 0,
458 NMI_EXECUTING,
459 NMI_LATCHED,
460 };
461 static DEFINE_PER_CPU(enum nmi_states, nmi_state);
462 static DEFINE_PER_CPU(unsigned long, nmi_cr2);
463
464 #ifdef CONFIG_X86_64
465 /*
466 * In x86_64, we need to handle breakpoint -> NMI -> breakpoint. Without
467 * some care, the inner breakpoint will clobber the outer breakpoint's
468 * stack.
469 *
470 * If a breakpoint is being processed, and the debug stack is being
471 * used, if an NMI comes in and also hits a breakpoint, the stack
472 * pointer will be set to the same fixed address as the breakpoint that
473 * was interrupted, causing that stack to be corrupted. To handle this
474 * case, check if the stack that was interrupted is the debug stack, and
475 * if so, change the IDT so that new breakpoints will use the current
476 * stack and not switch to the fixed address. On return of the NMI,
477 * switch back to the original IDT.
478 */
479 static DEFINE_PER_CPU(int, update_debug_stack);
480 #endif
481
482 dotraplinkage notrace void
do_nmi(struct pt_regs * regs,long error_code)483 do_nmi(struct pt_regs *regs, long error_code)
484 {
485 if (this_cpu_read(nmi_state) != NMI_NOT_RUNNING) {
486 this_cpu_write(nmi_state, NMI_LATCHED);
487 return;
488 }
489 this_cpu_write(nmi_state, NMI_EXECUTING);
490 this_cpu_write(nmi_cr2, read_cr2());
491 nmi_restart:
492
493 #ifdef CONFIG_X86_64
494 /*
495 * If we interrupted a breakpoint, it is possible that
496 * the nmi handler will have breakpoints too. We need to
497 * change the IDT such that breakpoints that happen here
498 * continue to use the NMI stack.
499 */
500 if (unlikely(is_debug_stack(regs->sp))) {
501 debug_stack_set_zero();
502 this_cpu_write(update_debug_stack, 1);
503 }
504 #endif
505
506 nmi_enter();
507
508 inc_irq_stat(__nmi_count);
509
510 if (!ignore_nmis)
511 default_do_nmi(regs);
512
513 nmi_exit();
514
515 #ifdef CONFIG_X86_64
516 if (unlikely(this_cpu_read(update_debug_stack))) {
517 debug_stack_reset();
518 this_cpu_write(update_debug_stack, 0);
519 }
520 #endif
521
522 if (unlikely(this_cpu_read(nmi_cr2) != read_cr2()))
523 write_cr2(this_cpu_read(nmi_cr2));
524 if (this_cpu_dec_return(nmi_state))
525 goto nmi_restart;
526
527 if (user_mode(regs))
528 mds_user_clear_cpu_buffers();
529 }
530 NOKPROBE_SYMBOL(do_nmi);
531
stop_nmi(void)532 void stop_nmi(void)
533 {
534 ignore_nmis++;
535 }
536
restart_nmi(void)537 void restart_nmi(void)
538 {
539 ignore_nmis--;
540 }
541
542 /* reset the back-to-back NMI logic */
local_touch_nmi(void)543 void local_touch_nmi(void)
544 {
545 __this_cpu_write(last_nmi_rip, 0);
546 }
547 EXPORT_SYMBOL_GPL(local_touch_nmi);
548