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1 #ifndef _ASM_X86_MCE_H
2 #define _ASM_X86_MCE_H
3 
4 #include <uapi/asm/mce.h>
5 
6 /*
7  * Machine Check support for x86
8  */
9 
10 /* MCG_CAP register defines */
11 #define MCG_BANKCNT_MASK	0xff         /* Number of Banks */
12 #define MCG_CTL_P		(1ULL<<8)    /* MCG_CTL register available */
13 #define MCG_EXT_P		(1ULL<<9)    /* Extended registers available */
14 #define MCG_CMCI_P		(1ULL<<10)   /* CMCI supported */
15 #define MCG_EXT_CNT_MASK	0xff0000     /* Number of Extended registers */
16 #define MCG_EXT_CNT_SHIFT	16
17 #define MCG_EXT_CNT(c)		(((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
18 #define MCG_SER_P		(1ULL<<24)   /* MCA recovery/new status bits */
19 #define MCG_ELOG_P		(1ULL<<26)   /* Extended error log supported */
20 #define MCG_LMCE_P		(1ULL<<27)   /* Local machine check supported */
21 
22 /* MCG_STATUS register defines */
23 #define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
24 #define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
25 #define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
26 #define MCG_STATUS_LMCES (1ULL<<3)   /* LMCE signaled */
27 
28 /* MCG_EXT_CTL register defines */
29 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Enable LMCE */
30 
31 /* MCi_STATUS register defines */
32 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
33 #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
34 #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
35 #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
36 #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
37 #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
38 #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
39 #define MCI_STATUS_S	 (1ULL<<56)  /* Signaled machine check */
40 #define MCI_STATUS_AR	 (1ULL<<55)  /* Action required */
41 
42 /* AMD-specific bits */
43 #define MCI_STATUS_DEFERRED	(1ULL<<44)  /* declare an uncorrected error */
44 #define MCI_STATUS_POISON	(1ULL<<43)  /* access poisonous data */
45 
46 /*
47  * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
48  * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
49  * errors to indicate that errors are being filtered by hardware.
50  * We should mask out bit 12 when looking for specific signatures
51  * of uncorrected errors - so the F bit is deliberately skipped
52  * in this #define.
53  */
54 #define MCACOD		  0xefff     /* MCA Error Code */
55 
56 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
57 #define MCACOD_SCRUB	0x00C0	/* 0xC0-0xCF Memory Scrubbing */
58 #define MCACOD_SCRUBMSK	0xeff0	/* Skip bit 12 ('F' bit) */
59 #define MCACOD_L3WB	0x017A	/* L3 Explicit Writeback */
60 #define MCACOD_DATA	0x0134	/* Data Load */
61 #define MCACOD_INSTR	0x0150	/* Instruction Fetch */
62 
63 /* MCi_MISC register defines */
64 #define MCI_MISC_ADDR_LSB(m)	((m) & 0x3f)
65 #define MCI_MISC_ADDR_MODE(m)	(((m) >> 6) & 7)
66 #define  MCI_MISC_ADDR_SEGOFF	0	/* segment offset */
67 #define  MCI_MISC_ADDR_LINEAR	1	/* linear address */
68 #define  MCI_MISC_ADDR_PHYS	2	/* physical address */
69 #define  MCI_MISC_ADDR_MEM	3	/* memory address */
70 #define  MCI_MISC_ADDR_GENERIC	7	/* generic */
71 
72 /* CTL2 register defines */
73 #define MCI_CTL2_CMCI_EN		(1ULL << 30)
74 #define MCI_CTL2_CMCI_THRESHOLD_MASK	0x7fffULL
75 
76 #define MCJ_CTX_MASK		3
77 #define MCJ_CTX(flags)		((flags) & MCJ_CTX_MASK)
78 #define MCJ_CTX_RANDOM		0    /* inject context: random */
79 #define MCJ_CTX_PROCESS		0x1  /* inject context: process */
80 #define MCJ_CTX_IRQ		0x2  /* inject context: IRQ */
81 #define MCJ_NMI_BROADCAST	0x4  /* do NMI broadcasting */
82 #define MCJ_EXCEPTION		0x8  /* raise as exception */
83 #define MCJ_IRQ_BROADCAST	0x10 /* do IRQ broadcasting */
84 
85 #define MCE_OVERFLOW 0		/* bit 0 in flags means overflow */
86 
87 /* Software defined banks */
88 #define MCE_EXTENDED_BANK	128
89 #define MCE_THERMAL_BANK	(MCE_EXTENDED_BANK + 0)
90 
91 #define MCE_LOG_LEN 32
92 #define MCE_LOG_SIGNATURE	"MACHINECHECK"
93 
94 /*
95  * This structure contains all data related to the MCE log.  Also
96  * carries a signature to make it easier to find from external
97  * debugging tools.  Each entry is only valid when its finished flag
98  * is set.
99  */
100 struct mce_log {
101 	char signature[12]; /* "MACHINECHECK" */
102 	unsigned len;	    /* = MCE_LOG_LEN */
103 	unsigned next;
104 	unsigned flags;
105 	unsigned recordlen;	/* length of struct mce */
106 	struct mce entry[MCE_LOG_LEN];
107 };
108 
109 struct mca_config {
110 	bool dont_log_ce;
111 	bool cmci_disabled;
112 	bool lmce_disabled;
113 	bool ignore_ce;
114 	bool disabled;
115 	bool ser;
116 	bool bios_cmci_threshold;
117 	u8 banks;
118 	s8 bootlog;
119 	int tolerant;
120 	int monarch_timeout;
121 	int panic_timeout;
122 	u32 rip_msr;
123 };
124 
125 struct mce_vendor_flags {
126 	/*
127 	 * Indicates that overflow conditions are not fatal, when set.
128 	 */
129 	__u64 overflow_recov	: 1,
130 
131 	/*
132 	 * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and
133 	 * Recovery. It indicates support for data poisoning in HW and deferred
134 	 * error interrupts.
135 	 */
136 	      succor		: 1,
137 
138 	/*
139 	 * (AMD) SMCA: This bit indicates support for Scalable MCA which expands
140 	 * the register space for each MCA bank and also increases number of
141 	 * banks. Also, to accommodate the new banks and registers, the MCA
142 	 * register space is moved to a new MSR range.
143 	 */
144 	      smca		: 1,
145 
146 	      __reserved_0	: 61;
147 };
148 extern struct mce_vendor_flags mce_flags;
149 
150 extern struct mca_config mca_cfg;
151 extern void mce_register_decode_chain(struct notifier_block *nb);
152 extern void mce_unregister_decode_chain(struct notifier_block *nb);
153 
154 #include <linux/percpu.h>
155 #include <linux/atomic.h>
156 
157 extern int mce_p5_enabled;
158 
159 #ifdef CONFIG_X86_MCE
160 int mcheck_init(void);
161 void mcheck_cpu_init(struct cpuinfo_x86 *c);
162 void mcheck_cpu_clear(struct cpuinfo_x86 *c);
163 void mcheck_vendor_init_severity(void);
164 #else
mcheck_init(void)165 static inline int mcheck_init(void) { return 0; }
mcheck_cpu_init(struct cpuinfo_x86 * c)166 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
mcheck_cpu_clear(struct cpuinfo_x86 * c)167 static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
mcheck_vendor_init_severity(void)168 static inline void mcheck_vendor_init_severity(void) {}
169 #endif
170 
171 #ifdef CONFIG_X86_ANCIENT_MCE
172 void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
173 void winchip_mcheck_init(struct cpuinfo_x86 *c);
enable_p5_mce(void)174 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
175 #else
intel_p5_mcheck_init(struct cpuinfo_x86 * c)176 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
winchip_mcheck_init(struct cpuinfo_x86 * c)177 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
enable_p5_mce(void)178 static inline void enable_p5_mce(void) {}
179 #endif
180 
181 void mce_setup(struct mce *m);
182 void mce_log(struct mce *m);
183 DECLARE_PER_CPU(struct device *, mce_device);
184 
185 /*
186  * Maximum banks number.
187  * This is the limit of the current register layout on
188  * Intel CPUs.
189  */
190 #define MAX_NR_BANKS 32
191 
192 #ifdef CONFIG_X86_MCE_INTEL
193 void mce_intel_feature_init(struct cpuinfo_x86 *c);
194 void mce_intel_feature_clear(struct cpuinfo_x86 *c);
195 void cmci_clear(void);
196 void cmci_reenable(void);
197 void cmci_rediscover(void);
198 void cmci_recheck(void);
199 #else
mce_intel_feature_init(struct cpuinfo_x86 * c)200 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
mce_intel_feature_clear(struct cpuinfo_x86 * c)201 static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
cmci_clear(void)202 static inline void cmci_clear(void) {}
cmci_reenable(void)203 static inline void cmci_reenable(void) {}
cmci_rediscover(void)204 static inline void cmci_rediscover(void) {}
cmci_recheck(void)205 static inline void cmci_recheck(void) {}
206 #endif
207 
208 #ifdef CONFIG_X86_MCE_AMD
209 void mce_amd_feature_init(struct cpuinfo_x86 *c);
210 #else
mce_amd_feature_init(struct cpuinfo_x86 * c)211 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
212 #endif
213 
214 int mce_available(struct cpuinfo_x86 *c);
215 
216 DECLARE_PER_CPU(unsigned, mce_exception_count);
217 DECLARE_PER_CPU(unsigned, mce_poll_count);
218 
219 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
220 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
221 
222 enum mcp_flags {
223 	MCP_TIMESTAMP	= BIT(0),	/* log time stamp */
224 	MCP_UC		= BIT(1),	/* log uncorrected errors */
225 	MCP_DONTLOG	= BIT(2),	/* only clear, don't log */
226 };
227 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
228 
229 int mce_notify_irq(void);
230 
231 DECLARE_PER_CPU(struct mce, injectm);
232 
233 extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
234 				    const char __user *ubuf,
235 				    size_t usize, loff_t *off));
236 
237 /* Disable CMCI/polling for MCA bank claimed by firmware */
238 extern void mce_disable_bank(int bank);
239 
240 /*
241  * Exception handler
242  */
243 
244 /* Call the installed machine check handler for this CPU setup. */
245 extern void (*machine_check_vector)(struct pt_regs *, long error_code);
246 void do_machine_check(struct pt_regs *, long);
247 
248 /*
249  * Threshold handler
250  */
251 
252 extern void (*mce_threshold_vector)(void);
253 extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
254 
255 /* Deferred error interrupt handler */
256 extern void (*deferred_error_int_vector)(void);
257 
258 /*
259  * Thermal handler
260  */
261 
262 void intel_init_thermal(struct cpuinfo_x86 *c);
263 
264 void mce_log_therm_throt_event(__u64 status);
265 
266 /* Interrupt Handler for core thermal thresholds */
267 extern int (*platform_thermal_notify)(__u64 msr_val);
268 
269 /* Interrupt Handler for package thermal thresholds */
270 extern int (*platform_thermal_package_notify)(__u64 msr_val);
271 
272 /* Callback support of rate control, return true, if
273  * callback has rate control */
274 extern bool (*platform_thermal_package_rate_control)(void);
275 
276 #ifdef CONFIG_X86_THERMAL_VECTOR
277 extern void mcheck_intel_therm_init(void);
278 #else
mcheck_intel_therm_init(void)279 static inline void mcheck_intel_therm_init(void) { }
280 #endif
281 
282 /*
283  * Used by APEI to report memory error via /dev/mcelog
284  */
285 
286 struct cper_sec_mem_err;
287 extern void apei_mce_report_mem_error(int corrected,
288 				      struct cper_sec_mem_err *mem_err);
289 
290 #endif /* _ASM_X86_MCE_H */
291