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1 /*
2  * srmmu.c:  SRMMU specific routines for memory management.
3  *
4  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
5  * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
6  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
7  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
9  */
10 
11 #include <linux/seq_file.h>
12 #include <linux/spinlock.h>
13 #include <linux/bootmem.h>
14 #include <linux/pagemap.h>
15 #include <linux/vmalloc.h>
16 #include <linux/kdebug.h>
17 #include <linux/export.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/log2.h>
21 #include <linux/gfp.h>
22 #include <linux/fs.h>
23 #include <linux/mm.h>
24 
25 #include <asm/mmu_context.h>
26 #include <asm/cacheflush.h>
27 #include <asm/tlbflush.h>
28 #include <asm/io-unit.h>
29 #include <asm/pgalloc.h>
30 #include <asm/pgtable.h>
31 #include <asm/bitext.h>
32 #include <asm/vaddrs.h>
33 #include <asm/cache.h>
34 #include <asm/traps.h>
35 #include <asm/oplib.h>
36 #include <asm/mbus.h>
37 #include <asm/page.h>
38 #include <asm/asi.h>
39 #include <asm/msi.h>
40 #include <asm/smp.h>
41 #include <asm/io.h>
42 
43 /* Now the cpu specific definitions. */
44 #include <asm/turbosparc.h>
45 #include <asm/tsunami.h>
46 #include <asm/viking.h>
47 #include <asm/swift.h>
48 #include <asm/leon.h>
49 #include <asm/mxcc.h>
50 #include <asm/ross.h>
51 
52 #include "mm_32.h"
53 
54 enum mbus_module srmmu_modtype;
55 static unsigned int hwbug_bitmask;
56 int vac_cache_size;
57 int vac_line_size;
58 
59 extern struct resource sparc_iomap;
60 
61 extern unsigned long last_valid_pfn;
62 
63 static pgd_t *srmmu_swapper_pg_dir;
64 
65 const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops;
66 EXPORT_SYMBOL(sparc32_cachetlb_ops);
67 
68 #ifdef CONFIG_SMP
69 const struct sparc32_cachetlb_ops *local_ops;
70 
71 #define FLUSH_BEGIN(mm)
72 #define FLUSH_END
73 #else
74 #define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) {
75 #define FLUSH_END	}
76 #endif
77 
78 int flush_page_for_dma_global = 1;
79 
80 char *srmmu_name;
81 
82 ctxd_t *srmmu_ctx_table_phys;
83 static ctxd_t *srmmu_context_table;
84 
85 int viking_mxcc_present;
86 static DEFINE_SPINLOCK(srmmu_context_spinlock);
87 
88 static int is_hypersparc;
89 
90 static int srmmu_cache_pagetables;
91 
92 /* these will be initialized in srmmu_nocache_calcsize() */
93 static unsigned long srmmu_nocache_size;
94 static unsigned long srmmu_nocache_end;
95 
96 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
97 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
98 
99 /* The context table is a nocache user with the biggest alignment needs. */
100 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
101 
102 void *srmmu_nocache_pool;
103 static struct bit_map srmmu_nocache_map;
104 
srmmu_pmd_none(pmd_t pmd)105 static inline int srmmu_pmd_none(pmd_t pmd)
106 { return !(pmd_val(pmd) & 0xFFFFFFF); }
107 
108 /* XXX should we hyper_flush_whole_icache here - Anton */
srmmu_ctxd_set(ctxd_t * ctxp,pgd_t * pgdp)109 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
110 { set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
111 
pmd_set(pmd_t * pmdp,pte_t * ptep)112 void pmd_set(pmd_t *pmdp, pte_t *ptep)
113 {
114 	unsigned long ptp;	/* Physical address, shifted right by 4 */
115 	int i;
116 
117 	ptp = __nocache_pa((unsigned long) ptep) >> 4;
118 	for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
119 		set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
120 		ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
121 	}
122 }
123 
pmd_populate(struct mm_struct * mm,pmd_t * pmdp,struct page * ptep)124 void pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep)
125 {
126 	unsigned long ptp;	/* Physical address, shifted right by 4 */
127 	int i;
128 
129 	ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4);	/* watch for overflow */
130 	for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
131 		set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
132 		ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
133 	}
134 }
135 
136 /* Find an entry in the third-level page table.. */
pte_offset_kernel(pmd_t * dir,unsigned long address)137 pte_t *pte_offset_kernel(pmd_t *dir, unsigned long address)
138 {
139 	void *pte;
140 
141 	pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
142 	return (pte_t *) pte +
143 	    ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
144 }
145 
146 /*
147  * size: bytes to allocate in the nocache area.
148  * align: bytes, number to align at.
149  * Returns the virtual address of the allocated area.
150  */
__srmmu_get_nocache(int size,int align)151 static void *__srmmu_get_nocache(int size, int align)
152 {
153 	int offset;
154 	unsigned long addr;
155 
156 	if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
157 		printk(KERN_ERR "Size 0x%x too small for nocache request\n",
158 		       size);
159 		size = SRMMU_NOCACHE_BITMAP_SHIFT;
160 	}
161 	if (size & (SRMMU_NOCACHE_BITMAP_SHIFT - 1)) {
162 		printk(KERN_ERR "Size 0x%x unaligned int nocache request\n",
163 		       size);
164 		size += SRMMU_NOCACHE_BITMAP_SHIFT - 1;
165 	}
166 	BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
167 
168 	offset = bit_map_string_get(&srmmu_nocache_map,
169 				    size >> SRMMU_NOCACHE_BITMAP_SHIFT,
170 				    align >> SRMMU_NOCACHE_BITMAP_SHIFT);
171 	if (offset == -1) {
172 		printk(KERN_ERR "srmmu: out of nocache %d: %d/%d\n",
173 		       size, (int) srmmu_nocache_size,
174 		       srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
175 		return NULL;
176 	}
177 
178 	addr = SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT);
179 	return (void *)addr;
180 }
181 
srmmu_get_nocache(int size,int align)182 void *srmmu_get_nocache(int size, int align)
183 {
184 	void *tmp;
185 
186 	tmp = __srmmu_get_nocache(size, align);
187 
188 	if (tmp)
189 		memset(tmp, 0, size);
190 
191 	return tmp;
192 }
193 
srmmu_free_nocache(void * addr,int size)194 void srmmu_free_nocache(void *addr, int size)
195 {
196 	unsigned long vaddr;
197 	int offset;
198 
199 	vaddr = (unsigned long)addr;
200 	if (vaddr < SRMMU_NOCACHE_VADDR) {
201 		printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
202 		    vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
203 		BUG();
204 	}
205 	if (vaddr + size > srmmu_nocache_end) {
206 		printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
207 		    vaddr, srmmu_nocache_end);
208 		BUG();
209 	}
210 	if (!is_power_of_2(size)) {
211 		printk("Size 0x%x is not a power of 2\n", size);
212 		BUG();
213 	}
214 	if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
215 		printk("Size 0x%x is too small\n", size);
216 		BUG();
217 	}
218 	if (vaddr & (size - 1)) {
219 		printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
220 		BUG();
221 	}
222 
223 	offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
224 	size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
225 
226 	bit_map_clear(&srmmu_nocache_map, offset, size);
227 }
228 
229 static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
230 						 unsigned long end);
231 
232 /* Return how much physical memory we have.  */
probe_memory(void)233 static unsigned long __init probe_memory(void)
234 {
235 	unsigned long total = 0;
236 	int i;
237 
238 	for (i = 0; sp_banks[i].num_bytes; i++)
239 		total += sp_banks[i].num_bytes;
240 
241 	return total;
242 }
243 
244 /*
245  * Reserve nocache dynamically proportionally to the amount of
246  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
247  */
srmmu_nocache_calcsize(void)248 static void __init srmmu_nocache_calcsize(void)
249 {
250 	unsigned long sysmemavail = probe_memory() / 1024;
251 	int srmmu_nocache_npages;
252 
253 	srmmu_nocache_npages =
254 		sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
255 
256  /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
257 	// if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
258 	if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
259 		srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
260 
261 	/* anything above 1280 blows up */
262 	if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
263 		srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
264 
265 	srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
266 	srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
267 }
268 
srmmu_nocache_init(void)269 static void __init srmmu_nocache_init(void)
270 {
271 	void *srmmu_nocache_bitmap;
272 	unsigned int bitmap_bits;
273 	pgd_t *pgd;
274 	pmd_t *pmd;
275 	pte_t *pte;
276 	unsigned long paddr, vaddr;
277 	unsigned long pteval;
278 
279 	bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
280 
281 	srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
282 		SRMMU_NOCACHE_ALIGN_MAX, 0UL);
283 	memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
284 
285 	srmmu_nocache_bitmap =
286 		__alloc_bootmem(BITS_TO_LONGS(bitmap_bits) * sizeof(long),
287 				SMP_CACHE_BYTES, 0UL);
288 	bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
289 
290 	srmmu_swapper_pg_dir = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
291 	memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
292 	init_mm.pgd = srmmu_swapper_pg_dir;
293 
294 	srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
295 
296 	paddr = __pa((unsigned long)srmmu_nocache_pool);
297 	vaddr = SRMMU_NOCACHE_VADDR;
298 
299 	while (vaddr < srmmu_nocache_end) {
300 		pgd = pgd_offset_k(vaddr);
301 		pmd = pmd_offset(__nocache_fix(pgd), vaddr);
302 		pte = pte_offset_kernel(__nocache_fix(pmd), vaddr);
303 
304 		pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
305 
306 		if (srmmu_cache_pagetables)
307 			pteval |= SRMMU_CACHE;
308 
309 		set_pte(__nocache_fix(pte), __pte(pteval));
310 
311 		vaddr += PAGE_SIZE;
312 		paddr += PAGE_SIZE;
313 	}
314 
315 	flush_cache_all();
316 	flush_tlb_all();
317 }
318 
get_pgd_fast(void)319 pgd_t *get_pgd_fast(void)
320 {
321 	pgd_t *pgd = NULL;
322 
323 	pgd = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
324 	if (pgd) {
325 		pgd_t *init = pgd_offset_k(0);
326 		memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
327 		memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
328 						(PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
329 	}
330 
331 	return pgd;
332 }
333 
334 /*
335  * Hardware needs alignment to 256 only, but we align to whole page size
336  * to reduce fragmentation problems due to the buddy principle.
337  * XXX Provide actual fragmentation statistics in /proc.
338  *
339  * Alignments up to the page size are the same for physical and virtual
340  * addresses of the nocache area.
341  */
pte_alloc_one(struct mm_struct * mm,unsigned long address)342 pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
343 {
344 	unsigned long pte;
345 	struct page *page;
346 
347 	if ((pte = (unsigned long)pte_alloc_one_kernel(mm, address)) == 0)
348 		return NULL;
349 	page = pfn_to_page(__nocache_pa(pte) >> PAGE_SHIFT);
350 	if (!pgtable_page_ctor(page)) {
351 		__free_page(page);
352 		return NULL;
353 	}
354 	return page;
355 }
356 
pte_free(struct mm_struct * mm,pgtable_t pte)357 void pte_free(struct mm_struct *mm, pgtable_t pte)
358 {
359 	unsigned long p;
360 
361 	pgtable_page_dtor(pte);
362 	p = (unsigned long)page_address(pte);	/* Cached address (for test) */
363 	if (p == 0)
364 		BUG();
365 	p = page_to_pfn(pte) << PAGE_SHIFT;	/* Physical address */
366 
367 	/* free non cached virtual address*/
368 	srmmu_free_nocache(__nocache_va(p), PTE_SIZE);
369 }
370 
371 /* context handling - a dynamically sized pool is used */
372 #define NO_CONTEXT	-1
373 
374 struct ctx_list {
375 	struct ctx_list *next;
376 	struct ctx_list *prev;
377 	unsigned int ctx_number;
378 	struct mm_struct *ctx_mm;
379 };
380 
381 static struct ctx_list *ctx_list_pool;
382 static struct ctx_list ctx_free;
383 static struct ctx_list ctx_used;
384 
385 /* At boot time we determine the number of contexts */
386 static int num_contexts;
387 
remove_from_ctx_list(struct ctx_list * entry)388 static inline void remove_from_ctx_list(struct ctx_list *entry)
389 {
390 	entry->next->prev = entry->prev;
391 	entry->prev->next = entry->next;
392 }
393 
add_to_ctx_list(struct ctx_list * head,struct ctx_list * entry)394 static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
395 {
396 	entry->next = head;
397 	(entry->prev = head->prev)->next = entry;
398 	head->prev = entry;
399 }
400 #define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
401 #define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
402 
403 
alloc_context(struct mm_struct * old_mm,struct mm_struct * mm)404 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
405 {
406 	struct ctx_list *ctxp;
407 
408 	ctxp = ctx_free.next;
409 	if (ctxp != &ctx_free) {
410 		remove_from_ctx_list(ctxp);
411 		add_to_used_ctxlist(ctxp);
412 		mm->context = ctxp->ctx_number;
413 		ctxp->ctx_mm = mm;
414 		return;
415 	}
416 	ctxp = ctx_used.next;
417 	if (ctxp->ctx_mm == old_mm)
418 		ctxp = ctxp->next;
419 	if (ctxp == &ctx_used)
420 		panic("out of mmu contexts");
421 	flush_cache_mm(ctxp->ctx_mm);
422 	flush_tlb_mm(ctxp->ctx_mm);
423 	remove_from_ctx_list(ctxp);
424 	add_to_used_ctxlist(ctxp);
425 	ctxp->ctx_mm->context = NO_CONTEXT;
426 	ctxp->ctx_mm = mm;
427 	mm->context = ctxp->ctx_number;
428 }
429 
free_context(int context)430 static inline void free_context(int context)
431 {
432 	struct ctx_list *ctx_old;
433 
434 	ctx_old = ctx_list_pool + context;
435 	remove_from_ctx_list(ctx_old);
436 	add_to_free_ctxlist(ctx_old);
437 }
438 
sparc_context_init(int numctx)439 static void __init sparc_context_init(int numctx)
440 {
441 	int ctx;
442 	unsigned long size;
443 
444 	size = numctx * sizeof(struct ctx_list);
445 	ctx_list_pool = __alloc_bootmem(size, SMP_CACHE_BYTES, 0UL);
446 
447 	for (ctx = 0; ctx < numctx; ctx++) {
448 		struct ctx_list *clist;
449 
450 		clist = (ctx_list_pool + ctx);
451 		clist->ctx_number = ctx;
452 		clist->ctx_mm = NULL;
453 	}
454 	ctx_free.next = ctx_free.prev = &ctx_free;
455 	ctx_used.next = ctx_used.prev = &ctx_used;
456 	for (ctx = 0; ctx < numctx; ctx++)
457 		add_to_free_ctxlist(ctx_list_pool + ctx);
458 }
459 
switch_mm(struct mm_struct * old_mm,struct mm_struct * mm,struct task_struct * tsk)460 void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
461 	       struct task_struct *tsk)
462 {
463 	unsigned long flags;
464 
465 	if (mm->context == NO_CONTEXT) {
466 		spin_lock_irqsave(&srmmu_context_spinlock, flags);
467 		alloc_context(old_mm, mm);
468 		spin_unlock_irqrestore(&srmmu_context_spinlock, flags);
469 		srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
470 	}
471 
472 	if (sparc_cpu_model == sparc_leon)
473 		leon_switch_mm();
474 
475 	if (is_hypersparc)
476 		hyper_flush_whole_icache();
477 
478 	srmmu_set_context(mm->context);
479 }
480 
481 /* Low level IO area allocation on the SRMMU. */
srmmu_mapioaddr(unsigned long physaddr,unsigned long virt_addr,int bus_type)482 static inline void srmmu_mapioaddr(unsigned long physaddr,
483 				   unsigned long virt_addr, int bus_type)
484 {
485 	pgd_t *pgdp;
486 	pmd_t *pmdp;
487 	pte_t *ptep;
488 	unsigned long tmp;
489 
490 	physaddr &= PAGE_MASK;
491 	pgdp = pgd_offset_k(virt_addr);
492 	pmdp = pmd_offset(pgdp, virt_addr);
493 	ptep = pte_offset_kernel(pmdp, virt_addr);
494 	tmp = (physaddr >> 4) | SRMMU_ET_PTE;
495 
496 	/* I need to test whether this is consistent over all
497 	 * sun4m's.  The bus_type represents the upper 4 bits of
498 	 * 36-bit physical address on the I/O space lines...
499 	 */
500 	tmp |= (bus_type << 28);
501 	tmp |= SRMMU_PRIV;
502 	__flush_page_to_ram(virt_addr);
503 	set_pte(ptep, __pte(tmp));
504 }
505 
srmmu_mapiorange(unsigned int bus,unsigned long xpa,unsigned long xva,unsigned int len)506 void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
507 		      unsigned long xva, unsigned int len)
508 {
509 	while (len != 0) {
510 		len -= PAGE_SIZE;
511 		srmmu_mapioaddr(xpa, xva, bus);
512 		xva += PAGE_SIZE;
513 		xpa += PAGE_SIZE;
514 	}
515 	flush_tlb_all();
516 }
517 
srmmu_unmapioaddr(unsigned long virt_addr)518 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
519 {
520 	pgd_t *pgdp;
521 	pmd_t *pmdp;
522 	pte_t *ptep;
523 
524 	pgdp = pgd_offset_k(virt_addr);
525 	pmdp = pmd_offset(pgdp, virt_addr);
526 	ptep = pte_offset_kernel(pmdp, virt_addr);
527 
528 	/* No need to flush uncacheable page. */
529 	__pte_clear(ptep);
530 }
531 
srmmu_unmapiorange(unsigned long virt_addr,unsigned int len)532 void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
533 {
534 	while (len != 0) {
535 		len -= PAGE_SIZE;
536 		srmmu_unmapioaddr(virt_addr);
537 		virt_addr += PAGE_SIZE;
538 	}
539 	flush_tlb_all();
540 }
541 
542 /* tsunami.S */
543 extern void tsunami_flush_cache_all(void);
544 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
545 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
546 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
547 extern void tsunami_flush_page_to_ram(unsigned long page);
548 extern void tsunami_flush_page_for_dma(unsigned long page);
549 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
550 extern void tsunami_flush_tlb_all(void);
551 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
552 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
553 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
554 extern void tsunami_setup_blockops(void);
555 
556 /* swift.S */
557 extern void swift_flush_cache_all(void);
558 extern void swift_flush_cache_mm(struct mm_struct *mm);
559 extern void swift_flush_cache_range(struct vm_area_struct *vma,
560 				    unsigned long start, unsigned long end);
561 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
562 extern void swift_flush_page_to_ram(unsigned long page);
563 extern void swift_flush_page_for_dma(unsigned long page);
564 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
565 extern void swift_flush_tlb_all(void);
566 extern void swift_flush_tlb_mm(struct mm_struct *mm);
567 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
568 				  unsigned long start, unsigned long end);
569 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
570 
571 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
572 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
573 {
574 	int cctx, ctx1;
575 
576 	page &= PAGE_MASK;
577 	if ((ctx1 = vma->vm_mm->context) != -1) {
578 		cctx = srmmu_get_context();
579 /* Is context # ever different from current context? P3 */
580 		if (cctx != ctx1) {
581 			printk("flush ctx %02x curr %02x\n", ctx1, cctx);
582 			srmmu_set_context(ctx1);
583 			swift_flush_page(page);
584 			__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
585 					"r" (page), "i" (ASI_M_FLUSH_PROBE));
586 			srmmu_set_context(cctx);
587 		} else {
588 			 /* Rm. prot. bits from virt. c. */
589 			/* swift_flush_cache_all(); */
590 			/* swift_flush_cache_page(vma, page); */
591 			swift_flush_page(page);
592 
593 			__asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
594 				"r" (page), "i" (ASI_M_FLUSH_PROBE));
595 			/* same as above: srmmu_flush_tlb_page() */
596 		}
597 	}
598 }
599 #endif
600 
601 /*
602  * The following are all MBUS based SRMMU modules, and therefore could
603  * be found in a multiprocessor configuration.  On the whole, these
604  * chips seems to be much more touchy about DVMA and page tables
605  * with respect to cache coherency.
606  */
607 
608 /* viking.S */
609 extern void viking_flush_cache_all(void);
610 extern void viking_flush_cache_mm(struct mm_struct *mm);
611 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
612 				     unsigned long end);
613 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
614 extern void viking_flush_page_to_ram(unsigned long page);
615 extern void viking_flush_page_for_dma(unsigned long page);
616 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
617 extern void viking_flush_page(unsigned long page);
618 extern void viking_mxcc_flush_page(unsigned long page);
619 extern void viking_flush_tlb_all(void);
620 extern void viking_flush_tlb_mm(struct mm_struct *mm);
621 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
622 				   unsigned long end);
623 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
624 				  unsigned long page);
625 extern void sun4dsmp_flush_tlb_all(void);
626 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
627 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
628 				   unsigned long end);
629 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
630 				  unsigned long page);
631 
632 /* hypersparc.S */
633 extern void hypersparc_flush_cache_all(void);
634 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
635 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
636 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
637 extern void hypersparc_flush_page_to_ram(unsigned long page);
638 extern void hypersparc_flush_page_for_dma(unsigned long page);
639 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
640 extern void hypersparc_flush_tlb_all(void);
641 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
642 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
643 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
644 extern void hypersparc_setup_blockops(void);
645 
646 /*
647  * NOTE: All of this startup code assumes the low 16mb (approx.) of
648  *       kernel mappings are done with one single contiguous chunk of
649  *       ram.  On small ram machines (classics mainly) we only get
650  *       around 8mb mapped for us.
651  */
652 
early_pgtable_allocfail(char * type)653 static void __init early_pgtable_allocfail(char *type)
654 {
655 	prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
656 	prom_halt();
657 }
658 
srmmu_early_allocate_ptable_skeleton(unsigned long start,unsigned long end)659 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
660 							unsigned long end)
661 {
662 	pgd_t *pgdp;
663 	pmd_t *pmdp;
664 	pte_t *ptep;
665 
666 	while (start < end) {
667 		pgdp = pgd_offset_k(start);
668 		if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
669 			pmdp = __srmmu_get_nocache(
670 			    SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
671 			if (pmdp == NULL)
672 				early_pgtable_allocfail("pmd");
673 			memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
674 			pgd_set(__nocache_fix(pgdp), pmdp);
675 		}
676 		pmdp = pmd_offset(__nocache_fix(pgdp), start);
677 		if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
678 			ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
679 			if (ptep == NULL)
680 				early_pgtable_allocfail("pte");
681 			memset(__nocache_fix(ptep), 0, PTE_SIZE);
682 			pmd_set(__nocache_fix(pmdp), ptep);
683 		}
684 		if (start > (0xffffffffUL - PMD_SIZE))
685 			break;
686 		start = (start + PMD_SIZE) & PMD_MASK;
687 	}
688 }
689 
srmmu_allocate_ptable_skeleton(unsigned long start,unsigned long end)690 static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
691 						  unsigned long end)
692 {
693 	pgd_t *pgdp;
694 	pmd_t *pmdp;
695 	pte_t *ptep;
696 
697 	while (start < end) {
698 		pgdp = pgd_offset_k(start);
699 		if (pgd_none(*pgdp)) {
700 			pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
701 			if (pmdp == NULL)
702 				early_pgtable_allocfail("pmd");
703 			memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
704 			pgd_set(pgdp, pmdp);
705 		}
706 		pmdp = pmd_offset(pgdp, start);
707 		if (srmmu_pmd_none(*pmdp)) {
708 			ptep = __srmmu_get_nocache(PTE_SIZE,
709 							     PTE_SIZE);
710 			if (ptep == NULL)
711 				early_pgtable_allocfail("pte");
712 			memset(ptep, 0, PTE_SIZE);
713 			pmd_set(pmdp, ptep);
714 		}
715 		if (start > (0xffffffffUL - PMD_SIZE))
716 			break;
717 		start = (start + PMD_SIZE) & PMD_MASK;
718 	}
719 }
720 
721 /* These flush types are not available on all chips... */
srmmu_probe(unsigned long vaddr)722 static inline unsigned long srmmu_probe(unsigned long vaddr)
723 {
724 	unsigned long retval;
725 
726 	if (sparc_cpu_model != sparc_leon) {
727 
728 		vaddr &= PAGE_MASK;
729 		__asm__ __volatile__("lda [%1] %2, %0\n\t" :
730 				     "=r" (retval) :
731 				     "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
732 	} else {
733 		retval = leon_swprobe(vaddr, NULL);
734 	}
735 	return retval;
736 }
737 
738 /*
739  * This is much cleaner than poking around physical address space
740  * looking at the prom's page table directly which is what most
741  * other OS's do.  Yuck... this is much better.
742  */
srmmu_inherit_prom_mappings(unsigned long start,unsigned long end)743 static void __init srmmu_inherit_prom_mappings(unsigned long start,
744 					       unsigned long end)
745 {
746 	unsigned long probed;
747 	unsigned long addr;
748 	pgd_t *pgdp;
749 	pmd_t *pmdp;
750 	pte_t *ptep;
751 	int what; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
752 
753 	while (start <= end) {
754 		if (start == 0)
755 			break; /* probably wrap around */
756 		if (start == 0xfef00000)
757 			start = KADB_DEBUGGER_BEGVM;
758 		probed = srmmu_probe(start);
759 		if (!probed) {
760 			/* continue probing until we find an entry */
761 			start += PAGE_SIZE;
762 			continue;
763 		}
764 
765 		/* A red snapper, see what it really is. */
766 		what = 0;
767 		addr = start - PAGE_SIZE;
768 
769 		if (!(start & ~(SRMMU_REAL_PMD_MASK))) {
770 			if (srmmu_probe(addr + SRMMU_REAL_PMD_SIZE) == probed)
771 				what = 1;
772 		}
773 
774 		if (!(start & ~(SRMMU_PGDIR_MASK))) {
775 			if (srmmu_probe(addr + SRMMU_PGDIR_SIZE) == probed)
776 				what = 2;
777 		}
778 
779 		pgdp = pgd_offset_k(start);
780 		if (what == 2) {
781 			*(pgd_t *)__nocache_fix(pgdp) = __pgd(probed);
782 			start += SRMMU_PGDIR_SIZE;
783 			continue;
784 		}
785 		if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
786 			pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE,
787 						   SRMMU_PMD_TABLE_SIZE);
788 			if (pmdp == NULL)
789 				early_pgtable_allocfail("pmd");
790 			memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
791 			pgd_set(__nocache_fix(pgdp), pmdp);
792 		}
793 		pmdp = pmd_offset(__nocache_fix(pgdp), start);
794 		if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
795 			ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
796 			if (ptep == NULL)
797 				early_pgtable_allocfail("pte");
798 			memset(__nocache_fix(ptep), 0, PTE_SIZE);
799 			pmd_set(__nocache_fix(pmdp), ptep);
800 		}
801 		if (what == 1) {
802 			/* We bend the rule where all 16 PTPs in a pmd_t point
803 			 * inside the same PTE page, and we leak a perfectly
804 			 * good hardware PTE piece. Alternatives seem worse.
805 			 */
806 			unsigned int x;	/* Index of HW PMD in soft cluster */
807 			unsigned long *val;
808 			x = (start >> PMD_SHIFT) & 15;
809 			val = &pmdp->pmdv[x];
810 			*(unsigned long *)__nocache_fix(val) = probed;
811 			start += SRMMU_REAL_PMD_SIZE;
812 			continue;
813 		}
814 		ptep = pte_offset_kernel(__nocache_fix(pmdp), start);
815 		*(pte_t *)__nocache_fix(ptep) = __pte(probed);
816 		start += PAGE_SIZE;
817 	}
818 }
819 
820 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
821 
822 /* Create a third-level SRMMU 16MB page mapping. */
do_large_mapping(unsigned long vaddr,unsigned long phys_base)823 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
824 {
825 	pgd_t *pgdp = pgd_offset_k(vaddr);
826 	unsigned long big_pte;
827 
828 	big_pte = KERNEL_PTE(phys_base >> 4);
829 	*(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
830 }
831 
832 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
map_spbank(unsigned long vbase,int sp_entry)833 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
834 {
835 	unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
836 	unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
837 	unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
838 	/* Map "low" memory only */
839 	const unsigned long min_vaddr = PAGE_OFFSET;
840 	const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
841 
842 	if (vstart < min_vaddr || vstart >= max_vaddr)
843 		return vstart;
844 
845 	if (vend > max_vaddr || vend < min_vaddr)
846 		vend = max_vaddr;
847 
848 	while (vstart < vend) {
849 		do_large_mapping(vstart, pstart);
850 		vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
851 	}
852 	return vstart;
853 }
854 
map_kernel(void)855 static void __init map_kernel(void)
856 {
857 	int i;
858 
859 	if (phys_base > 0) {
860 		do_large_mapping(PAGE_OFFSET, phys_base);
861 	}
862 
863 	for (i = 0; sp_banks[i].num_bytes != 0; i++) {
864 		map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
865 	}
866 }
867 
868 void (*poke_srmmu)(void) = NULL;
869 
srmmu_paging_init(void)870 void __init srmmu_paging_init(void)
871 {
872 	int i;
873 	phandle cpunode;
874 	char node_str[128];
875 	pgd_t *pgd;
876 	pmd_t *pmd;
877 	pte_t *pte;
878 	unsigned long pages_avail;
879 
880 	init_mm.context = (unsigned long) NO_CONTEXT;
881 	sparc_iomap.start = SUN4M_IOBASE_VADDR;	/* 16MB of IOSPACE on all sun4m's. */
882 
883 	if (sparc_cpu_model == sun4d)
884 		num_contexts = 65536; /* We know it is Viking */
885 	else {
886 		/* Find the number of contexts on the srmmu. */
887 		cpunode = prom_getchild(prom_root_node);
888 		num_contexts = 0;
889 		while (cpunode != 0) {
890 			prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
891 			if (!strcmp(node_str, "cpu")) {
892 				num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
893 				break;
894 			}
895 			cpunode = prom_getsibling(cpunode);
896 		}
897 	}
898 
899 	if (!num_contexts) {
900 		prom_printf("Something wrong, can't find cpu node in paging_init.\n");
901 		prom_halt();
902 	}
903 
904 	pages_avail = 0;
905 	last_valid_pfn = bootmem_init(&pages_avail);
906 
907 	srmmu_nocache_calcsize();
908 	srmmu_nocache_init();
909 	srmmu_inherit_prom_mappings(0xfe400000, (LINUX_OPPROM_ENDVM - PAGE_SIZE));
910 	map_kernel();
911 
912 	/* ctx table has to be physically aligned to its size */
913 	srmmu_context_table = __srmmu_get_nocache(num_contexts * sizeof(ctxd_t), num_contexts * sizeof(ctxd_t));
914 	srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
915 
916 	for (i = 0; i < num_contexts; i++)
917 		srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
918 
919 	flush_cache_all();
920 	srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
921 #ifdef CONFIG_SMP
922 	/* Stop from hanging here... */
923 	local_ops->tlb_all();
924 #else
925 	flush_tlb_all();
926 #endif
927 	poke_srmmu();
928 
929 	srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
930 	srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
931 
932 	srmmu_allocate_ptable_skeleton(
933 		__fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
934 	srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
935 
936 	pgd = pgd_offset_k(PKMAP_BASE);
937 	pmd = pmd_offset(pgd, PKMAP_BASE);
938 	pte = pte_offset_kernel(pmd, PKMAP_BASE);
939 	pkmap_page_table = pte;
940 
941 	flush_cache_all();
942 	flush_tlb_all();
943 
944 	sparc_context_init(num_contexts);
945 
946 	kmap_init();
947 
948 	{
949 		unsigned long zones_size[MAX_NR_ZONES];
950 		unsigned long zholes_size[MAX_NR_ZONES];
951 		unsigned long npages;
952 		int znum;
953 
954 		for (znum = 0; znum < MAX_NR_ZONES; znum++)
955 			zones_size[znum] = zholes_size[znum] = 0;
956 
957 		npages = max_low_pfn - pfn_base;
958 
959 		zones_size[ZONE_DMA] = npages;
960 		zholes_size[ZONE_DMA] = npages - pages_avail;
961 
962 		npages = highend_pfn - max_low_pfn;
963 		zones_size[ZONE_HIGHMEM] = npages;
964 		zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
965 
966 		free_area_init_node(0, zones_size, pfn_base, zholes_size);
967 	}
968 }
969 
mmu_info(struct seq_file * m)970 void mmu_info(struct seq_file *m)
971 {
972 	seq_printf(m,
973 		   "MMU type\t: %s\n"
974 		   "contexts\t: %d\n"
975 		   "nocache total\t: %ld\n"
976 		   "nocache used\t: %d\n",
977 		   srmmu_name,
978 		   num_contexts,
979 		   srmmu_nocache_size,
980 		   srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
981 }
982 
init_new_context(struct task_struct * tsk,struct mm_struct * mm)983 int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
984 {
985 	mm->context = NO_CONTEXT;
986 	return 0;
987 }
988 
destroy_context(struct mm_struct * mm)989 void destroy_context(struct mm_struct *mm)
990 {
991 	unsigned long flags;
992 
993 	if (mm->context != NO_CONTEXT) {
994 		flush_cache_mm(mm);
995 		srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
996 		flush_tlb_mm(mm);
997 		spin_lock_irqsave(&srmmu_context_spinlock, flags);
998 		free_context(mm->context);
999 		spin_unlock_irqrestore(&srmmu_context_spinlock, flags);
1000 		mm->context = NO_CONTEXT;
1001 	}
1002 }
1003 
1004 /* Init various srmmu chip types. */
srmmu_is_bad(void)1005 static void __init srmmu_is_bad(void)
1006 {
1007 	prom_printf("Could not determine SRMMU chip type.\n");
1008 	prom_halt();
1009 }
1010 
init_vac_layout(void)1011 static void __init init_vac_layout(void)
1012 {
1013 	phandle nd;
1014 	int cache_lines;
1015 	char node_str[128];
1016 #ifdef CONFIG_SMP
1017 	int cpu = 0;
1018 	unsigned long max_size = 0;
1019 	unsigned long min_line_size = 0x10000000;
1020 #endif
1021 
1022 	nd = prom_getchild(prom_root_node);
1023 	while ((nd = prom_getsibling(nd)) != 0) {
1024 		prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1025 		if (!strcmp(node_str, "cpu")) {
1026 			vac_line_size = prom_getint(nd, "cache-line-size");
1027 			if (vac_line_size == -1) {
1028 				prom_printf("can't determine cache-line-size, halting.\n");
1029 				prom_halt();
1030 			}
1031 			cache_lines = prom_getint(nd, "cache-nlines");
1032 			if (cache_lines == -1) {
1033 				prom_printf("can't determine cache-nlines, halting.\n");
1034 				prom_halt();
1035 			}
1036 
1037 			vac_cache_size = cache_lines * vac_line_size;
1038 #ifdef CONFIG_SMP
1039 			if (vac_cache_size > max_size)
1040 				max_size = vac_cache_size;
1041 			if (vac_line_size < min_line_size)
1042 				min_line_size = vac_line_size;
1043 			//FIXME: cpus not contiguous!!
1044 			cpu++;
1045 			if (cpu >= nr_cpu_ids || !cpu_online(cpu))
1046 				break;
1047 #else
1048 			break;
1049 #endif
1050 		}
1051 	}
1052 	if (nd == 0) {
1053 		prom_printf("No CPU nodes found, halting.\n");
1054 		prom_halt();
1055 	}
1056 #ifdef CONFIG_SMP
1057 	vac_cache_size = max_size;
1058 	vac_line_size = min_line_size;
1059 #endif
1060 	printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1061 	       (int)vac_cache_size, (int)vac_line_size);
1062 }
1063 
poke_hypersparc(void)1064 static void poke_hypersparc(void)
1065 {
1066 	volatile unsigned long clear;
1067 	unsigned long mreg = srmmu_get_mmureg();
1068 
1069 	hyper_flush_unconditional_combined();
1070 
1071 	mreg &= ~(HYPERSPARC_CWENABLE);
1072 	mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1073 	mreg |= (HYPERSPARC_CMODE);
1074 
1075 	srmmu_set_mmureg(mreg);
1076 
1077 #if 0 /* XXX I think this is bad news... -DaveM */
1078 	hyper_clear_all_tags();
1079 #endif
1080 
1081 	put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1082 	hyper_flush_whole_icache();
1083 	clear = srmmu_get_faddr();
1084 	clear = srmmu_get_fstatus();
1085 }
1086 
1087 static const struct sparc32_cachetlb_ops hypersparc_ops = {
1088 	.cache_all	= hypersparc_flush_cache_all,
1089 	.cache_mm	= hypersparc_flush_cache_mm,
1090 	.cache_page	= hypersparc_flush_cache_page,
1091 	.cache_range	= hypersparc_flush_cache_range,
1092 	.tlb_all	= hypersparc_flush_tlb_all,
1093 	.tlb_mm		= hypersparc_flush_tlb_mm,
1094 	.tlb_page	= hypersparc_flush_tlb_page,
1095 	.tlb_range	= hypersparc_flush_tlb_range,
1096 	.page_to_ram	= hypersparc_flush_page_to_ram,
1097 	.sig_insns	= hypersparc_flush_sig_insns,
1098 	.page_for_dma	= hypersparc_flush_page_for_dma,
1099 };
1100 
init_hypersparc(void)1101 static void __init init_hypersparc(void)
1102 {
1103 	srmmu_name = "ROSS HyperSparc";
1104 	srmmu_modtype = HyperSparc;
1105 
1106 	init_vac_layout();
1107 
1108 	is_hypersparc = 1;
1109 	sparc32_cachetlb_ops = &hypersparc_ops;
1110 
1111 	poke_srmmu = poke_hypersparc;
1112 
1113 	hypersparc_setup_blockops();
1114 }
1115 
poke_swift(void)1116 static void poke_swift(void)
1117 {
1118 	unsigned long mreg;
1119 
1120 	/* Clear any crap from the cache or else... */
1121 	swift_flush_cache_all();
1122 
1123 	/* Enable I & D caches */
1124 	mreg = srmmu_get_mmureg();
1125 	mreg |= (SWIFT_IE | SWIFT_DE);
1126 	/*
1127 	 * The Swift branch folding logic is completely broken.  At
1128 	 * trap time, if things are just right, if can mistakenly
1129 	 * think that a trap is coming from kernel mode when in fact
1130 	 * it is coming from user mode (it mis-executes the branch in
1131 	 * the trap code).  So you see things like crashme completely
1132 	 * hosing your machine which is completely unacceptable.  Turn
1133 	 * this shit off... nice job Fujitsu.
1134 	 */
1135 	mreg &= ~(SWIFT_BF);
1136 	srmmu_set_mmureg(mreg);
1137 }
1138 
1139 static const struct sparc32_cachetlb_ops swift_ops = {
1140 	.cache_all	= swift_flush_cache_all,
1141 	.cache_mm	= swift_flush_cache_mm,
1142 	.cache_page	= swift_flush_cache_page,
1143 	.cache_range	= swift_flush_cache_range,
1144 	.tlb_all	= swift_flush_tlb_all,
1145 	.tlb_mm		= swift_flush_tlb_mm,
1146 	.tlb_page	= swift_flush_tlb_page,
1147 	.tlb_range	= swift_flush_tlb_range,
1148 	.page_to_ram	= swift_flush_page_to_ram,
1149 	.sig_insns	= swift_flush_sig_insns,
1150 	.page_for_dma	= swift_flush_page_for_dma,
1151 };
1152 
1153 #define SWIFT_MASKID_ADDR  0x10003018
init_swift(void)1154 static void __init init_swift(void)
1155 {
1156 	unsigned long swift_rev;
1157 
1158 	__asm__ __volatile__("lda [%1] %2, %0\n\t"
1159 			     "srl %0, 0x18, %0\n\t" :
1160 			     "=r" (swift_rev) :
1161 			     "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1162 	srmmu_name = "Fujitsu Swift";
1163 	switch (swift_rev) {
1164 	case 0x11:
1165 	case 0x20:
1166 	case 0x23:
1167 	case 0x30:
1168 		srmmu_modtype = Swift_lots_o_bugs;
1169 		hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1170 		/*
1171 		 * Gee george, I wonder why Sun is so hush hush about
1172 		 * this hardware bug... really braindamage stuff going
1173 		 * on here.  However I think we can find a way to avoid
1174 		 * all of the workaround overhead under Linux.  Basically,
1175 		 * any page fault can cause kernel pages to become user
1176 		 * accessible (the mmu gets confused and clears some of
1177 		 * the ACC bits in kernel ptes).  Aha, sounds pretty
1178 		 * horrible eh?  But wait, after extensive testing it appears
1179 		 * that if you use pgd_t level large kernel pte's (like the
1180 		 * 4MB pages on the Pentium) the bug does not get tripped
1181 		 * at all.  This avoids almost all of the major overhead.
1182 		 * Welcome to a world where your vendor tells you to,
1183 		 * "apply this kernel patch" instead of "sorry for the
1184 		 * broken hardware, send it back and we'll give you
1185 		 * properly functioning parts"
1186 		 */
1187 		break;
1188 	case 0x25:
1189 	case 0x31:
1190 		srmmu_modtype = Swift_bad_c;
1191 		hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1192 		/*
1193 		 * You see Sun allude to this hardware bug but never
1194 		 * admit things directly, they'll say things like,
1195 		 * "the Swift chip cache problems" or similar.
1196 		 */
1197 		break;
1198 	default:
1199 		srmmu_modtype = Swift_ok;
1200 		break;
1201 	}
1202 
1203 	sparc32_cachetlb_ops = &swift_ops;
1204 	flush_page_for_dma_global = 0;
1205 
1206 	/*
1207 	 * Are you now convinced that the Swift is one of the
1208 	 * biggest VLSI abortions of all time?  Bravo Fujitsu!
1209 	 * Fujitsu, the !#?!%$'d up processor people.  I bet if
1210 	 * you examined the microcode of the Swift you'd find
1211 	 * XXX's all over the place.
1212 	 */
1213 	poke_srmmu = poke_swift;
1214 }
1215 
turbosparc_flush_cache_all(void)1216 static void turbosparc_flush_cache_all(void)
1217 {
1218 	flush_user_windows();
1219 	turbosparc_idflash_clear();
1220 }
1221 
turbosparc_flush_cache_mm(struct mm_struct * mm)1222 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1223 {
1224 	FLUSH_BEGIN(mm)
1225 	flush_user_windows();
1226 	turbosparc_idflash_clear();
1227 	FLUSH_END
1228 }
1229 
turbosparc_flush_cache_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)1230 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1231 {
1232 	FLUSH_BEGIN(vma->vm_mm)
1233 	flush_user_windows();
1234 	turbosparc_idflash_clear();
1235 	FLUSH_END
1236 }
1237 
turbosparc_flush_cache_page(struct vm_area_struct * vma,unsigned long page)1238 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1239 {
1240 	FLUSH_BEGIN(vma->vm_mm)
1241 	flush_user_windows();
1242 	if (vma->vm_flags & VM_EXEC)
1243 		turbosparc_flush_icache();
1244 	turbosparc_flush_dcache();
1245 	FLUSH_END
1246 }
1247 
1248 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
turbosparc_flush_page_to_ram(unsigned long page)1249 static void turbosparc_flush_page_to_ram(unsigned long page)
1250 {
1251 #ifdef TURBOSPARC_WRITEBACK
1252 	volatile unsigned long clear;
1253 
1254 	if (srmmu_probe(page))
1255 		turbosparc_flush_page_cache(page);
1256 	clear = srmmu_get_fstatus();
1257 #endif
1258 }
1259 
turbosparc_flush_sig_insns(struct mm_struct * mm,unsigned long insn_addr)1260 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1261 {
1262 }
1263 
turbosparc_flush_page_for_dma(unsigned long page)1264 static void turbosparc_flush_page_for_dma(unsigned long page)
1265 {
1266 	turbosparc_flush_dcache();
1267 }
1268 
turbosparc_flush_tlb_all(void)1269 static void turbosparc_flush_tlb_all(void)
1270 {
1271 	srmmu_flush_whole_tlb();
1272 }
1273 
turbosparc_flush_tlb_mm(struct mm_struct * mm)1274 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1275 {
1276 	FLUSH_BEGIN(mm)
1277 	srmmu_flush_whole_tlb();
1278 	FLUSH_END
1279 }
1280 
turbosparc_flush_tlb_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)1281 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1282 {
1283 	FLUSH_BEGIN(vma->vm_mm)
1284 	srmmu_flush_whole_tlb();
1285 	FLUSH_END
1286 }
1287 
turbosparc_flush_tlb_page(struct vm_area_struct * vma,unsigned long page)1288 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1289 {
1290 	FLUSH_BEGIN(vma->vm_mm)
1291 	srmmu_flush_whole_tlb();
1292 	FLUSH_END
1293 }
1294 
1295 
poke_turbosparc(void)1296 static void poke_turbosparc(void)
1297 {
1298 	unsigned long mreg = srmmu_get_mmureg();
1299 	unsigned long ccreg;
1300 
1301 	/* Clear any crap from the cache or else... */
1302 	turbosparc_flush_cache_all();
1303 	/* Temporarily disable I & D caches */
1304 	mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE);
1305 	mreg &= ~(TURBOSPARC_PCENABLE);		/* Don't check parity */
1306 	srmmu_set_mmureg(mreg);
1307 
1308 	ccreg = turbosparc_get_ccreg();
1309 
1310 #ifdef TURBOSPARC_WRITEBACK
1311 	ccreg |= (TURBOSPARC_SNENABLE);		/* Do DVMA snooping in Dcache */
1312 	ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1313 			/* Write-back D-cache, emulate VLSI
1314 			 * abortion number three, not number one */
1315 #else
1316 	/* For now let's play safe, optimize later */
1317 	ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1318 			/* Do DVMA snooping in Dcache, Write-thru D-cache */
1319 	ccreg &= ~(TURBOSPARC_uS2);
1320 			/* Emulate VLSI abortion number three, not number one */
1321 #endif
1322 
1323 	switch (ccreg & 7) {
1324 	case 0: /* No SE cache */
1325 	case 7: /* Test mode */
1326 		break;
1327 	default:
1328 		ccreg |= (TURBOSPARC_SCENABLE);
1329 	}
1330 	turbosparc_set_ccreg(ccreg);
1331 
1332 	mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1333 	mreg |= (TURBOSPARC_ICSNOOP);		/* Icache snooping on */
1334 	srmmu_set_mmureg(mreg);
1335 }
1336 
1337 static const struct sparc32_cachetlb_ops turbosparc_ops = {
1338 	.cache_all	= turbosparc_flush_cache_all,
1339 	.cache_mm	= turbosparc_flush_cache_mm,
1340 	.cache_page	= turbosparc_flush_cache_page,
1341 	.cache_range	= turbosparc_flush_cache_range,
1342 	.tlb_all	= turbosparc_flush_tlb_all,
1343 	.tlb_mm		= turbosparc_flush_tlb_mm,
1344 	.tlb_page	= turbosparc_flush_tlb_page,
1345 	.tlb_range	= turbosparc_flush_tlb_range,
1346 	.page_to_ram	= turbosparc_flush_page_to_ram,
1347 	.sig_insns	= turbosparc_flush_sig_insns,
1348 	.page_for_dma	= turbosparc_flush_page_for_dma,
1349 };
1350 
init_turbosparc(void)1351 static void __init init_turbosparc(void)
1352 {
1353 	srmmu_name = "Fujitsu TurboSparc";
1354 	srmmu_modtype = TurboSparc;
1355 	sparc32_cachetlb_ops = &turbosparc_ops;
1356 	poke_srmmu = poke_turbosparc;
1357 }
1358 
poke_tsunami(void)1359 static void poke_tsunami(void)
1360 {
1361 	unsigned long mreg = srmmu_get_mmureg();
1362 
1363 	tsunami_flush_icache();
1364 	tsunami_flush_dcache();
1365 	mreg &= ~TSUNAMI_ITD;
1366 	mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1367 	srmmu_set_mmureg(mreg);
1368 }
1369 
1370 static const struct sparc32_cachetlb_ops tsunami_ops = {
1371 	.cache_all	= tsunami_flush_cache_all,
1372 	.cache_mm	= tsunami_flush_cache_mm,
1373 	.cache_page	= tsunami_flush_cache_page,
1374 	.cache_range	= tsunami_flush_cache_range,
1375 	.tlb_all	= tsunami_flush_tlb_all,
1376 	.tlb_mm		= tsunami_flush_tlb_mm,
1377 	.tlb_page	= tsunami_flush_tlb_page,
1378 	.tlb_range	= tsunami_flush_tlb_range,
1379 	.page_to_ram	= tsunami_flush_page_to_ram,
1380 	.sig_insns	= tsunami_flush_sig_insns,
1381 	.page_for_dma	= tsunami_flush_page_for_dma,
1382 };
1383 
init_tsunami(void)1384 static void __init init_tsunami(void)
1385 {
1386 	/*
1387 	 * Tsunami's pretty sane, Sun and TI actually got it
1388 	 * somewhat right this time.  Fujitsu should have
1389 	 * taken some lessons from them.
1390 	 */
1391 
1392 	srmmu_name = "TI Tsunami";
1393 	srmmu_modtype = Tsunami;
1394 	sparc32_cachetlb_ops = &tsunami_ops;
1395 	poke_srmmu = poke_tsunami;
1396 
1397 	tsunami_setup_blockops();
1398 }
1399 
poke_viking(void)1400 static void poke_viking(void)
1401 {
1402 	unsigned long mreg = srmmu_get_mmureg();
1403 	static int smp_catch;
1404 
1405 	if (viking_mxcc_present) {
1406 		unsigned long mxcc_control = mxcc_get_creg();
1407 
1408 		mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1409 		mxcc_control &= ~(MXCC_CTL_RRC);
1410 		mxcc_set_creg(mxcc_control);
1411 
1412 		/*
1413 		 * We don't need memory parity checks.
1414 		 * XXX This is a mess, have to dig out later. ecd.
1415 		viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1416 		 */
1417 
1418 		/* We do cache ptables on MXCC. */
1419 		mreg |= VIKING_TCENABLE;
1420 	} else {
1421 		unsigned long bpreg;
1422 
1423 		mreg &= ~(VIKING_TCENABLE);
1424 		if (smp_catch++) {
1425 			/* Must disable mixed-cmd mode here for other cpu's. */
1426 			bpreg = viking_get_bpreg();
1427 			bpreg &= ~(VIKING_ACTION_MIX);
1428 			viking_set_bpreg(bpreg);
1429 
1430 			/* Just in case PROM does something funny. */
1431 			msi_set_sync();
1432 		}
1433 	}
1434 
1435 	mreg |= VIKING_SPENABLE;
1436 	mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1437 	mreg |= VIKING_SBENABLE;
1438 	mreg &= ~(VIKING_ACENABLE);
1439 	srmmu_set_mmureg(mreg);
1440 }
1441 
1442 static struct sparc32_cachetlb_ops viking_ops = {
1443 	.cache_all	= viking_flush_cache_all,
1444 	.cache_mm	= viking_flush_cache_mm,
1445 	.cache_page	= viking_flush_cache_page,
1446 	.cache_range	= viking_flush_cache_range,
1447 	.tlb_all	= viking_flush_tlb_all,
1448 	.tlb_mm		= viking_flush_tlb_mm,
1449 	.tlb_page	= viking_flush_tlb_page,
1450 	.tlb_range	= viking_flush_tlb_range,
1451 	.page_to_ram	= viking_flush_page_to_ram,
1452 	.sig_insns	= viking_flush_sig_insns,
1453 	.page_for_dma	= viking_flush_page_for_dma,
1454 };
1455 
1456 #ifdef CONFIG_SMP
1457 /* On sun4d the cpu broadcasts local TLB flushes, so we can just
1458  * perform the local TLB flush and all the other cpus will see it.
1459  * But, unfortunately, there is a bug in the sun4d XBUS backplane
1460  * that requires that we add some synchronization to these flushes.
1461  *
1462  * The bug is that the fifo which keeps track of all the pending TLB
1463  * broadcasts in the system is an entry or two too small, so if we
1464  * have too many going at once we'll overflow that fifo and lose a TLB
1465  * flush resulting in corruption.
1466  *
1467  * Our workaround is to take a global spinlock around the TLB flushes,
1468  * which guarentees we won't ever have too many pending.  It's a big
1469  * hammer, but a semaphore like system to make sure we only have N TLB
1470  * flushes going at once will require SMP locking anyways so there's
1471  * no real value in trying any harder than this.
1472  */
1473 static struct sparc32_cachetlb_ops viking_sun4d_smp_ops = {
1474 	.cache_all	= viking_flush_cache_all,
1475 	.cache_mm	= viking_flush_cache_mm,
1476 	.cache_page	= viking_flush_cache_page,
1477 	.cache_range	= viking_flush_cache_range,
1478 	.tlb_all	= sun4dsmp_flush_tlb_all,
1479 	.tlb_mm		= sun4dsmp_flush_tlb_mm,
1480 	.tlb_page	= sun4dsmp_flush_tlb_page,
1481 	.tlb_range	= sun4dsmp_flush_tlb_range,
1482 	.page_to_ram	= viking_flush_page_to_ram,
1483 	.sig_insns	= viking_flush_sig_insns,
1484 	.page_for_dma	= viking_flush_page_for_dma,
1485 };
1486 #endif
1487 
init_viking(void)1488 static void __init init_viking(void)
1489 {
1490 	unsigned long mreg = srmmu_get_mmureg();
1491 
1492 	/* Ahhh, the viking.  SRMMU VLSI abortion number two... */
1493 	if (mreg & VIKING_MMODE) {
1494 		srmmu_name = "TI Viking";
1495 		viking_mxcc_present = 0;
1496 		msi_set_sync();
1497 
1498 		/*
1499 		 * We need this to make sure old viking takes no hits
1500 		 * on it's cache for dma snoops to workaround the
1501 		 * "load from non-cacheable memory" interrupt bug.
1502 		 * This is only necessary because of the new way in
1503 		 * which we use the IOMMU.
1504 		 */
1505 		viking_ops.page_for_dma = viking_flush_page;
1506 #ifdef CONFIG_SMP
1507 		viking_sun4d_smp_ops.page_for_dma = viking_flush_page;
1508 #endif
1509 		flush_page_for_dma_global = 0;
1510 	} else {
1511 		srmmu_name = "TI Viking/MXCC";
1512 		viking_mxcc_present = 1;
1513 		srmmu_cache_pagetables = 1;
1514 	}
1515 
1516 	sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1517 		&viking_ops;
1518 #ifdef CONFIG_SMP
1519 	if (sparc_cpu_model == sun4d)
1520 		sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1521 			&viking_sun4d_smp_ops;
1522 #endif
1523 
1524 	poke_srmmu = poke_viking;
1525 }
1526 
1527 /* Probe for the srmmu chip version. */
get_srmmu_type(void)1528 static void __init get_srmmu_type(void)
1529 {
1530 	unsigned long mreg, psr;
1531 	unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1532 
1533 	srmmu_modtype = SRMMU_INVAL_MOD;
1534 	hwbug_bitmask = 0;
1535 
1536 	mreg = srmmu_get_mmureg(); psr = get_psr();
1537 	mod_typ = (mreg & 0xf0000000) >> 28;
1538 	mod_rev = (mreg & 0x0f000000) >> 24;
1539 	psr_typ = (psr >> 28) & 0xf;
1540 	psr_vers = (psr >> 24) & 0xf;
1541 
1542 	/* First, check for sparc-leon. */
1543 	if (sparc_cpu_model == sparc_leon) {
1544 		init_leon();
1545 		return;
1546 	}
1547 
1548 	/* Second, check for HyperSparc or Cypress. */
1549 	if (mod_typ == 1) {
1550 		switch (mod_rev) {
1551 		case 7:
1552 			/* UP or MP Hypersparc */
1553 			init_hypersparc();
1554 			break;
1555 		case 0:
1556 		case 2:
1557 		case 10:
1558 		case 11:
1559 		case 12:
1560 		case 13:
1561 		case 14:
1562 		case 15:
1563 		default:
1564 			prom_printf("Sparc-Linux Cypress support does not longer exit.\n");
1565 			prom_halt();
1566 			break;
1567 		}
1568 		return;
1569 	}
1570 
1571 	/* Now Fujitsu TurboSparc. It might happen that it is
1572 	 * in Swift emulation mode, so we will check later...
1573 	 */
1574 	if (psr_typ == 0 && psr_vers == 5) {
1575 		init_turbosparc();
1576 		return;
1577 	}
1578 
1579 	/* Next check for Fujitsu Swift. */
1580 	if (psr_typ == 0 && psr_vers == 4) {
1581 		phandle cpunode;
1582 		char node_str[128];
1583 
1584 		/* Look if it is not a TurboSparc emulating Swift... */
1585 		cpunode = prom_getchild(prom_root_node);
1586 		while ((cpunode = prom_getsibling(cpunode)) != 0) {
1587 			prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1588 			if (!strcmp(node_str, "cpu")) {
1589 				if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
1590 				    prom_getintdefault(cpunode, "psr-version", 1) == 5) {
1591 					init_turbosparc();
1592 					return;
1593 				}
1594 				break;
1595 			}
1596 		}
1597 
1598 		init_swift();
1599 		return;
1600 	}
1601 
1602 	/* Now the Viking family of srmmu. */
1603 	if (psr_typ == 4 &&
1604 	   ((psr_vers == 0) ||
1605 	    ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
1606 		init_viking();
1607 		return;
1608 	}
1609 
1610 	/* Finally the Tsunami. */
1611 	if (psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
1612 		init_tsunami();
1613 		return;
1614 	}
1615 
1616 	/* Oh well */
1617 	srmmu_is_bad();
1618 }
1619 
1620 #ifdef CONFIG_SMP
1621 /* Local cross-calls. */
smp_flush_page_for_dma(unsigned long page)1622 static void smp_flush_page_for_dma(unsigned long page)
1623 {
1624 	xc1((smpfunc_t) local_ops->page_for_dma, page);
1625 	local_ops->page_for_dma(page);
1626 }
1627 
smp_flush_cache_all(void)1628 static void smp_flush_cache_all(void)
1629 {
1630 	xc0((smpfunc_t) local_ops->cache_all);
1631 	local_ops->cache_all();
1632 }
1633 
smp_flush_tlb_all(void)1634 static void smp_flush_tlb_all(void)
1635 {
1636 	xc0((smpfunc_t) local_ops->tlb_all);
1637 	local_ops->tlb_all();
1638 }
1639 
smp_flush_cache_mm(struct mm_struct * mm)1640 static void smp_flush_cache_mm(struct mm_struct *mm)
1641 {
1642 	if (mm->context != NO_CONTEXT) {
1643 		cpumask_t cpu_mask;
1644 		cpumask_copy(&cpu_mask, mm_cpumask(mm));
1645 		cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1646 		if (!cpumask_empty(&cpu_mask))
1647 			xc1((smpfunc_t) local_ops->cache_mm, (unsigned long) mm);
1648 		local_ops->cache_mm(mm);
1649 	}
1650 }
1651 
smp_flush_tlb_mm(struct mm_struct * mm)1652 static void smp_flush_tlb_mm(struct mm_struct *mm)
1653 {
1654 	if (mm->context != NO_CONTEXT) {
1655 		cpumask_t cpu_mask;
1656 		cpumask_copy(&cpu_mask, mm_cpumask(mm));
1657 		cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1658 		if (!cpumask_empty(&cpu_mask)) {
1659 			xc1((smpfunc_t) local_ops->tlb_mm, (unsigned long) mm);
1660 			if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm)
1661 				cpumask_copy(mm_cpumask(mm),
1662 					     cpumask_of(smp_processor_id()));
1663 		}
1664 		local_ops->tlb_mm(mm);
1665 	}
1666 }
1667 
smp_flush_cache_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)1668 static void smp_flush_cache_range(struct vm_area_struct *vma,
1669 				  unsigned long start,
1670 				  unsigned long end)
1671 {
1672 	struct mm_struct *mm = vma->vm_mm;
1673 
1674 	if (mm->context != NO_CONTEXT) {
1675 		cpumask_t cpu_mask;
1676 		cpumask_copy(&cpu_mask, mm_cpumask(mm));
1677 		cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1678 		if (!cpumask_empty(&cpu_mask))
1679 			xc3((smpfunc_t) local_ops->cache_range,
1680 			    (unsigned long) vma, start, end);
1681 		local_ops->cache_range(vma, start, end);
1682 	}
1683 }
1684 
smp_flush_tlb_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)1685 static void smp_flush_tlb_range(struct vm_area_struct *vma,
1686 				unsigned long start,
1687 				unsigned long end)
1688 {
1689 	struct mm_struct *mm = vma->vm_mm;
1690 
1691 	if (mm->context != NO_CONTEXT) {
1692 		cpumask_t cpu_mask;
1693 		cpumask_copy(&cpu_mask, mm_cpumask(mm));
1694 		cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1695 		if (!cpumask_empty(&cpu_mask))
1696 			xc3((smpfunc_t) local_ops->tlb_range,
1697 			    (unsigned long) vma, start, end);
1698 		local_ops->tlb_range(vma, start, end);
1699 	}
1700 }
1701 
smp_flush_cache_page(struct vm_area_struct * vma,unsigned long page)1702 static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1703 {
1704 	struct mm_struct *mm = vma->vm_mm;
1705 
1706 	if (mm->context != NO_CONTEXT) {
1707 		cpumask_t cpu_mask;
1708 		cpumask_copy(&cpu_mask, mm_cpumask(mm));
1709 		cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1710 		if (!cpumask_empty(&cpu_mask))
1711 			xc2((smpfunc_t) local_ops->cache_page,
1712 			    (unsigned long) vma, page);
1713 		local_ops->cache_page(vma, page);
1714 	}
1715 }
1716 
smp_flush_tlb_page(struct vm_area_struct * vma,unsigned long page)1717 static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1718 {
1719 	struct mm_struct *mm = vma->vm_mm;
1720 
1721 	if (mm->context != NO_CONTEXT) {
1722 		cpumask_t cpu_mask;
1723 		cpumask_copy(&cpu_mask, mm_cpumask(mm));
1724 		cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1725 		if (!cpumask_empty(&cpu_mask))
1726 			xc2((smpfunc_t) local_ops->tlb_page,
1727 			    (unsigned long) vma, page);
1728 		local_ops->tlb_page(vma, page);
1729 	}
1730 }
1731 
smp_flush_page_to_ram(unsigned long page)1732 static void smp_flush_page_to_ram(unsigned long page)
1733 {
1734 	/* Current theory is that those who call this are the one's
1735 	 * who have just dirtied their cache with the pages contents
1736 	 * in kernel space, therefore we only run this on local cpu.
1737 	 *
1738 	 * XXX This experiment failed, research further... -DaveM
1739 	 */
1740 #if 1
1741 	xc1((smpfunc_t) local_ops->page_to_ram, page);
1742 #endif
1743 	local_ops->page_to_ram(page);
1744 }
1745 
smp_flush_sig_insns(struct mm_struct * mm,unsigned long insn_addr)1746 static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1747 {
1748 	cpumask_t cpu_mask;
1749 	cpumask_copy(&cpu_mask, mm_cpumask(mm));
1750 	cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1751 	if (!cpumask_empty(&cpu_mask))
1752 		xc2((smpfunc_t) local_ops->sig_insns,
1753 		    (unsigned long) mm, insn_addr);
1754 	local_ops->sig_insns(mm, insn_addr);
1755 }
1756 
1757 static struct sparc32_cachetlb_ops smp_cachetlb_ops = {
1758 	.cache_all	= smp_flush_cache_all,
1759 	.cache_mm	= smp_flush_cache_mm,
1760 	.cache_page	= smp_flush_cache_page,
1761 	.cache_range	= smp_flush_cache_range,
1762 	.tlb_all	= smp_flush_tlb_all,
1763 	.tlb_mm		= smp_flush_tlb_mm,
1764 	.tlb_page	= smp_flush_tlb_page,
1765 	.tlb_range	= smp_flush_tlb_range,
1766 	.page_to_ram	= smp_flush_page_to_ram,
1767 	.sig_insns	= smp_flush_sig_insns,
1768 	.page_for_dma	= smp_flush_page_for_dma,
1769 };
1770 #endif
1771 
1772 /* Load up routines and constants for sun4m and sun4d mmu */
load_mmu(void)1773 void __init load_mmu(void)
1774 {
1775 	/* Functions */
1776 	get_srmmu_type();
1777 
1778 #ifdef CONFIG_SMP
1779 	/* El switcheroo... */
1780 	local_ops = sparc32_cachetlb_ops;
1781 
1782 	if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) {
1783 		smp_cachetlb_ops.tlb_all = local_ops->tlb_all;
1784 		smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm;
1785 		smp_cachetlb_ops.tlb_range = local_ops->tlb_range;
1786 		smp_cachetlb_ops.tlb_page = local_ops->tlb_page;
1787 	}
1788 
1789 	if (poke_srmmu == poke_viking) {
1790 		/* Avoid unnecessary cross calls. */
1791 		smp_cachetlb_ops.cache_all = local_ops->cache_all;
1792 		smp_cachetlb_ops.cache_mm = local_ops->cache_mm;
1793 		smp_cachetlb_ops.cache_range = local_ops->cache_range;
1794 		smp_cachetlb_ops.cache_page = local_ops->cache_page;
1795 
1796 		smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram;
1797 		smp_cachetlb_ops.sig_insns = local_ops->sig_insns;
1798 		smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma;
1799 	}
1800 
1801 	/* It really is const after this point. */
1802 	sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1803 		&smp_cachetlb_ops;
1804 #endif
1805 
1806 	if (sparc_cpu_model == sun4d)
1807 		ld_mmu_iounit();
1808 	else
1809 		ld_mmu_iommu();
1810 #ifdef CONFIG_SMP
1811 	if (sparc_cpu_model == sun4d)
1812 		sun4d_init_smp();
1813 	else if (sparc_cpu_model == sparc_leon)
1814 		leon_init_smp();
1815 	else
1816 		sun4m_init_smp();
1817 #endif
1818 }
1819