1 /*
2 * linux/arch/alpha/kernel/core_titan.c
3 *
4 * Code common to all TITAN core logic chips.
5 */
6
7 #define __EXTERN_INLINE inline
8 #include <asm/io.h>
9 #include <asm/core_titan.h>
10 #undef __EXTERN_INLINE
11
12 #include <linux/module.h>
13 #include <linux/types.h>
14 #include <linux/pci.h>
15 #include <linux/sched.h>
16 #include <linux/init.h>
17 #include <linux/vmalloc.h>
18 #include <linux/bootmem.h>
19
20 #include <asm/ptrace.h>
21 #include <asm/smp.h>
22 #include <asm/pgalloc.h>
23 #include <asm/tlbflush.h>
24 #include <asm/vga.h>
25
26 #include "proto.h"
27 #include "pci_impl.h"
28
29 /* Save Titan configuration data as the console had it set up. */
30
31 struct
32 {
33 unsigned long wsba[4];
34 unsigned long wsm[4];
35 unsigned long tba[4];
36 } saved_config[4] __attribute__((common));
37
38 /*
39 * Is PChip 1 present? No need to query it more than once.
40 */
41 static int titan_pchip1_present;
42
43 /*
44 * BIOS32-style PCI interface:
45 */
46
47 #define DEBUG_CONFIG 0
48
49 #if DEBUG_CONFIG
50 # define DBG_CFG(args) printk args
51 #else
52 # define DBG_CFG(args)
53 #endif
54
55
56 /*
57 * Routines to access TIG registers.
58 */
59 static inline volatile unsigned long *
mk_tig_addr(int offset)60 mk_tig_addr(int offset)
61 {
62 return (volatile unsigned long *)(TITAN_TIG_SPACE + (offset << 6));
63 }
64
65 static inline u8
titan_read_tig(int offset,u8 value)66 titan_read_tig(int offset, u8 value)
67 {
68 volatile unsigned long *tig_addr = mk_tig_addr(offset);
69 return (u8)(*tig_addr & 0xff);
70 }
71
72 static inline void
titan_write_tig(int offset,u8 value)73 titan_write_tig(int offset, u8 value)
74 {
75 volatile unsigned long *tig_addr = mk_tig_addr(offset);
76 *tig_addr = (unsigned long)value;
77 }
78
79
80 /*
81 * Given a bus, device, and function number, compute resulting
82 * configuration space address
83 * accordingly. It is therefore not safe to have concurrent
84 * invocations to configuration space access routines, but there
85 * really shouldn't be any need for this.
86 *
87 * Note that all config space accesses use Type 1 address format.
88 *
89 * Note also that type 1 is determined by non-zero bus number.
90 *
91 * Type 1:
92 *
93 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
94 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
95 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
96 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
97 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
98 *
99 * 31:24 reserved
100 * 23:16 bus number (8 bits = 128 possible buses)
101 * 15:11 Device number (5 bits)
102 * 10:8 function number
103 * 7:2 register number
104 *
105 * Notes:
106 * The function number selects which function of a multi-function device
107 * (e.g., SCSI and Ethernet).
108 *
109 * The register selects a DWORD (32 bit) register offset. Hence it
110 * doesn't get shifted by 2 bits as we want to "drop" the bottom two
111 * bits.
112 */
113
114 static int
mk_conf_addr(struct pci_bus * pbus,unsigned int device_fn,int where,unsigned long * pci_addr,unsigned char * type1)115 mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
116 unsigned long *pci_addr, unsigned char *type1)
117 {
118 struct pci_controller *hose = pbus->sysdata;
119 unsigned long addr;
120 u8 bus = pbus->number;
121
122 DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, "
123 "pci_addr=0x%p, type1=0x%p)\n",
124 bus, device_fn, where, pci_addr, type1));
125
126 if (!pbus->parent) /* No parent means peer PCI bus. */
127 bus = 0;
128 *type1 = (bus != 0);
129
130 addr = (bus << 16) | (device_fn << 8) | where;
131 addr |= hose->config_space_base;
132
133 *pci_addr = addr;
134 DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
135 return 0;
136 }
137
138 static int
titan_read_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * value)139 titan_read_config(struct pci_bus *bus, unsigned int devfn, int where,
140 int size, u32 *value)
141 {
142 unsigned long addr;
143 unsigned char type1;
144
145 if (mk_conf_addr(bus, devfn, where, &addr, &type1))
146 return PCIBIOS_DEVICE_NOT_FOUND;
147
148 switch (size) {
149 case 1:
150 *value = __kernel_ldbu(*(vucp)addr);
151 break;
152 case 2:
153 *value = __kernel_ldwu(*(vusp)addr);
154 break;
155 case 4:
156 *value = *(vuip)addr;
157 break;
158 }
159
160 return PCIBIOS_SUCCESSFUL;
161 }
162
163 static int
titan_write_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 value)164 titan_write_config(struct pci_bus *bus, unsigned int devfn, int where,
165 int size, u32 value)
166 {
167 unsigned long addr;
168 unsigned char type1;
169
170 if (mk_conf_addr(bus, devfn, where, &addr, &type1))
171 return PCIBIOS_DEVICE_NOT_FOUND;
172
173 switch (size) {
174 case 1:
175 __kernel_stb(value, *(vucp)addr);
176 mb();
177 __kernel_ldbu(*(vucp)addr);
178 break;
179 case 2:
180 __kernel_stw(value, *(vusp)addr);
181 mb();
182 __kernel_ldwu(*(vusp)addr);
183 break;
184 case 4:
185 *(vuip)addr = value;
186 mb();
187 *(vuip)addr;
188 break;
189 }
190
191 return PCIBIOS_SUCCESSFUL;
192 }
193
194 struct pci_ops titan_pci_ops =
195 {
196 .read = titan_read_config,
197 .write = titan_write_config,
198 };
199
200
201 void
titan_pci_tbi(struct pci_controller * hose,dma_addr_t start,dma_addr_t end)202 titan_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
203 {
204 titan_pachip *pachip =
205 (hose->index & 1) ? TITAN_pachip1 : TITAN_pachip0;
206 titan_pachip_port *port;
207 volatile unsigned long *csr;
208 unsigned long value;
209
210 /* Get the right hose. */
211 port = &pachip->g_port;
212 if (hose->index & 2)
213 port = &pachip->a_port;
214
215 /* We can invalidate up to 8 tlb entries in a go. The flush
216 matches against <31:16> in the pci address.
217 Note that gtlbi* and atlbi* are in the same place in the g_port
218 and a_port, respectively, so the g_port offset can be used
219 even if hose is an a_port */
220 csr = &port->port_specific.g.gtlbia.csr;
221 if (((start ^ end) & 0xffff0000) == 0)
222 csr = &port->port_specific.g.gtlbiv.csr;
223
224 /* For TBIA, it doesn't matter what value we write. For TBI,
225 it's the shifted tag bits. */
226 value = (start & 0xffff0000) >> 12;
227
228 wmb();
229 *csr = value;
230 mb();
231 *csr;
232 }
233
234 static int
titan_query_agp(titan_pachip_port * port)235 titan_query_agp(titan_pachip_port *port)
236 {
237 union TPAchipPCTL pctl;
238
239 /* set up APCTL */
240 pctl.pctl_q_whole = port->pctl.csr;
241
242 return pctl.pctl_r_bits.apctl_v_agp_present;
243
244 }
245
246 static void __init
titan_init_one_pachip_port(titan_pachip_port * port,int index)247 titan_init_one_pachip_port(titan_pachip_port *port, int index)
248 {
249 struct pci_controller *hose;
250
251 hose = alloc_pci_controller();
252 if (index == 0)
253 pci_isa_hose = hose;
254 hose->io_space = alloc_resource();
255 hose->mem_space = alloc_resource();
256
257 /*
258 * This is for userland consumption. The 40-bit PIO bias that we
259 * use in the kernel through KSEG doesn't work in the page table
260 * based user mappings. (43-bit KSEG sign extends the physical
261 * address from bit 40 to hit the I/O bit - mapped addresses don't).
262 * So make sure we get the 43-bit PIO bias.
263 */
264 hose->sparse_mem_base = 0;
265 hose->sparse_io_base = 0;
266 hose->dense_mem_base
267 = (TITAN_MEM(index) & 0xffffffffffUL) | 0x80000000000UL;
268 hose->dense_io_base
269 = (TITAN_IO(index) & 0xffffffffffUL) | 0x80000000000UL;
270
271 hose->config_space_base = TITAN_CONF(index);
272 hose->index = index;
273
274 hose->io_space->start = TITAN_IO(index) - TITAN_IO_BIAS;
275 hose->io_space->end = hose->io_space->start + TITAN_IO_SPACE - 1;
276 hose->io_space->name = pci_io_names[index];
277 hose->io_space->flags = IORESOURCE_IO;
278
279 hose->mem_space->start = TITAN_MEM(index) - TITAN_MEM_BIAS;
280 hose->mem_space->end = hose->mem_space->start + 0xffffffff;
281 hose->mem_space->name = pci_mem_names[index];
282 hose->mem_space->flags = IORESOURCE_MEM;
283
284 if (request_resource(&ioport_resource, hose->io_space) < 0)
285 printk(KERN_ERR "Failed to request IO on hose %d\n", index);
286 if (request_resource(&iomem_resource, hose->mem_space) < 0)
287 printk(KERN_ERR "Failed to request MEM on hose %d\n", index);
288
289 /*
290 * Save the existing PCI window translations. SRM will
291 * need them when we go to reboot.
292 */
293 saved_config[index].wsba[0] = port->wsba[0].csr;
294 saved_config[index].wsm[0] = port->wsm[0].csr;
295 saved_config[index].tba[0] = port->tba[0].csr;
296
297 saved_config[index].wsba[1] = port->wsba[1].csr;
298 saved_config[index].wsm[1] = port->wsm[1].csr;
299 saved_config[index].tba[1] = port->tba[1].csr;
300
301 saved_config[index].wsba[2] = port->wsba[2].csr;
302 saved_config[index].wsm[2] = port->wsm[2].csr;
303 saved_config[index].tba[2] = port->tba[2].csr;
304
305 saved_config[index].wsba[3] = port->wsba[3].csr;
306 saved_config[index].wsm[3] = port->wsm[3].csr;
307 saved_config[index].tba[3] = port->tba[3].csr;
308
309 /*
310 * Set up the PCI to main memory translation windows.
311 *
312 * Note: Window 3 on Titan is Scatter-Gather ONLY.
313 *
314 * Window 0 is scatter-gather 8MB at 8MB (for isa)
315 * Window 1 is direct access 1GB at 2GB
316 * Window 2 is scatter-gather 1GB at 3GB
317 */
318 hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0);
319 hose->sg_isa->align_entry = 8; /* 64KB for ISA */
320
321 hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x40000000, 0);
322 hose->sg_pci->align_entry = 4; /* Titan caches 4 PTEs at a time */
323
324 port->wsba[0].csr = hose->sg_isa->dma_base | 3;
325 port->wsm[0].csr = (hose->sg_isa->size - 1) & 0xfff00000;
326 port->tba[0].csr = virt_to_phys(hose->sg_isa->ptes);
327
328 port->wsba[1].csr = __direct_map_base | 1;
329 port->wsm[1].csr = (__direct_map_size - 1) & 0xfff00000;
330 port->tba[1].csr = 0;
331
332 port->wsba[2].csr = hose->sg_pci->dma_base | 3;
333 port->wsm[2].csr = (hose->sg_pci->size - 1) & 0xfff00000;
334 port->tba[2].csr = virt_to_phys(hose->sg_pci->ptes);
335
336 port->wsba[3].csr = 0;
337
338 /* Enable the Monster Window to make DAC pci64 possible. */
339 port->pctl.csr |= pctl_m_mwin;
340
341 /*
342 * If it's an AGP port, initialize agplastwr.
343 */
344 if (titan_query_agp(port))
345 port->port_specific.a.agplastwr.csr = __direct_map_base;
346
347 titan_pci_tbi(hose, 0, -1);
348 }
349
350 static void __init
titan_init_pachips(titan_pachip * pachip0,titan_pachip * pachip1)351 titan_init_pachips(titan_pachip *pachip0, titan_pachip *pachip1)
352 {
353 titan_pchip1_present = TITAN_cchip->csc.csr & 1L<<14;
354
355 /* Init the ports in hose order... */
356 titan_init_one_pachip_port(&pachip0->g_port, 0); /* hose 0 */
357 if (titan_pchip1_present)
358 titan_init_one_pachip_port(&pachip1->g_port, 1);/* hose 1 */
359 titan_init_one_pachip_port(&pachip0->a_port, 2); /* hose 2 */
360 if (titan_pchip1_present)
361 titan_init_one_pachip_port(&pachip1->a_port, 3);/* hose 3 */
362 }
363
364 void __init
titan_init_arch(void)365 titan_init_arch(void)
366 {
367 #if 0
368 printk("%s: titan_init_arch()\n", __func__);
369 printk("%s: CChip registers:\n", __func__);
370 printk("%s: CSR_CSC 0x%lx\n", __func__, TITAN_cchip->csc.csr);
371 printk("%s: CSR_MTR 0x%lx\n", __func__, TITAN_cchip->mtr.csr);
372 printk("%s: CSR_MISC 0x%lx\n", __func__, TITAN_cchip->misc.csr);
373 printk("%s: CSR_DIM0 0x%lx\n", __func__, TITAN_cchip->dim0.csr);
374 printk("%s: CSR_DIM1 0x%lx\n", __func__, TITAN_cchip->dim1.csr);
375 printk("%s: CSR_DIR0 0x%lx\n", __func__, TITAN_cchip->dir0.csr);
376 printk("%s: CSR_DIR1 0x%lx\n", __func__, TITAN_cchip->dir1.csr);
377 printk("%s: CSR_DRIR 0x%lx\n", __func__, TITAN_cchip->drir.csr);
378
379 printk("%s: DChip registers:\n", __func__);
380 printk("%s: CSR_DSC 0x%lx\n", __func__, TITAN_dchip->dsc.csr);
381 printk("%s: CSR_STR 0x%lx\n", __func__, TITAN_dchip->str.csr);
382 printk("%s: CSR_DREV 0x%lx\n", __func__, TITAN_dchip->drev.csr);
383 #endif
384
385 boot_cpuid = __hard_smp_processor_id();
386
387 /* With multiple PCI busses, we play with I/O as physical addrs. */
388 ioport_resource.end = ~0UL;
389 iomem_resource.end = ~0UL;
390
391 /* PCI DMA Direct Mapping is 1GB at 2GB. */
392 __direct_map_base = 0x80000000;
393 __direct_map_size = 0x40000000;
394
395 /* Init the PA chip(s). */
396 titan_init_pachips(TITAN_pachip0, TITAN_pachip1);
397
398 /* Check for graphic console location (if any). */
399 find_console_vga_hose();
400 }
401
402 static void
titan_kill_one_pachip_port(titan_pachip_port * port,int index)403 titan_kill_one_pachip_port(titan_pachip_port *port, int index)
404 {
405 port->wsba[0].csr = saved_config[index].wsba[0];
406 port->wsm[0].csr = saved_config[index].wsm[0];
407 port->tba[0].csr = saved_config[index].tba[0];
408
409 port->wsba[1].csr = saved_config[index].wsba[1];
410 port->wsm[1].csr = saved_config[index].wsm[1];
411 port->tba[1].csr = saved_config[index].tba[1];
412
413 port->wsba[2].csr = saved_config[index].wsba[2];
414 port->wsm[2].csr = saved_config[index].wsm[2];
415 port->tba[2].csr = saved_config[index].tba[2];
416
417 port->wsba[3].csr = saved_config[index].wsba[3];
418 port->wsm[3].csr = saved_config[index].wsm[3];
419 port->tba[3].csr = saved_config[index].tba[3];
420 }
421
422 static void
titan_kill_pachips(titan_pachip * pachip0,titan_pachip * pachip1)423 titan_kill_pachips(titan_pachip *pachip0, titan_pachip *pachip1)
424 {
425 if (titan_pchip1_present) {
426 titan_kill_one_pachip_port(&pachip1->g_port, 1);
427 titan_kill_one_pachip_port(&pachip1->a_port, 3);
428 }
429 titan_kill_one_pachip_port(&pachip0->g_port, 0);
430 titan_kill_one_pachip_port(&pachip0->a_port, 2);
431 }
432
433 void
titan_kill_arch(int mode)434 titan_kill_arch(int mode)
435 {
436 titan_kill_pachips(TITAN_pachip0, TITAN_pachip1);
437 }
438
439
440 /*
441 * IO map support.
442 */
443
444 void __iomem *
titan_ioportmap(unsigned long addr)445 titan_ioportmap(unsigned long addr)
446 {
447 FIXUP_IOADDR_VGA(addr);
448 return (void __iomem *)(addr + TITAN_IO_BIAS);
449 }
450
451
452 void __iomem *
titan_ioremap(unsigned long addr,unsigned long size)453 titan_ioremap(unsigned long addr, unsigned long size)
454 {
455 int h = (addr & TITAN_HOSE_MASK) >> TITAN_HOSE_SHIFT;
456 unsigned long baddr = addr & ~TITAN_HOSE_MASK;
457 unsigned long last = baddr + size - 1;
458 struct pci_controller *hose;
459 struct vm_struct *area;
460 unsigned long vaddr;
461 unsigned long *ptes;
462 unsigned long pfn;
463
464 /*
465 * Adjust the address and hose, if necessary.
466 */
467 if (pci_vga_hose && __is_mem_vga(addr)) {
468 h = pci_vga_hose->index;
469 addr += pci_vga_hose->mem_space->start;
470 }
471
472 /*
473 * Find the hose.
474 */
475 for (hose = hose_head; hose; hose = hose->next)
476 if (hose->index == h)
477 break;
478 if (!hose)
479 return NULL;
480
481 /*
482 * Is it direct-mapped?
483 */
484 if ((baddr >= __direct_map_base) &&
485 ((baddr + size - 1) < __direct_map_base + __direct_map_size)) {
486 vaddr = addr - __direct_map_base + TITAN_MEM_BIAS;
487 return (void __iomem *) vaddr;
488 }
489
490 /*
491 * Check the scatter-gather arena.
492 */
493 if (hose->sg_pci &&
494 baddr >= (unsigned long)hose->sg_pci->dma_base &&
495 last < (unsigned long)hose->sg_pci->dma_base + hose->sg_pci->size){
496
497 /*
498 * Adjust the limits (mappings must be page aligned)
499 */
500 baddr -= hose->sg_pci->dma_base;
501 last -= hose->sg_pci->dma_base;
502 baddr &= PAGE_MASK;
503 size = PAGE_ALIGN(last) - baddr;
504
505 /*
506 * Map it
507 */
508 area = get_vm_area(size, VM_IOREMAP);
509 if (!area) {
510 printk("ioremap failed... no vm_area...\n");
511 return NULL;
512 }
513
514 ptes = hose->sg_pci->ptes;
515 for (vaddr = (unsigned long)area->addr;
516 baddr <= last;
517 baddr += PAGE_SIZE, vaddr += PAGE_SIZE) {
518 pfn = ptes[baddr >> PAGE_SHIFT];
519 if (!(pfn & 1)) {
520 printk("ioremap failed... pte not valid...\n");
521 vfree(area->addr);
522 return NULL;
523 }
524 pfn >>= 1; /* make it a true pfn */
525
526 if (__alpha_remap_area_pages(vaddr,
527 pfn << PAGE_SHIFT,
528 PAGE_SIZE, 0)) {
529 printk("FAILED to remap_area_pages...\n");
530 vfree(area->addr);
531 return NULL;
532 }
533 }
534
535 flush_tlb_all();
536
537 vaddr = (unsigned long)area->addr + (addr & ~PAGE_MASK);
538 return (void __iomem *) vaddr;
539 }
540
541 /* Assume a legacy (read: VGA) address, and return appropriately. */
542 return (void __iomem *)(addr + TITAN_MEM_BIAS);
543 }
544
545 void
titan_iounmap(volatile void __iomem * xaddr)546 titan_iounmap(volatile void __iomem *xaddr)
547 {
548 unsigned long addr = (unsigned long) xaddr;
549 if (addr >= VMALLOC_START)
550 vfree((void *)(PAGE_MASK & addr));
551 }
552
553 int
titan_is_mmio(const volatile void __iomem * xaddr)554 titan_is_mmio(const volatile void __iomem *xaddr)
555 {
556 unsigned long addr = (unsigned long) xaddr;
557
558 if (addr >= VMALLOC_START)
559 return 1;
560 else
561 return (addr & 0x100000000UL) == 0;
562 }
563
564 #ifndef CONFIG_ALPHA_GENERIC
565 EXPORT_SYMBOL(titan_ioportmap);
566 EXPORT_SYMBOL(titan_ioremap);
567 EXPORT_SYMBOL(titan_iounmap);
568 EXPORT_SYMBOL(titan_is_mmio);
569 #endif
570
571 /*
572 * AGP GART Support.
573 */
574 #include <linux/agp_backend.h>
575 #include <asm/agp_backend.h>
576 #include <linux/slab.h>
577 #include <linux/delay.h>
578
579 struct titan_agp_aperture {
580 struct pci_iommu_arena *arena;
581 long pg_start;
582 long pg_count;
583 };
584
585 static int
titan_agp_setup(alpha_agp_info * agp)586 titan_agp_setup(alpha_agp_info *agp)
587 {
588 struct titan_agp_aperture *aper;
589
590 if (!alpha_agpgart_size)
591 return -ENOMEM;
592
593 aper = kmalloc(sizeof(struct titan_agp_aperture), GFP_KERNEL);
594 if (aper == NULL)
595 return -ENOMEM;
596
597 aper->arena = agp->hose->sg_pci;
598 aper->pg_count = alpha_agpgart_size / PAGE_SIZE;
599 aper->pg_start = iommu_reserve(aper->arena, aper->pg_count,
600 aper->pg_count - 1);
601 if (aper->pg_start < 0) {
602 printk(KERN_ERR "Failed to reserve AGP memory\n");
603 kfree(aper);
604 return -ENOMEM;
605 }
606
607 agp->aperture.bus_base =
608 aper->arena->dma_base + aper->pg_start * PAGE_SIZE;
609 agp->aperture.size = aper->pg_count * PAGE_SIZE;
610 agp->aperture.sysdata = aper;
611
612 return 0;
613 }
614
615 static void
titan_agp_cleanup(alpha_agp_info * agp)616 titan_agp_cleanup(alpha_agp_info *agp)
617 {
618 struct titan_agp_aperture *aper = agp->aperture.sysdata;
619 int status;
620
621 status = iommu_release(aper->arena, aper->pg_start, aper->pg_count);
622 if (status == -EBUSY) {
623 printk(KERN_WARNING
624 "Attempted to release bound AGP memory - unbinding\n");
625 iommu_unbind(aper->arena, aper->pg_start, aper->pg_count);
626 status = iommu_release(aper->arena, aper->pg_start,
627 aper->pg_count);
628 }
629 if (status < 0)
630 printk(KERN_ERR "Failed to release AGP memory\n");
631
632 kfree(aper);
633 kfree(agp);
634 }
635
636 static int
titan_agp_configure(alpha_agp_info * agp)637 titan_agp_configure(alpha_agp_info *agp)
638 {
639 union TPAchipPCTL pctl;
640 titan_pachip_port *port = agp->private;
641 pctl.pctl_q_whole = port->pctl.csr;
642
643 /* Side-Band Addressing? */
644 pctl.pctl_r_bits.apctl_v_agp_sba_en = agp->mode.bits.sba;
645
646 /* AGP Rate? */
647 pctl.pctl_r_bits.apctl_v_agp_rate = 0; /* 1x */
648 if (agp->mode.bits.rate & 2)
649 pctl.pctl_r_bits.apctl_v_agp_rate = 1; /* 2x */
650 #if 0
651 if (agp->mode.bits.rate & 4)
652 pctl.pctl_r_bits.apctl_v_agp_rate = 2; /* 4x */
653 #endif
654
655 /* RQ Depth? */
656 pctl.pctl_r_bits.apctl_v_agp_hp_rd = 2;
657 pctl.pctl_r_bits.apctl_v_agp_lp_rd = 7;
658
659 /*
660 * AGP Enable.
661 */
662 pctl.pctl_r_bits.apctl_v_agp_en = agp->mode.bits.enable;
663
664 /* Tell the user. */
665 printk("Enabling AGP: %dX%s\n",
666 1 << pctl.pctl_r_bits.apctl_v_agp_rate,
667 pctl.pctl_r_bits.apctl_v_agp_sba_en ? " - SBA" : "");
668
669 /* Write it. */
670 port->pctl.csr = pctl.pctl_q_whole;
671
672 /* And wait at least 5000 66MHz cycles (per Titan spec). */
673 udelay(100);
674
675 return 0;
676 }
677
678 static int
titan_agp_bind_memory(alpha_agp_info * agp,off_t pg_start,struct agp_memory * mem)679 titan_agp_bind_memory(alpha_agp_info *agp, off_t pg_start, struct agp_memory *mem)
680 {
681 struct titan_agp_aperture *aper = agp->aperture.sysdata;
682 return iommu_bind(aper->arena, aper->pg_start + pg_start,
683 mem->page_count, mem->pages);
684 }
685
686 static int
titan_agp_unbind_memory(alpha_agp_info * agp,off_t pg_start,struct agp_memory * mem)687 titan_agp_unbind_memory(alpha_agp_info *agp, off_t pg_start, struct agp_memory *mem)
688 {
689 struct titan_agp_aperture *aper = agp->aperture.sysdata;
690 return iommu_unbind(aper->arena, aper->pg_start + pg_start,
691 mem->page_count);
692 }
693
694 static unsigned long
titan_agp_translate(alpha_agp_info * agp,dma_addr_t addr)695 titan_agp_translate(alpha_agp_info *agp, dma_addr_t addr)
696 {
697 struct titan_agp_aperture *aper = agp->aperture.sysdata;
698 unsigned long baddr = addr - aper->arena->dma_base;
699 unsigned long pte;
700
701 if (addr < agp->aperture.bus_base ||
702 addr >= agp->aperture.bus_base + agp->aperture.size) {
703 printk("%s: addr out of range\n", __func__);
704 return -EINVAL;
705 }
706
707 pte = aper->arena->ptes[baddr >> PAGE_SHIFT];
708 if (!(pte & 1)) {
709 printk("%s: pte not valid\n", __func__);
710 return -EINVAL;
711 }
712
713 return (pte >> 1) << PAGE_SHIFT;
714 }
715
716 struct alpha_agp_ops titan_agp_ops =
717 {
718 .setup = titan_agp_setup,
719 .cleanup = titan_agp_cleanup,
720 .configure = titan_agp_configure,
721 .bind = titan_agp_bind_memory,
722 .unbind = titan_agp_unbind_memory,
723 .translate = titan_agp_translate
724 };
725
726 alpha_agp_info *
titan_agp_info(void)727 titan_agp_info(void)
728 {
729 alpha_agp_info *agp;
730 struct pci_controller *hose;
731 titan_pachip_port *port;
732 int hosenum = -1;
733 union TPAchipPCTL pctl;
734
735 /*
736 * Find the AGP port.
737 */
738 port = &TITAN_pachip0->a_port;
739 if (titan_query_agp(port))
740 hosenum = 2;
741 if (hosenum < 0 &&
742 titan_pchip1_present &&
743 titan_query_agp(port = &TITAN_pachip1->a_port))
744 hosenum = 3;
745
746 /*
747 * Find the hose the port is on.
748 */
749 for (hose = hose_head; hose; hose = hose->next)
750 if (hose->index == hosenum)
751 break;
752
753 if (!hose || !hose->sg_pci)
754 return NULL;
755
756 /*
757 * Allocate the info structure.
758 */
759 agp = kmalloc(sizeof(*agp), GFP_KERNEL);
760 if (!agp)
761 return NULL;
762
763 /*
764 * Fill it in.
765 */
766 agp->hose = hose;
767 agp->private = port;
768 agp->ops = &titan_agp_ops;
769
770 /*
771 * Aperture - not configured until ops.setup().
772 *
773 * FIXME - should we go ahead and allocate it here?
774 */
775 agp->aperture.bus_base = 0;
776 agp->aperture.size = 0;
777 agp->aperture.sysdata = NULL;
778
779 /*
780 * Capabilities.
781 */
782 agp->capability.lw = 0;
783 agp->capability.bits.rate = 3; /* 2x, 1x */
784 agp->capability.bits.sba = 1;
785 agp->capability.bits.rq = 7; /* 8 - 1 */
786
787 /*
788 * Mode.
789 */
790 pctl.pctl_q_whole = port->pctl.csr;
791 agp->mode.lw = 0;
792 agp->mode.bits.rate = 1 << pctl.pctl_r_bits.apctl_v_agp_rate;
793 agp->mode.bits.sba = pctl.pctl_r_bits.apctl_v_agp_sba_en;
794 agp->mode.bits.rq = 7; /* RQ Depth? */
795 agp->mode.bits.enable = pctl.pctl_r_bits.apctl_v_agp_en;
796
797 return agp;
798 }
799