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1 /*
2  * TX4938/4937 setup routines
3  * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4  *	    and RBTX49xx patch from CELF patch archive.
5  *
6  * 2003-2005 (c) MontaVista Software, Inc.
7  * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8  *
9  * This file is subject to the terms and conditions of the GNU General Public
10  * License.  See the file "COPYING" in the main directory of this archive
11  * for more details.
12  */
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/delay.h>
16 #include <linux/param.h>
17 #include <linux/ptrace.h>
18 #include <linux/mtd/physmap.h>
19 #include <linux/platform_device.h>
20 #include <asm/reboot.h>
21 #include <asm/traps.h>
22 #include <asm/txx9irq.h>
23 #include <asm/txx9tmr.h>
24 #include <asm/txx9pio.h>
25 #include <asm/txx9/generic.h>
26 #include <asm/txx9/ndfmc.h>
27 #include <asm/txx9/dmac.h>
28 #include <asm/txx9/tx4938.h>
29 
tx4938_wdr_init(void)30 static void __init tx4938_wdr_init(void)
31 {
32 	/* report watchdog reset status */
33 	if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST)
34 		pr_warn("Watchdog reset detected at 0x%lx\n",
35 			read_c0_errorepc());
36 	/* clear WatchDogReset (W1C) */
37 	tx4938_ccfg_set(TX4938_CCFG_WDRST);
38 	/* do reset on watchdog */
39 	tx4938_ccfg_set(TX4938_CCFG_WR);
40 }
41 
tx4938_wdt_init(void)42 void __init tx4938_wdt_init(void)
43 {
44 	txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
45 }
46 
tx4938_machine_restart(char * command)47 static void tx4938_machine_restart(char *command)
48 {
49 	local_irq_disable();
50 	pr_emerg("Rebooting (with %s watchdog reset)...\n",
51 		 (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) ?
52 		 "external" : "internal");
53 	/* clear watchdog status */
54 	tx4938_ccfg_set(TX4938_CCFG_WDRST);	/* W1C */
55 	txx9_wdt_now(TX4938_TMR_REG(2) & 0xfffffffffULL);
56 	while (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST))
57 		;
58 	mdelay(10);
59 	if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) {
60 		pr_emerg("Rebooting (with internal watchdog reset)...\n");
61 		/* External WDRST failed.  Do internal watchdog reset */
62 		tx4938_ccfg_clear(TX4938_CCFG_WDREXEN);
63 	}
64 	/* fallback */
65 	(*_machine_halt)();
66 }
67 
68 void show_registers(struct pt_regs *regs);
tx4938_be_handler(struct pt_regs * regs,int is_fixup)69 static int tx4938_be_handler(struct pt_regs *regs, int is_fixup)
70 {
71 	int data = regs->cp0_cause & 4;
72 	console_verbose();
73 	pr_err("%cBE exception at %#lx\n", data ? 'D' : 'I', regs->cp0_epc);
74 	pr_err("ccfg:%llx, toea:%llx\n",
75 	       (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
76 	       (unsigned long long)____raw_readq(&tx4938_ccfgptr->toea));
77 #ifdef CONFIG_PCI
78 	tx4927_report_pcic_status();
79 #endif
80 	show_registers(regs);
81 	panic("BusError!");
82 }
tx4938_be_init(void)83 static void __init tx4938_be_init(void)
84 {
85 	board_be_handler = tx4938_be_handler;
86 }
87 
88 static struct resource tx4938_sdram_resource[4];
89 static struct resource tx4938_sram_resource;
90 
91 #define TX4938_SRAM_SIZE 0x800
92 
tx4938_setup(void)93 void __init tx4938_setup(void)
94 {
95 	int i;
96 	__u32 divmode;
97 	unsigned int cpuclk = 0;
98 	u64 ccfg;
99 
100 	txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
101 			  TX4938_REG_SIZE);
102 	set_c0_config(TX49_CONF_CWFON);
103 
104 	/* SDRAMC,EBUSC are configured by PROM */
105 	for (i = 0; i < 8; i++) {
106 		if (!(TX4938_EBUSC_CR(i) & 0x8))
107 			continue;	/* disabled */
108 		txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
109 		txx9_ce_res[i].end =
110 			txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
111 		request_resource(&iomem_resource, &txx9_ce_res[i]);
112 	}
113 
114 	/* clocks */
115 	ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
116 	if (txx9_master_clock) {
117 		/* calculate gbus_clock and cpu_clock from master_clock */
118 		divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
119 		switch (divmode) {
120 		case TX4938_CCFG_DIVMODE_8:
121 		case TX4938_CCFG_DIVMODE_10:
122 		case TX4938_CCFG_DIVMODE_12:
123 		case TX4938_CCFG_DIVMODE_16:
124 		case TX4938_CCFG_DIVMODE_18:
125 			txx9_gbus_clock = txx9_master_clock * 4; break;
126 		default:
127 			txx9_gbus_clock = txx9_master_clock;
128 		}
129 		switch (divmode) {
130 		case TX4938_CCFG_DIVMODE_2:
131 		case TX4938_CCFG_DIVMODE_8:
132 			cpuclk = txx9_gbus_clock * 2; break;
133 		case TX4938_CCFG_DIVMODE_2_5:
134 		case TX4938_CCFG_DIVMODE_10:
135 			cpuclk = txx9_gbus_clock * 5 / 2; break;
136 		case TX4938_CCFG_DIVMODE_3:
137 		case TX4938_CCFG_DIVMODE_12:
138 			cpuclk = txx9_gbus_clock * 3; break;
139 		case TX4938_CCFG_DIVMODE_4:
140 		case TX4938_CCFG_DIVMODE_16:
141 			cpuclk = txx9_gbus_clock * 4; break;
142 		case TX4938_CCFG_DIVMODE_4_5:
143 		case TX4938_CCFG_DIVMODE_18:
144 			cpuclk = txx9_gbus_clock * 9 / 2; break;
145 		}
146 		txx9_cpu_clock = cpuclk;
147 	} else {
148 		if (txx9_cpu_clock == 0)
149 			txx9_cpu_clock = 300000000;	/* 300MHz */
150 		/* calculate gbus_clock and master_clock from cpu_clock */
151 		cpuclk = txx9_cpu_clock;
152 		divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
153 		switch (divmode) {
154 		case TX4938_CCFG_DIVMODE_2:
155 		case TX4938_CCFG_DIVMODE_8:
156 			txx9_gbus_clock = cpuclk / 2; break;
157 		case TX4938_CCFG_DIVMODE_2_5:
158 		case TX4938_CCFG_DIVMODE_10:
159 			txx9_gbus_clock = cpuclk * 2 / 5; break;
160 		case TX4938_CCFG_DIVMODE_3:
161 		case TX4938_CCFG_DIVMODE_12:
162 			txx9_gbus_clock = cpuclk / 3; break;
163 		case TX4938_CCFG_DIVMODE_4:
164 		case TX4938_CCFG_DIVMODE_16:
165 			txx9_gbus_clock = cpuclk / 4; break;
166 		case TX4938_CCFG_DIVMODE_4_5:
167 		case TX4938_CCFG_DIVMODE_18:
168 			txx9_gbus_clock = cpuclk * 2 / 9; break;
169 		}
170 		switch (divmode) {
171 		case TX4938_CCFG_DIVMODE_8:
172 		case TX4938_CCFG_DIVMODE_10:
173 		case TX4938_CCFG_DIVMODE_12:
174 		case TX4938_CCFG_DIVMODE_16:
175 		case TX4938_CCFG_DIVMODE_18:
176 			txx9_master_clock = txx9_gbus_clock / 4; break;
177 		default:
178 			txx9_master_clock = txx9_gbus_clock;
179 		}
180 	}
181 	/* change default value to udelay/mdelay take reasonable time */
182 	loops_per_jiffy = txx9_cpu_clock / HZ / 2;
183 
184 	/* CCFG */
185 	tx4938_wdr_init();
186 	/* clear BusErrorOnWrite flag (W1C) */
187 	tx4938_ccfg_set(TX4938_CCFG_BEOW);
188 	/* enable Timeout BusError */
189 	if (txx9_ccfg_toeon)
190 		tx4938_ccfg_set(TX4938_CCFG_TOE);
191 
192 	/* DMA selection */
193 	txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
194 
195 	/* Use external clock for external arbiter */
196 	if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
197 		txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
198 
199 	printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
200 	       txx9_pcode_str,
201 	       (cpuclk + 500000) / 1000000,
202 	       (txx9_master_clock + 500000) / 1000000,
203 	       (__u32)____raw_readq(&tx4938_ccfgptr->crir),
204 	       (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
205 	       (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
206 
207 	printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
208 	for (i = 0; i < 4; i++) {
209 		__u64 cr = TX4938_SDRAMC_CR(i);
210 		unsigned long base, size;
211 		if (!((__u32)cr & 0x00000400))
212 			continue;	/* disabled */
213 		base = (unsigned long)(cr >> 49) << 21;
214 		size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
215 		printk(" CR%d:%016llx", i, (unsigned long long)cr);
216 		tx4938_sdram_resource[i].name = "SDRAM";
217 		tx4938_sdram_resource[i].start = base;
218 		tx4938_sdram_resource[i].end = base + size - 1;
219 		tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
220 		request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
221 	}
222 	printk(" TR:%09llx\n",
223 	       (unsigned long long)____raw_readq(&tx4938_sdramcptr->tr));
224 
225 	/* SRAM */
226 	if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) {
227 		unsigned int size = TX4938_SRAM_SIZE;
228 		tx4938_sram_resource.name = "SRAM";
229 		tx4938_sram_resource.start =
230 			(____raw_readq(&tx4938_sramcptr->cr) >> (39-11))
231 			& ~(size - 1);
232 		tx4938_sram_resource.end =
233 			tx4938_sram_resource.start + TX4938_SRAM_SIZE - 1;
234 		tx4938_sram_resource.flags = IORESOURCE_MEM;
235 		request_resource(&iomem_resource, &tx4938_sram_resource);
236 	}
237 
238 	/* TMR */
239 	/* disable all timers */
240 	for (i = 0; i < TX4938_NR_TMR; i++)
241 		txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
242 
243 	/* PIO */
244 	txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
245 	__raw_writel(0, &tx4938_pioptr->maskcpu);
246 	__raw_writel(0, &tx4938_pioptr->maskext);
247 
248 	if (txx9_pcode == 0x4938) {
249 		__u64 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
250 		/* set PCIC1 reset */
251 		txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
252 		if (pcfg & (TX4938_PCFG_ETH0_SEL | TX4938_PCFG_ETH1_SEL)) {
253 			mdelay(1);	/* at least 128 cpu clock */
254 			/* clear PCIC1 reset */
255 			txx9_clear64(&tx4938_ccfgptr->clkctr,
256 				     TX4938_CLKCTR_PCIC1RST);
257 		} else {
258 			printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str);
259 			/* stop PCIC1 */
260 			txx9_set64(&tx4938_ccfgptr->clkctr,
261 				   TX4938_CLKCTR_PCIC1CKD);
262 		}
263 		if (!(pcfg & TX4938_PCFG_ETH0_SEL)) {
264 			printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str);
265 			txx9_set64(&tx4938_ccfgptr->clkctr,
266 				   TX4938_CLKCTR_ETH0RST);
267 			txx9_set64(&tx4938_ccfgptr->clkctr,
268 				   TX4938_CLKCTR_ETH0CKD);
269 		}
270 		if (!(pcfg & TX4938_PCFG_ETH1_SEL)) {
271 			printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str);
272 			txx9_set64(&tx4938_ccfgptr->clkctr,
273 				   TX4938_CLKCTR_ETH1RST);
274 			txx9_set64(&tx4938_ccfgptr->clkctr,
275 				   TX4938_CLKCTR_ETH1CKD);
276 		}
277 	}
278 
279 	_machine_restart = tx4938_machine_restart;
280 	board_be_init = tx4938_be_init;
281 }
282 
tx4938_time_init(unsigned int tmrnr)283 void __init tx4938_time_init(unsigned int tmrnr)
284 {
285 	if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
286 		txx9_clockevent_init(TX4938_TMR_REG(tmrnr) & 0xfffffffffULL,
287 				     TXX9_IRQ_BASE + TX4938_IR_TMR(tmrnr),
288 				     TXX9_IMCLK);
289 }
290 
tx4938_sio_init(unsigned int sclk,unsigned int cts_mask)291 void __init tx4938_sio_init(unsigned int sclk, unsigned int cts_mask)
292 {
293 	int i;
294 	unsigned int ch_mask = 0;
295 
296 	if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL)
297 		ch_mask |= 1 << 1; /* disable SIO1 by PCFG setting */
298 	for (i = 0; i < 2; i++) {
299 		if ((1 << i) & ch_mask)
300 			continue;
301 		txx9_sio_init(TX4938_SIO_REG(i) & 0xfffffffffULL,
302 			      TXX9_IRQ_BASE + TX4938_IR_SIO(i),
303 			      i, sclk, (1 << i) & cts_mask);
304 	}
305 }
306 
tx4938_spi_init(int busid)307 void __init tx4938_spi_init(int busid)
308 {
309 	txx9_spi_init(busid, TX4938_SPI_REG & 0xfffffffffULL,
310 		      TXX9_IRQ_BASE + TX4938_IR_SPI);
311 }
312 
tx4938_ethaddr_init(unsigned char * addr0,unsigned char * addr1)313 void __init tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
314 {
315 	u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg);
316 
317 	if (addr0 && (pcfg & TX4938_PCFG_ETH0_SEL))
318 		txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH0, addr0);
319 	if (addr1 && (pcfg & TX4938_PCFG_ETH1_SEL))
320 		txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH1, addr1);
321 }
322 
tx4938_mtd_init(int ch)323 void __init tx4938_mtd_init(int ch)
324 {
325 	struct physmap_flash_data pdata = {
326 		.width = TX4938_EBUSC_WIDTH(ch) / 8,
327 	};
328 	unsigned long start = txx9_ce_res[ch].start;
329 	unsigned long size = txx9_ce_res[ch].end - start + 1;
330 
331 	if (!(TX4938_EBUSC_CR(ch) & 0x8))
332 		return; /* disabled */
333 	txx9_physmap_flash_init(ch, start, size, &pdata);
334 }
335 
tx4938_ata_init(unsigned int irq,unsigned int shift,int tune)336 void __init tx4938_ata_init(unsigned int irq, unsigned int shift, int tune)
337 {
338 	struct platform_device *pdev;
339 	struct resource res[] = {
340 		{
341 			/* .start and .end are filled in later */
342 			.flags = IORESOURCE_MEM,
343 		}, {
344 			.start = irq,
345 			.flags = IORESOURCE_IRQ,
346 		},
347 	};
348 	struct tx4938ide_platform_info pdata = {
349 		.ioport_shift = shift,
350 		/*
351 		 * The IDE driver should not change bus timings if other ISA
352 		 * devices existed.
353 		 */
354 		.gbus_clock = tune ? txx9_gbus_clock : 0,
355 	};
356 	u64 ebccr;
357 	int i;
358 
359 	if ((__raw_readq(&tx4938_ccfgptr->pcfg) &
360 	     (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL))
361 	    != TX4938_PCFG_ATA_SEL)
362 		return;
363 	for (i = 0; i < 8; i++) {
364 		/* check EBCCRn.ISA, EBCCRn.BSZ, EBCCRn.ME */
365 		ebccr = __raw_readq(&tx4938_ebuscptr->cr[i]);
366 		if ((ebccr & 0x00f00008) == 0x00e00008)
367 			break;
368 	}
369 	if (i == 8)
370 		return;
371 	pdata.ebus_ch = i;
372 	res[0].start = ((ebccr >> 48) << 20) + 0x10000;
373 	res[0].end = res[0].start + 0x20000 - 1;
374 	pdev = platform_device_alloc("tx4938ide", -1);
375 	if (!pdev ||
376 	    platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
377 	    platform_device_add_data(pdev, &pdata, sizeof(pdata)) ||
378 	    platform_device_add(pdev))
379 		platform_device_put(pdev);
380 }
381 
tx4938_ndfmc_init(unsigned int hold,unsigned int spw)382 void __init tx4938_ndfmc_init(unsigned int hold, unsigned int spw)
383 {
384 	struct txx9ndfmc_platform_data plat_data = {
385 		.shift = 1,
386 		.gbus_clock = txx9_gbus_clock,
387 		.hold = hold,
388 		.spw = spw,
389 		.ch_mask = 1,
390 	};
391 	unsigned long baseaddr = TX4938_NDFMC_REG & 0xfffffffffULL;
392 
393 #ifdef __BIG_ENDIAN
394 	baseaddr += 4;
395 #endif
396 	if ((__raw_readq(&tx4938_ccfgptr->pcfg) &
397 	     (TX4938_PCFG_ATA_SEL|TX4938_PCFG_ISA_SEL|TX4938_PCFG_NDF_SEL)) ==
398 	    TX4938_PCFG_NDF_SEL)
399 		txx9_ndfmc_init(baseaddr, &plat_data);
400 }
401 
tx4938_dmac_init(int memcpy_chan0,int memcpy_chan1)402 void __init tx4938_dmac_init(int memcpy_chan0, int memcpy_chan1)
403 {
404 	struct txx9dmac_platform_data plat_data = {
405 		.have_64bit_regs = true,
406 	};
407 	int i;
408 
409 	for (i = 0; i < 2; i++) {
410 		plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0;
411 		txx9_dmac_init(i, TX4938_DMA_REG(i) & 0xfffffffffULL,
412 			       TXX9_IRQ_BASE + TX4938_IR_DMA(i, 0),
413 			       &plat_data);
414 	}
415 }
416 
tx4938_aclc_init(void)417 void __init tx4938_aclc_init(void)
418 {
419 	u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg);
420 
421 	if ((pcfg & TX4938_PCFG_SEL2) &&
422 	    !(pcfg & TX4938_PCFG_ETH0_SEL))
423 		txx9_aclc_init(TX4938_ACLC_REG & 0xfffffffffULL,
424 			       TXX9_IRQ_BASE + TX4938_IR_ACLC,
425 			       1, 0, 1);
426 }
427 
tx4938_sramc_init(void)428 void __init tx4938_sramc_init(void)
429 {
430 	if (tx4938_sram_resource.start)
431 		txx9_sramc_init(&tx4938_sram_resource);
432 }
433 
tx4938_stop_unused_modules(void)434 static void __init tx4938_stop_unused_modules(void)
435 {
436 	__u64 pcfg, rst = 0, ckd = 0;
437 	char buf[128];
438 
439 	buf[0] = '\0';
440 	local_irq_disable();
441 	pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
442 	switch (txx9_pcode) {
443 	case 0x4937:
444 		if (!(pcfg & TX4938_PCFG_SEL2)) {
445 			rst |= TX4938_CLKCTR_ACLRST;
446 			ckd |= TX4938_CLKCTR_ACLCKD;
447 			strcat(buf, " ACLC");
448 		}
449 		break;
450 	case 0x4938:
451 		if (!(pcfg & TX4938_PCFG_SEL2) ||
452 		    (pcfg & TX4938_PCFG_ETH0_SEL)) {
453 			rst |= TX4938_CLKCTR_ACLRST;
454 			ckd |= TX4938_CLKCTR_ACLCKD;
455 			strcat(buf, " ACLC");
456 		}
457 		if ((pcfg &
458 		     (TX4938_PCFG_ATA_SEL | TX4938_PCFG_ISA_SEL |
459 		      TX4938_PCFG_NDF_SEL))
460 		    != TX4938_PCFG_NDF_SEL) {
461 			rst |= TX4938_CLKCTR_NDFRST;
462 			ckd |= TX4938_CLKCTR_NDFCKD;
463 			strcat(buf, " NDFMC");
464 		}
465 		if (!(pcfg & TX4938_PCFG_SPI_SEL)) {
466 			rst |= TX4938_CLKCTR_SPIRST;
467 			ckd |= TX4938_CLKCTR_SPICKD;
468 			strcat(buf, " SPI");
469 		}
470 		break;
471 	}
472 	if (rst | ckd) {
473 		txx9_set64(&tx4938_ccfgptr->clkctr, rst);
474 		txx9_set64(&tx4938_ccfgptr->clkctr, ckd);
475 	}
476 	local_irq_enable();
477 	if (buf[0])
478 		pr_info("%s: stop%s\n", txx9_pcode_str, buf);
479 }
480 
tx4938_late_init(void)481 static int __init tx4938_late_init(void)
482 {
483 	if (txx9_pcode != 0x4937 && txx9_pcode != 0x4938)
484 		return -ENODEV;
485 	tx4938_stop_unused_modules();
486 	return 0;
487 }
488 late_initcall(tx4938_late_init);
489