1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Please try to maintain the following order within this file unless it makes
24 * sense to do otherwise. From top to bottom:
25 * 1. typedefs
26 * 2. #defines, and macros
27 * 3. structure definitions
28 * 4. function prototypes
29 *
30 * Within each section, please try to order by generation in ascending order,
31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
32 */
33
34 #ifndef __I915_GEM_GTT_H__
35 #define __I915_GEM_GTT_H__
36
37 struct drm_i915_file_private;
38
39 typedef uint32_t gen6_pte_t;
40 typedef uint64_t gen8_pte_t;
41 typedef uint64_t gen8_pde_t;
42 typedef uint64_t gen8_ppgtt_pdpe_t;
43 typedef uint64_t gen8_ppgtt_pml4e_t;
44
45 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
46
47
48 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
49 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
50 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
51 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
52 #define GEN6_PTE_CACHE_LLC (2 << 1)
53 #define GEN6_PTE_UNCACHED (1 << 1)
54 #define GEN6_PTE_VALID (1 << 0)
55
56 #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len))
57 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
58 #define I915_PDES 512
59 #define I915_PDE_MASK (I915_PDES - 1)
60 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
61
62 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
63 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
64 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
65 #define GEN6_PDE_SHIFT 22
66 #define GEN6_PDE_VALID (1 << 0)
67
68 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
69
70 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
71 #define BYT_PTE_WRITEABLE (1 << 1)
72
73 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits
74 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
75 */
76 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
77 (((bits) & 0x8) << (11 - 3)))
78 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
79 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
80 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
81 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
82 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
83 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
84 #define HSW_PTE_UNCACHED (0)
85 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
86 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
87
88 /* GEN8 legacy style address is defined as a 3 level page table:
89 * 31:30 | 29:21 | 20:12 | 11:0
90 * PDPE | PDE | PTE | offset
91 * The difference as compared to normal x86 3 level page table is the PDPEs are
92 * programmed via register.
93 *
94 * GEN8 48b legacy style address is defined as a 4 level page table:
95 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0
96 * PML4E | PDPE | PDE | PTE | offset
97 */
98 #define GEN8_PML4ES_PER_PML4 512
99 #define GEN8_PML4E_SHIFT 39
100 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1)
101 #define GEN8_PDPE_SHIFT 30
102 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page
103 * tables */
104 #define GEN8_PDPE_MASK 0x1ff
105 #define GEN8_PDE_SHIFT 21
106 #define GEN8_PDE_MASK 0x1ff
107 #define GEN8_PTE_SHIFT 12
108 #define GEN8_PTE_MASK 0x1ff
109 #define GEN8_LEGACY_PDPES 4
110 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t))
111
112 #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
113 GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES)
114
115 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD)
116 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
117 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
118 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
119
120 #define CHV_PPAT_SNOOP (1<<6)
121 #define GEN8_PPAT_AGE(x) (x<<4)
122 #define GEN8_PPAT_LLCeLLC (3<<2)
123 #define GEN8_PPAT_LLCELLC (2<<2)
124 #define GEN8_PPAT_LLC (1<<2)
125 #define GEN8_PPAT_WB (3<<0)
126 #define GEN8_PPAT_WT (2<<0)
127 #define GEN8_PPAT_WC (1<<0)
128 #define GEN8_PPAT_UC (0<<0)
129 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
130 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
131
132 enum i915_ggtt_view_type {
133 I915_GGTT_VIEW_NORMAL = 0,
134 I915_GGTT_VIEW_ROTATED,
135 I915_GGTT_VIEW_PARTIAL,
136 };
137
138 struct intel_rotation_info {
139 unsigned int height;
140 unsigned int pitch;
141 unsigned int uv_offset;
142 uint32_t pixel_format;
143 uint64_t fb_modifier;
144 unsigned int width_pages, height_pages;
145 uint64_t size;
146 unsigned int width_pages_uv, height_pages_uv;
147 uint64_t size_uv;
148 unsigned int uv_start_page;
149 };
150
151 struct i915_ggtt_view {
152 enum i915_ggtt_view_type type;
153
154 union {
155 struct {
156 u64 offset;
157 unsigned int size;
158 } partial;
159 } params;
160
161 struct sg_table *pages;
162
163 union {
164 struct intel_rotation_info rotation_info;
165 };
166 };
167
168 extern const struct i915_ggtt_view i915_ggtt_view_normal;
169 extern const struct i915_ggtt_view i915_ggtt_view_rotated;
170
171 enum i915_cache_level;
172
173 /**
174 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
175 * VMA's presence cannot be guaranteed before binding, or after unbinding the
176 * object into/from the address space.
177 *
178 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
179 * will always be <= an objects lifetime. So object refcounting should cover us.
180 */
181 struct i915_vma {
182 struct drm_mm_node node;
183 struct drm_i915_gem_object *obj;
184 struct i915_address_space *vm;
185
186 /** Flags and address space this VMA is bound to */
187 #define GLOBAL_BIND (1<<0)
188 #define LOCAL_BIND (1<<1)
189 unsigned int bound : 4;
190
191 /**
192 * Support different GGTT views into the same object.
193 * This means there can be multiple VMA mappings per object and per VM.
194 * i915_ggtt_view_type is used to distinguish between those entries.
195 * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also
196 * assumed in GEM functions which take no ggtt view parameter.
197 */
198 struct i915_ggtt_view ggtt_view;
199
200 /** This object's place on the active/inactive lists */
201 struct list_head mm_list;
202
203 struct list_head vma_link; /* Link in the object's VMA list */
204
205 /** This vma's place in the batchbuffer or on the eviction list */
206 struct list_head exec_list;
207
208 /**
209 * Used for performing relocations during execbuffer insertion.
210 */
211 struct hlist_node exec_node;
212 unsigned long exec_handle;
213 struct drm_i915_gem_exec_object2 *exec_entry;
214
215 /**
216 * How many users have pinned this object in GTT space. The following
217 * users can each hold at most one reference: pwrite/pread, execbuffer
218 * (objects are not allowed multiple times for the same batchbuffer),
219 * and the framebuffer code. When switching/pageflipping, the
220 * framebuffer code has at most two buffers pinned per crtc.
221 *
222 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
223 * bits with absolutely no headroom. So use 4 bits. */
224 unsigned int pin_count:4;
225 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
226 };
227
228 struct i915_page_dma {
229 struct page *page;
230 union {
231 dma_addr_t daddr;
232
233 /* For gen6/gen7 only. This is the offset in the GGTT
234 * where the page directory entries for PPGTT begin
235 */
236 uint32_t ggtt_offset;
237 };
238 };
239
240 #define px_base(px) (&(px)->base)
241 #define px_page(px) (px_base(px)->page)
242 #define px_dma(px) (px_base(px)->daddr)
243
244 struct i915_page_scratch {
245 struct i915_page_dma base;
246 };
247
248 struct i915_page_table {
249 struct i915_page_dma base;
250
251 unsigned long *used_ptes;
252 };
253
254 struct i915_page_directory {
255 struct i915_page_dma base;
256
257 unsigned long *used_pdes;
258 struct i915_page_table *page_table[I915_PDES]; /* PDEs */
259 };
260
261 struct i915_page_directory_pointer {
262 struct i915_page_dma base;
263
264 unsigned long *used_pdpes;
265 struct i915_page_directory **page_directory;
266 };
267
268 struct i915_pml4 {
269 struct i915_page_dma base;
270
271 DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4);
272 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4];
273 };
274
275 struct i915_address_space {
276 struct drm_mm mm;
277 struct drm_device *dev;
278 struct list_head global_link;
279 u64 start; /* Start offset always 0 for dri2 */
280 u64 total; /* size addr space maps (ex. 2GB for ggtt) */
281
282 struct i915_page_scratch *scratch_page;
283 struct i915_page_table *scratch_pt;
284 struct i915_page_directory *scratch_pd;
285 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */
286
287 /**
288 * List of objects currently involved in rendering.
289 *
290 * Includes buffers having the contents of their GPU caches
291 * flushed, not necessarily primitives. last_read_req
292 * represents when the rendering involved will be completed.
293 *
294 * A reference is held on the buffer while on this list.
295 */
296 struct list_head active_list;
297
298 /**
299 * LRU list of objects which are not in the ringbuffer and
300 * are ready to unbind, but are still in the GTT.
301 *
302 * last_read_req is NULL while an object is in this list.
303 *
304 * A reference is not held on the buffer while on this list,
305 * as merely being GTT-bound shouldn't prevent its being
306 * freed, and we'll pull it off the list in the free path.
307 */
308 struct list_head inactive_list;
309
310 /* Some systems support read-only mappings for GGTT and/or PPGTT */
311 bool has_read_only:1;
312
313 /* FIXME: Need a more generic return type */
314 gen6_pte_t (*pte_encode)(dma_addr_t addr,
315 enum i915_cache_level level,
316 bool valid, u32 flags); /* Create a valid PTE */
317 /* flags for pte_encode */
318 #define PTE_READ_ONLY (1<<0)
319 int (*allocate_va_range)(struct i915_address_space *vm,
320 uint64_t start,
321 uint64_t length);
322 void (*clear_range)(struct i915_address_space *vm,
323 uint64_t start,
324 uint64_t length,
325 bool use_scratch);
326 void (*insert_entries)(struct i915_address_space *vm,
327 struct sg_table *st,
328 uint64_t start,
329 enum i915_cache_level cache_level, u32 flags);
330 void (*cleanup)(struct i915_address_space *vm);
331 /** Unmap an object from an address space. This usually consists of
332 * setting the valid PTE entries to a reserved scratch page. */
333 void (*unbind_vma)(struct i915_vma *vma);
334 /* Map an object into an address space with the given cache flags. */
335 int (*bind_vma)(struct i915_vma *vma,
336 enum i915_cache_level cache_level,
337 u32 flags);
338 };
339
340 /* The Graphics Translation Table is the way in which GEN hardware translates a
341 * Graphics Virtual Address into a Physical Address. In addition to the normal
342 * collateral associated with any va->pa translations GEN hardware also has a
343 * portion of the GTT which can be mapped by the CPU and remain both coherent
344 * and correct (in cases like swizzling). That region is referred to as GMADR in
345 * the spec.
346 */
347 struct i915_gtt {
348 struct i915_address_space base;
349
350 size_t stolen_size; /* Total size of stolen memory */
351 size_t stolen_usable_size; /* Total size minus BIOS reserved */
352 u64 mappable_end; /* End offset that we can CPU map */
353 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
354 phys_addr_t mappable_base; /* PA of our GMADR */
355
356 /** "Graphics Stolen Memory" holds the global PTEs */
357 void __iomem *gsm;
358
359 bool do_idle_maps;
360
361 int mtrr;
362
363 /* global gtt ops */
364 int (*gtt_probe)(struct drm_device *dev, u64 *gtt_total,
365 size_t *stolen, phys_addr_t *mappable_base,
366 u64 *mappable_end);
367 };
368
369 struct i915_hw_ppgtt {
370 struct i915_address_space base;
371 struct kref ref;
372 struct drm_mm_node node;
373 unsigned long pd_dirty_rings;
374 union {
375 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */
376 struct i915_page_directory_pointer pdp; /* GEN8+ */
377 struct i915_page_directory pd; /* GEN6-7 */
378 };
379
380 struct drm_i915_file_private *file_priv;
381
382 gen6_pte_t __iomem *pd_addr;
383
384 int (*enable)(struct i915_hw_ppgtt *ppgtt);
385 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
386 struct drm_i915_gem_request *req);
387 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
388 };
389
390 /* For each pde iterates over every pde between from start until start + length.
391 * If start, and start+length are not perfectly divisible, the macro will round
392 * down, and up as needed. The macro modifies pde, start, and length. Dev is
393 * only used to differentiate shift values. Temp is temp. On gen6/7, start = 0,
394 * and length = 2G effectively iterates over every PDE in the system.
395 *
396 * XXX: temp is not actually needed, but it saves doing the ALIGN operation.
397 */
398 #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \
399 for (iter = gen6_pde_index(start); \
400 length > 0 && iter < I915_PDES ? \
401 (pt = (pd)->page_table[iter]), 1 : 0; \
402 iter++, \
403 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \
404 temp = min_t(unsigned, temp, length), \
405 start += temp, length -= temp)
406
407 #define gen6_for_all_pdes(pt, ppgtt, iter) \
408 for (iter = 0; \
409 pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \
410 iter++)
411
i915_pte_index(uint64_t address,uint32_t pde_shift)412 static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift)
413 {
414 const uint32_t mask = NUM_PTE(pde_shift) - 1;
415
416 return (address >> PAGE_SHIFT) & mask;
417 }
418
419 /* Helper to counts the number of PTEs within the given length. This count
420 * does not cross a page table boundary, so the max value would be
421 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
422 */
i915_pte_count(uint64_t addr,size_t length,uint32_t pde_shift)423 static inline uint32_t i915_pte_count(uint64_t addr, size_t length,
424 uint32_t pde_shift)
425 {
426 const uint64_t mask = ~((1 << pde_shift) - 1);
427 uint64_t end;
428
429 WARN_ON(length == 0);
430 WARN_ON(offset_in_page(addr|length));
431
432 end = addr + length;
433
434 if ((addr & mask) != (end & mask))
435 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
436
437 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
438 }
439
i915_pde_index(uint64_t addr,uint32_t shift)440 static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift)
441 {
442 return (addr >> shift) & I915_PDE_MASK;
443 }
444
gen6_pte_index(uint32_t addr)445 static inline uint32_t gen6_pte_index(uint32_t addr)
446 {
447 return i915_pte_index(addr, GEN6_PDE_SHIFT);
448 }
449
gen6_pte_count(uint32_t addr,uint32_t length)450 static inline size_t gen6_pte_count(uint32_t addr, uint32_t length)
451 {
452 return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
453 }
454
gen6_pde_index(uint32_t addr)455 static inline uint32_t gen6_pde_index(uint32_t addr)
456 {
457 return i915_pde_index(addr, GEN6_PDE_SHIFT);
458 }
459
460 /* Equivalent to the gen6 version, For each pde iterates over every pde
461 * between from start until start + length. On gen8+ it simply iterates
462 * over every page directory entry in a page directory.
463 */
464 #define gen8_for_each_pde(pt, pd, start, length, temp, iter) \
465 for (iter = gen8_pde_index(start); \
466 length > 0 && iter < I915_PDES ? \
467 (pt = (pd)->page_table[iter]), 1 : 0; \
468 iter++, \
469 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start, \
470 temp = min(temp, length), \
471 start += temp, length -= temp)
472
473 #define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter) \
474 for (iter = gen8_pdpe_index(start); \
475 length > 0 && (iter < I915_PDPES_PER_PDP(dev)) ? \
476 (pd = (pdp)->page_directory[iter]), 1 : 0; \
477 iter++, \
478 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start, \
479 temp = min(temp, length), \
480 start += temp, length -= temp)
481
482 #define gen8_for_each_pml4e(pdp, pml4, start, length, temp, iter) \
483 for (iter = gen8_pml4e_index(start); \
484 length > 0 && iter < GEN8_PML4ES_PER_PML4 ? \
485 (pdp = (pml4)->pdps[iter]), 1 : 0; \
486 iter++, \
487 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT) - start, \
488 temp = min(temp, length), \
489 start += temp, length -= temp)
490
gen8_pte_index(uint64_t address)491 static inline uint32_t gen8_pte_index(uint64_t address)
492 {
493 return i915_pte_index(address, GEN8_PDE_SHIFT);
494 }
495
gen8_pde_index(uint64_t address)496 static inline uint32_t gen8_pde_index(uint64_t address)
497 {
498 return i915_pde_index(address, GEN8_PDE_SHIFT);
499 }
500
gen8_pdpe_index(uint64_t address)501 static inline uint32_t gen8_pdpe_index(uint64_t address)
502 {
503 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK;
504 }
505
gen8_pml4e_index(uint64_t address)506 static inline uint32_t gen8_pml4e_index(uint64_t address)
507 {
508 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK;
509 }
510
gen8_pte_count(uint64_t address,uint64_t length)511 static inline size_t gen8_pte_count(uint64_t address, uint64_t length)
512 {
513 return i915_pte_count(address, length, GEN8_PDE_SHIFT);
514 }
515
516 static inline dma_addr_t
i915_page_dir_dma_addr(const struct i915_hw_ppgtt * ppgtt,const unsigned n)517 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
518 {
519 return test_bit(n, ppgtt->pdp.used_pdpes) ?
520 px_dma(ppgtt->pdp.page_directory[n]) :
521 px_dma(ppgtt->base.scratch_pd);
522 }
523
524 int i915_gem_gtt_init(struct drm_device *dev);
525 void i915_gem_init_global_gtt(struct drm_device *dev);
526 void i915_global_gtt_cleanup(struct drm_device *dev);
527
528
529 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
530 int i915_ppgtt_init_hw(struct drm_device *dev);
531 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req);
532 void i915_ppgtt_release(struct kref *kref);
533 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev,
534 struct drm_i915_file_private *fpriv);
i915_ppgtt_get(struct i915_hw_ppgtt * ppgtt)535 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
536 {
537 if (ppgtt)
538 kref_get(&ppgtt->ref);
539 }
i915_ppgtt_put(struct i915_hw_ppgtt * ppgtt)540 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
541 {
542 if (ppgtt)
543 kref_put(&ppgtt->ref, i915_ppgtt_release);
544 }
545
546 void i915_check_and_clear_faults(struct drm_device *dev);
547 void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
548 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
549
550 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
551 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
552
553 static inline bool
i915_ggtt_view_equal(const struct i915_ggtt_view * a,const struct i915_ggtt_view * b)554 i915_ggtt_view_equal(const struct i915_ggtt_view *a,
555 const struct i915_ggtt_view *b)
556 {
557 if (WARN_ON(!a || !b))
558 return false;
559
560 if (a->type != b->type)
561 return false;
562 if (a->type == I915_GGTT_VIEW_PARTIAL)
563 return !memcmp(&a->params, &b->params, sizeof(a->params));
564 return true;
565 }
566
567 size_t
568 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
569 const struct i915_ggtt_view *view);
570
571 #endif
572