1 /*
2 * User-space Probes (UProbes) for x86
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * Copyright (C) IBM Corporation, 2008-2011
19 * Authors:
20 * Srikar Dronamraju
21 * Jim Keniston
22 */
23 #include <linux/kernel.h>
24 #include <linux/sched.h>
25 #include <linux/ptrace.h>
26 #include <linux/uprobes.h>
27 #include <linux/uaccess.h>
28
29 #include <linux/kdebug.h>
30 #include <asm/processor.h>
31 #include <asm/insn.h>
32 #include <asm/mmu_context.h>
33
34 /* Post-execution fixups. */
35
36 /* Adjust IP back to vicinity of actual insn */
37 #define UPROBE_FIX_IP 0x01
38
39 /* Adjust the return address of a call insn */
40 #define UPROBE_FIX_CALL 0x02
41
42 /* Instruction will modify TF, don't change it */
43 #define UPROBE_FIX_SETF 0x04
44
45 #define UPROBE_FIX_RIP_SI 0x08
46 #define UPROBE_FIX_RIP_DI 0x10
47 #define UPROBE_FIX_RIP_BX 0x20
48 #define UPROBE_FIX_RIP_MASK \
49 (UPROBE_FIX_RIP_SI | UPROBE_FIX_RIP_DI | UPROBE_FIX_RIP_BX)
50
51 #define UPROBE_TRAP_NR UINT_MAX
52
53 /* Adaptations for mhiramat x86 decoder v14. */
54 #define OPCODE1(insn) ((insn)->opcode.bytes[0])
55 #define OPCODE2(insn) ((insn)->opcode.bytes[1])
56 #define OPCODE3(insn) ((insn)->opcode.bytes[2])
57 #define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value)
58
59 #define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\
60 (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \
61 (b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \
62 (b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \
63 (bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \
64 << (row % 32))
65
66 /*
67 * Good-instruction tables for 32-bit apps. This is non-const and volatile
68 * to keep gcc from statically optimizing it out, as variable_test_bit makes
69 * some versions of gcc to think only *(unsigned long*) is used.
70 *
71 * Opcodes we'll probably never support:
72 * 6c-6f - ins,outs. SEGVs if used in userspace
73 * e4-e7 - in,out imm. SEGVs if used in userspace
74 * ec-ef - in,out acc. SEGVs if used in userspace
75 * cc - int3. SIGTRAP if used in userspace
76 * ce - into. Not used in userspace - no kernel support to make it useful. SEGVs
77 * (why we support bound (62) then? it's similar, and similarly unused...)
78 * f1 - int1. SIGTRAP if used in userspace
79 * f4 - hlt. SEGVs if used in userspace
80 * fa - cli. SEGVs if used in userspace
81 * fb - sti. SEGVs if used in userspace
82 *
83 * Opcodes which need some work to be supported:
84 * 07,17,1f - pop es/ss/ds
85 * Normally not used in userspace, but would execute if used.
86 * Can cause GP or stack exception if tries to load wrong segment descriptor.
87 * We hesitate to run them under single step since kernel's handling
88 * of userspace single-stepping (TF flag) is fragile.
89 * We can easily refuse to support push es/cs/ss/ds (06/0e/16/1e)
90 * on the same grounds that they are never used.
91 * cd - int N.
92 * Used by userspace for "int 80" syscall entry. (Other "int N"
93 * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3).
94 * Not supported since kernel's handling of userspace single-stepping
95 * (TF flag) is fragile.
96 * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad
97 */
98 #if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION)
99 static volatile u32 good_insns_32[256 / 32] = {
100 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
101 /* ---------------------------------------------- */
102 W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 00 */
103 W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */
104 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
105 W(0x30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */
106 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
107 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
108 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
109 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
110 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
111 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
112 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
113 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
114 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
115 W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
116 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */
117 W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
118 /* ---------------------------------------------- */
119 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
120 };
121 #else
122 #define good_insns_32 NULL
123 #endif
124
125 /* Good-instruction tables for 64-bit apps.
126 *
127 * Genuinely invalid opcodes:
128 * 06,07 - formerly push/pop es
129 * 0e - formerly push cs
130 * 16,17 - formerly push/pop ss
131 * 1e,1f - formerly push/pop ds
132 * 27,2f,37,3f - formerly daa/das/aaa/aas
133 * 60,61 - formerly pusha/popa
134 * 62 - formerly bound. EVEX prefix for AVX512 (not yet supported)
135 * 82 - formerly redundant encoding of Group1
136 * 9a - formerly call seg:ofs
137 * ce - formerly into
138 * d4,d5 - formerly aam/aad
139 * d6 - formerly undocumented salc
140 * ea - formerly jmp seg:ofs
141 *
142 * Opcodes we'll probably never support:
143 * 6c-6f - ins,outs. SEGVs if used in userspace
144 * e4-e7 - in,out imm. SEGVs if used in userspace
145 * ec-ef - in,out acc. SEGVs if used in userspace
146 * cc - int3. SIGTRAP if used in userspace
147 * f1 - int1. SIGTRAP if used in userspace
148 * f4 - hlt. SEGVs if used in userspace
149 * fa - cli. SEGVs if used in userspace
150 * fb - sti. SEGVs if used in userspace
151 *
152 * Opcodes which need some work to be supported:
153 * cd - int N.
154 * Used by userspace for "int 80" syscall entry. (Other "int N"
155 * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3).
156 * Not supported since kernel's handling of userspace single-stepping
157 * (TF flag) is fragile.
158 * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad
159 */
160 #if defined(CONFIG_X86_64)
161 static volatile u32 good_insns_64[256 / 32] = {
162 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
163 /* ---------------------------------------------- */
164 W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* 00 */
165 W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */
166 W(0x20, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 20 */
167 W(0x30, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 30 */
168 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
169 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
170 W(0x60, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
171 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
172 W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
173 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1) , /* 90 */
174 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
175 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
176 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
177 W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
178 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0) | /* e0 */
179 W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
180 /* ---------------------------------------------- */
181 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
182 };
183 #else
184 #define good_insns_64 NULL
185 #endif
186
187 /* Using this for both 64-bit and 32-bit apps.
188 * Opcodes we don't support:
189 * 0f 00 - SLDT/STR/LLDT/LTR/VERR/VERW/-/- group. System insns
190 * 0f 01 - SGDT/SIDT/LGDT/LIDT/SMSW/-/LMSW/INVLPG group.
191 * Also encodes tons of other system insns if mod=11.
192 * Some are in fact non-system: xend, xtest, rdtscp, maybe more
193 * 0f 05 - syscall
194 * 0f 06 - clts (CPL0 insn)
195 * 0f 07 - sysret
196 * 0f 08 - invd (CPL0 insn)
197 * 0f 09 - wbinvd (CPL0 insn)
198 * 0f 0b - ud2
199 * 0f 30 - wrmsr (CPL0 insn) (then why rdmsr is allowed, it's also CPL0 insn?)
200 * 0f 34 - sysenter
201 * 0f 35 - sysexit
202 * 0f 37 - getsec
203 * 0f 78 - vmread (Intel VMX. CPL0 insn)
204 * 0f 79 - vmwrite (Intel VMX. CPL0 insn)
205 * Note: with prefixes, these two opcodes are
206 * extrq/insertq/AVX512 convert vector ops.
207 * 0f ae - group15: [f]xsave,[f]xrstor,[v]{ld,st}mxcsr,clflush[opt],
208 * {rd,wr}{fs,gs}base,{s,l,m}fence.
209 * Why? They are all user-executable.
210 */
211 static volatile u32 good_2byte_insns[256 / 32] = {
212 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
213 /* ---------------------------------------------- */
214 W(0x00, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1) | /* 00 */
215 W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 10 */
216 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
217 W(0x30, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */
218 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
219 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
220 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */
221 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1) , /* 70 */
222 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
223 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
224 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */
225 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
226 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */
227 W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
228 W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */
229 W(0xf0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) /* f0 */
230 /* ---------------------------------------------- */
231 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
232 };
233 #undef W
234
235 /*
236 * opcodes we may need to refine support for:
237 *
238 * 0f - 2-byte instructions: For many of these instructions, the validity
239 * depends on the prefix and/or the reg field. On such instructions, we
240 * just consider the opcode combination valid if it corresponds to any
241 * valid instruction.
242 *
243 * 8f - Group 1 - only reg = 0 is OK
244 * c6-c7 - Group 11 - only reg = 0 is OK
245 * d9-df - fpu insns with some illegal encodings
246 * f2, f3 - repnz, repz prefixes. These are also the first byte for
247 * certain floating-point instructions, such as addsd.
248 *
249 * fe - Group 4 - only reg = 0 or 1 is OK
250 * ff - Group 5 - only reg = 0-6 is OK
251 *
252 * others -- Do we need to support these?
253 *
254 * 0f - (floating-point?) prefetch instructions
255 * 07, 17, 1f - pop es, pop ss, pop ds
256 * 26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes --
257 * but 64 and 65 (fs: and gs:) seem to be used, so we support them
258 * 67 - addr16 prefix
259 * ce - into
260 * f0 - lock prefix
261 */
262
263 /*
264 * TODO:
265 * - Where necessary, examine the modrm byte and allow only valid instructions
266 * in the different Groups and fpu instructions.
267 */
268
is_prefix_bad(struct insn * insn)269 static bool is_prefix_bad(struct insn *insn)
270 {
271 insn_byte_t p;
272 int i;
273
274 for_each_insn_prefix(insn, i, p) {
275 switch (p) {
276 case 0x26: /* INAT_PFX_ES */
277 case 0x2E: /* INAT_PFX_CS */
278 case 0x36: /* INAT_PFX_DS */
279 case 0x3E: /* INAT_PFX_SS */
280 case 0xF0: /* INAT_PFX_LOCK */
281 return true;
282 }
283 }
284 return false;
285 }
286
uprobe_init_insn(struct arch_uprobe * auprobe,struct insn * insn,bool x86_64)287 static int uprobe_init_insn(struct arch_uprobe *auprobe, struct insn *insn, bool x86_64)
288 {
289 u32 volatile *good_insns;
290
291 insn_init(insn, auprobe->insn, sizeof(auprobe->insn), x86_64);
292 /* has the side-effect of processing the entire instruction */
293 insn_get_length(insn);
294 if (!insn_complete(insn))
295 return -ENOEXEC;
296
297 if (is_prefix_bad(insn))
298 return -ENOTSUPP;
299
300 /* We should not singlestep on the exception masking instructions */
301 if (insn_masking_exception(insn))
302 return -ENOTSUPP;
303
304 if (x86_64)
305 good_insns = good_insns_64;
306 else
307 good_insns = good_insns_32;
308
309 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns))
310 return 0;
311
312 if (insn->opcode.nbytes == 2) {
313 if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns))
314 return 0;
315 }
316
317 return -ENOTSUPP;
318 }
319
320 #ifdef CONFIG_X86_64
321 /*
322 * If arch_uprobe->insn doesn't use rip-relative addressing, return
323 * immediately. Otherwise, rewrite the instruction so that it accesses
324 * its memory operand indirectly through a scratch register. Set
325 * defparam->fixups accordingly. (The contents of the scratch register
326 * will be saved before we single-step the modified instruction,
327 * and restored afterward).
328 *
329 * We do this because a rip-relative instruction can access only a
330 * relatively small area (+/- 2 GB from the instruction), and the XOL
331 * area typically lies beyond that area. At least for instructions
332 * that store to memory, we can't execute the original instruction
333 * and "fix things up" later, because the misdirected store could be
334 * disastrous.
335 *
336 * Some useful facts about rip-relative instructions:
337 *
338 * - There's always a modrm byte with bit layout "00 reg 101".
339 * - There's never a SIB byte.
340 * - The displacement is always 4 bytes.
341 * - REX.B=1 bit in REX prefix, which normally extends r/m field,
342 * has no effect on rip-relative mode. It doesn't make modrm byte
343 * with r/m=101 refer to register 1101 = R13.
344 */
riprel_analyze(struct arch_uprobe * auprobe,struct insn * insn)345 static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn)
346 {
347 u8 *cursor;
348 u8 reg;
349 u8 reg2;
350
351 if (!insn_rip_relative(insn))
352 return;
353
354 /*
355 * insn_rip_relative() would have decoded rex_prefix, vex_prefix, modrm.
356 * Clear REX.b bit (extension of MODRM.rm field):
357 * we want to encode low numbered reg, not r8+.
358 */
359 if (insn->rex_prefix.nbytes) {
360 cursor = auprobe->insn + insn_offset_rex_prefix(insn);
361 /* REX byte has 0100wrxb layout, clearing REX.b bit */
362 *cursor &= 0xfe;
363 }
364 /*
365 * Similar treatment for VEX3/EVEX prefix.
366 * TODO: add XOP treatment when insn decoder supports them
367 */
368 if (insn->vex_prefix.nbytes >= 3) {
369 /*
370 * vex2: c5 rvvvvLpp (has no b bit)
371 * vex3/xop: c4/8f rxbmmmmm wvvvvLpp
372 * evex: 62 rxbR00mm wvvvv1pp zllBVaaa
373 * Setting VEX3.b (setting because it has inverted meaning).
374 * Setting EVEX.x since (in non-SIB encoding) EVEX.x
375 * is the 4th bit of MODRM.rm, and needs the same treatment.
376 * For VEX3-encoded insns, VEX3.x value has no effect in
377 * non-SIB encoding, the change is superfluous but harmless.
378 */
379 cursor = auprobe->insn + insn_offset_vex_prefix(insn) + 1;
380 *cursor |= 0x60;
381 }
382
383 /*
384 * Convert from rip-relative addressing to register-relative addressing
385 * via a scratch register.
386 *
387 * This is tricky since there are insns with modrm byte
388 * which also use registers not encoded in modrm byte:
389 * [i]div/[i]mul: implicitly use dx:ax
390 * shift ops: implicitly use cx
391 * cmpxchg: implicitly uses ax
392 * cmpxchg8/16b: implicitly uses dx:ax and bx:cx
393 * Encoding: 0f c7/1 modrm
394 * The code below thinks that reg=1 (cx), chooses si as scratch.
395 * mulx: implicitly uses dx: mulx r/m,r1,r2 does r1:r2 = dx * r/m.
396 * First appeared in Haswell (BMI2 insn). It is vex-encoded.
397 * Example where none of bx,cx,dx can be used as scratch reg:
398 * c4 e2 63 f6 0d disp32 mulx disp32(%rip),%ebx,%ecx
399 * [v]pcmpistri: implicitly uses cx, xmm0
400 * [v]pcmpistrm: implicitly uses xmm0
401 * [v]pcmpestri: implicitly uses ax, dx, cx, xmm0
402 * [v]pcmpestrm: implicitly uses ax, dx, xmm0
403 * Evil SSE4.2 string comparison ops from hell.
404 * maskmovq/[v]maskmovdqu: implicitly uses (ds:rdi) as destination.
405 * Encoding: 0f f7 modrm, 66 0f f7 modrm, vex-encoded: c5 f9 f7 modrm.
406 * Store op1, byte-masked by op2 msb's in each byte, to (ds:rdi).
407 * AMD says it has no 3-operand form (vex.vvvv must be 1111)
408 * and that it can have only register operands, not mem
409 * (its modrm byte must have mode=11).
410 * If these restrictions will ever be lifted,
411 * we'll need code to prevent selection of di as scratch reg!
412 *
413 * Summary: I don't know any insns with modrm byte which
414 * use SI register implicitly. DI register is used only
415 * by one insn (maskmovq) and BX register is used
416 * only by one too (cmpxchg8b).
417 * BP is stack-segment based (may be a problem?).
418 * AX, DX, CX are off-limits (many implicit users).
419 * SP is unusable (it's stack pointer - think about "pop mem";
420 * also, rsp+disp32 needs sib encoding -> insn length change).
421 */
422
423 reg = MODRM_REG(insn); /* Fetch modrm.reg */
424 reg2 = 0xff; /* Fetch vex.vvvv */
425 if (insn->vex_prefix.nbytes)
426 reg2 = insn->vex_prefix.bytes[2];
427 /*
428 * TODO: add XOP vvvv reading.
429 *
430 * vex.vvvv field is in bits 6-3, bits are inverted.
431 * But in 32-bit mode, high-order bit may be ignored.
432 * Therefore, let's consider only 3 low-order bits.
433 */
434 reg2 = ((reg2 >> 3) & 0x7) ^ 0x7;
435 /*
436 * Register numbering is ax,cx,dx,bx, sp,bp,si,di, r8..r15.
437 *
438 * Choose scratch reg. Order is important: must not select bx
439 * if we can use si (cmpxchg8b case!)
440 */
441 if (reg != 6 && reg2 != 6) {
442 reg2 = 6;
443 auprobe->defparam.fixups |= UPROBE_FIX_RIP_SI;
444 } else if (reg != 7 && reg2 != 7) {
445 reg2 = 7;
446 auprobe->defparam.fixups |= UPROBE_FIX_RIP_DI;
447 /* TODO (paranoia): force maskmovq to not use di */
448 } else {
449 reg2 = 3;
450 auprobe->defparam.fixups |= UPROBE_FIX_RIP_BX;
451 }
452 /*
453 * Point cursor at the modrm byte. The next 4 bytes are the
454 * displacement. Beyond the displacement, for some instructions,
455 * is the immediate operand.
456 */
457 cursor = auprobe->insn + insn_offset_modrm(insn);
458 /*
459 * Change modrm from "00 reg 101" to "10 reg reg2". Example:
460 * 89 05 disp32 mov %eax,disp32(%rip) becomes
461 * 89 86 disp32 mov %eax,disp32(%rsi)
462 */
463 *cursor = 0x80 | (reg << 3) | reg2;
464 }
465
466 static inline unsigned long *
scratch_reg(struct arch_uprobe * auprobe,struct pt_regs * regs)467 scratch_reg(struct arch_uprobe *auprobe, struct pt_regs *regs)
468 {
469 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_SI)
470 return ®s->si;
471 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_DI)
472 return ®s->di;
473 return ®s->bx;
474 }
475
476 /*
477 * If we're emulating a rip-relative instruction, save the contents
478 * of the scratch register and store the target address in that register.
479 */
riprel_pre_xol(struct arch_uprobe * auprobe,struct pt_regs * regs)480 static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
481 {
482 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) {
483 struct uprobe_task *utask = current->utask;
484 unsigned long *sr = scratch_reg(auprobe, regs);
485
486 utask->autask.saved_scratch_register = *sr;
487 *sr = utask->vaddr + auprobe->defparam.ilen;
488 }
489 }
490
riprel_post_xol(struct arch_uprobe * auprobe,struct pt_regs * regs)491 static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
492 {
493 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) {
494 struct uprobe_task *utask = current->utask;
495 unsigned long *sr = scratch_reg(auprobe, regs);
496
497 *sr = utask->autask.saved_scratch_register;
498 }
499 }
500 #else /* 32-bit: */
501 /*
502 * No RIP-relative addressing on 32-bit
503 */
riprel_analyze(struct arch_uprobe * auprobe,struct insn * insn)504 static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn)
505 {
506 }
riprel_pre_xol(struct arch_uprobe * auprobe,struct pt_regs * regs)507 static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
508 {
509 }
riprel_post_xol(struct arch_uprobe * auprobe,struct pt_regs * regs)510 static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
511 {
512 }
513 #endif /* CONFIG_X86_64 */
514
515 struct uprobe_xol_ops {
516 bool (*emulate)(struct arch_uprobe *, struct pt_regs *);
517 int (*pre_xol)(struct arch_uprobe *, struct pt_regs *);
518 int (*post_xol)(struct arch_uprobe *, struct pt_regs *);
519 void (*abort)(struct arch_uprobe *, struct pt_regs *);
520 };
521
sizeof_long(struct pt_regs * regs)522 static inline int sizeof_long(struct pt_regs *regs)
523 {
524 /*
525 * Check registers for mode as in_xxx_syscall() does not apply here.
526 */
527 return user_64bit_mode(regs) ? 8 : 4;
528 }
529
default_pre_xol_op(struct arch_uprobe * auprobe,struct pt_regs * regs)530 static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
531 {
532 riprel_pre_xol(auprobe, regs);
533 return 0;
534 }
535
push_ret_address(struct pt_regs * regs,unsigned long ip)536 static int push_ret_address(struct pt_regs *regs, unsigned long ip)
537 {
538 unsigned long new_sp = regs->sp - sizeof_long(regs);
539
540 if (copy_to_user((void __user *)new_sp, &ip, sizeof_long(regs)))
541 return -EFAULT;
542
543 regs->sp = new_sp;
544 return 0;
545 }
546
547 /*
548 * We have to fix things up as follows:
549 *
550 * Typically, the new ip is relative to the copied instruction. We need
551 * to make it relative to the original instruction (FIX_IP). Exceptions
552 * are return instructions and absolute or indirect jump or call instructions.
553 *
554 * If the single-stepped instruction was a call, the return address that
555 * is atop the stack is the address following the copied instruction. We
556 * need to make it the address following the original instruction (FIX_CALL).
557 *
558 * If the original instruction was a rip-relative instruction such as
559 * "movl %edx,0xnnnn(%rip)", we have instead executed an equivalent
560 * instruction using a scratch register -- e.g., "movl %edx,0xnnnn(%rsi)".
561 * We need to restore the contents of the scratch register
562 * (FIX_RIP_reg).
563 */
default_post_xol_op(struct arch_uprobe * auprobe,struct pt_regs * regs)564 static int default_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
565 {
566 struct uprobe_task *utask = current->utask;
567
568 riprel_post_xol(auprobe, regs);
569 if (auprobe->defparam.fixups & UPROBE_FIX_IP) {
570 long correction = utask->vaddr - utask->xol_vaddr;
571 regs->ip += correction;
572 } else if (auprobe->defparam.fixups & UPROBE_FIX_CALL) {
573 regs->sp += sizeof_long(regs); /* Pop incorrect return address */
574 if (push_ret_address(regs, utask->vaddr + auprobe->defparam.ilen))
575 return -ERESTART;
576 }
577 /* popf; tell the caller to not touch TF */
578 if (auprobe->defparam.fixups & UPROBE_FIX_SETF)
579 utask->autask.saved_tf = true;
580
581 return 0;
582 }
583
default_abort_op(struct arch_uprobe * auprobe,struct pt_regs * regs)584 static void default_abort_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
585 {
586 riprel_post_xol(auprobe, regs);
587 }
588
589 static struct uprobe_xol_ops default_xol_ops = {
590 .pre_xol = default_pre_xol_op,
591 .post_xol = default_post_xol_op,
592 .abort = default_abort_op,
593 };
594
branch_is_call(struct arch_uprobe * auprobe)595 static bool branch_is_call(struct arch_uprobe *auprobe)
596 {
597 return auprobe->branch.opc1 == 0xe8;
598 }
599
600 #define CASE_COND \
601 COND(70, 71, XF(OF)) \
602 COND(72, 73, XF(CF)) \
603 COND(74, 75, XF(ZF)) \
604 COND(78, 79, XF(SF)) \
605 COND(7a, 7b, XF(PF)) \
606 COND(76, 77, XF(CF) || XF(ZF)) \
607 COND(7c, 7d, XF(SF) != XF(OF)) \
608 COND(7e, 7f, XF(ZF) || XF(SF) != XF(OF))
609
610 #define COND(op_y, op_n, expr) \
611 case 0x ## op_y: DO((expr) != 0) \
612 case 0x ## op_n: DO((expr) == 0)
613
614 #define XF(xf) (!!(flags & X86_EFLAGS_ ## xf))
615
is_cond_jmp_opcode(u8 opcode)616 static bool is_cond_jmp_opcode(u8 opcode)
617 {
618 switch (opcode) {
619 #define DO(expr) \
620 return true;
621 CASE_COND
622 #undef DO
623
624 default:
625 return false;
626 }
627 }
628
check_jmp_cond(struct arch_uprobe * auprobe,struct pt_regs * regs)629 static bool check_jmp_cond(struct arch_uprobe *auprobe, struct pt_regs *regs)
630 {
631 unsigned long flags = regs->flags;
632
633 switch (auprobe->branch.opc1) {
634 #define DO(expr) \
635 return expr;
636 CASE_COND
637 #undef DO
638
639 default: /* not a conditional jmp */
640 return true;
641 }
642 }
643
644 #undef XF
645 #undef COND
646 #undef CASE_COND
647
branch_emulate_op(struct arch_uprobe * auprobe,struct pt_regs * regs)648 static bool branch_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
649 {
650 unsigned long new_ip = regs->ip += auprobe->branch.ilen;
651 unsigned long offs = (long)auprobe->branch.offs;
652
653 if (branch_is_call(auprobe)) {
654 /*
655 * If it fails we execute this (mangled, see the comment in
656 * branch_clear_offset) insn out-of-line. In the likely case
657 * this should trigger the trap, and the probed application
658 * should die or restart the same insn after it handles the
659 * signal, arch_uprobe_post_xol() won't be even called.
660 *
661 * But there is corner case, see the comment in ->post_xol().
662 */
663 if (push_ret_address(regs, new_ip))
664 return false;
665 } else if (!check_jmp_cond(auprobe, regs)) {
666 offs = 0;
667 }
668
669 regs->ip = new_ip + offs;
670 return true;
671 }
672
branch_post_xol_op(struct arch_uprobe * auprobe,struct pt_regs * regs)673 static int branch_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
674 {
675 BUG_ON(!branch_is_call(auprobe));
676 /*
677 * We can only get here if branch_emulate_op() failed to push the ret
678 * address _and_ another thread expanded our stack before the (mangled)
679 * "call" insn was executed out-of-line. Just restore ->sp and restart.
680 * We could also restore ->ip and try to call branch_emulate_op() again.
681 */
682 regs->sp += sizeof_long(regs);
683 return -ERESTART;
684 }
685
branch_clear_offset(struct arch_uprobe * auprobe,struct insn * insn)686 static void branch_clear_offset(struct arch_uprobe *auprobe, struct insn *insn)
687 {
688 /*
689 * Turn this insn into "call 1f; 1:", this is what we will execute
690 * out-of-line if ->emulate() fails. We only need this to generate
691 * a trap, so that the probed task receives the correct signal with
692 * the properly filled siginfo.
693 *
694 * But see the comment in ->post_xol(), in the unlikely case it can
695 * succeed. So we need to ensure that the new ->ip can not fall into
696 * the non-canonical area and trigger #GP.
697 *
698 * We could turn it into (say) "pushf", but then we would need to
699 * divorce ->insn[] and ->ixol[]. We need to preserve the 1st byte
700 * of ->insn[] for set_orig_insn().
701 */
702 memset(auprobe->insn + insn_offset_immediate(insn),
703 0, insn->immediate.nbytes);
704 }
705
706 static struct uprobe_xol_ops branch_xol_ops = {
707 .emulate = branch_emulate_op,
708 .post_xol = branch_post_xol_op,
709 };
710
711 /* Returns -ENOSYS if branch_xol_ops doesn't handle this insn */
branch_setup_xol_ops(struct arch_uprobe * auprobe,struct insn * insn)712 static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn)
713 {
714 u8 opc1 = OPCODE1(insn);
715 insn_byte_t p;
716 int i;
717
718 switch (opc1) {
719 case 0xeb: /* jmp 8 */
720 case 0xe9: /* jmp 32 */
721 case 0x90: /* prefix* + nop; same as jmp with .offs = 0 */
722 break;
723
724 case 0xe8: /* call relative */
725 branch_clear_offset(auprobe, insn);
726 break;
727
728 case 0x0f:
729 if (insn->opcode.nbytes != 2)
730 return -ENOSYS;
731 /*
732 * If it is a "near" conditional jmp, OPCODE2() - 0x10 matches
733 * OPCODE1() of the "short" jmp which checks the same condition.
734 */
735 opc1 = OPCODE2(insn) - 0x10;
736 default:
737 if (!is_cond_jmp_opcode(opc1))
738 return -ENOSYS;
739 }
740
741 /*
742 * 16-bit overrides such as CALLW (66 e8 nn nn) are not supported.
743 * Intel and AMD behavior differ in 64-bit mode: Intel ignores 66 prefix.
744 * No one uses these insns, reject any branch insns with such prefix.
745 */
746 for_each_insn_prefix(insn, i, p) {
747 if (p == 0x66)
748 return -ENOTSUPP;
749 }
750
751 auprobe->branch.opc1 = opc1;
752 auprobe->branch.ilen = insn->length;
753 auprobe->branch.offs = insn->immediate.value;
754
755 auprobe->ops = &branch_xol_ops;
756 return 0;
757 }
758
759 /**
760 * arch_uprobe_analyze_insn - instruction analysis including validity and fixups.
761 * @mm: the probed address space.
762 * @arch_uprobe: the probepoint information.
763 * @addr: virtual address at which to install the probepoint
764 * Return 0 on success or a -ve number on error.
765 */
arch_uprobe_analyze_insn(struct arch_uprobe * auprobe,struct mm_struct * mm,unsigned long addr)766 int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr)
767 {
768 struct insn insn;
769 u8 fix_ip_or_call = UPROBE_FIX_IP;
770 int ret;
771
772 ret = uprobe_init_insn(auprobe, &insn, is_64bit_mm(mm));
773 if (ret)
774 return ret;
775
776 ret = branch_setup_xol_ops(auprobe, &insn);
777 if (ret != -ENOSYS)
778 return ret;
779
780 /*
781 * Figure out which fixups default_post_xol_op() will need to perform,
782 * and annotate defparam->fixups accordingly.
783 */
784 switch (OPCODE1(&insn)) {
785 case 0x9d: /* popf */
786 auprobe->defparam.fixups |= UPROBE_FIX_SETF;
787 break;
788 case 0xc3: /* ret or lret -- ip is correct */
789 case 0xcb:
790 case 0xc2:
791 case 0xca:
792 case 0xea: /* jmp absolute -- ip is correct */
793 fix_ip_or_call = 0;
794 break;
795 case 0x9a: /* call absolute - Fix return addr, not ip */
796 fix_ip_or_call = UPROBE_FIX_CALL;
797 break;
798 case 0xff:
799 switch (MODRM_REG(&insn)) {
800 case 2: case 3: /* call or lcall, indirect */
801 fix_ip_or_call = UPROBE_FIX_CALL;
802 break;
803 case 4: case 5: /* jmp or ljmp, indirect */
804 fix_ip_or_call = 0;
805 break;
806 }
807 /* fall through */
808 default:
809 riprel_analyze(auprobe, &insn);
810 }
811
812 auprobe->defparam.ilen = insn.length;
813 auprobe->defparam.fixups |= fix_ip_or_call;
814
815 auprobe->ops = &default_xol_ops;
816 return 0;
817 }
818
819 /*
820 * arch_uprobe_pre_xol - prepare to execute out of line.
821 * @auprobe: the probepoint information.
822 * @regs: reflects the saved user state of current task.
823 */
arch_uprobe_pre_xol(struct arch_uprobe * auprobe,struct pt_regs * regs)824 int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
825 {
826 struct uprobe_task *utask = current->utask;
827
828 if (auprobe->ops->pre_xol) {
829 int err = auprobe->ops->pre_xol(auprobe, regs);
830 if (err)
831 return err;
832 }
833
834 regs->ip = utask->xol_vaddr;
835 utask->autask.saved_trap_nr = current->thread.trap_nr;
836 current->thread.trap_nr = UPROBE_TRAP_NR;
837
838 utask->autask.saved_tf = !!(regs->flags & X86_EFLAGS_TF);
839 regs->flags |= X86_EFLAGS_TF;
840 if (test_tsk_thread_flag(current, TIF_BLOCKSTEP))
841 set_task_blockstep(current, false);
842
843 return 0;
844 }
845
846 /*
847 * If xol insn itself traps and generates a signal(Say,
848 * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped
849 * instruction jumps back to its own address. It is assumed that anything
850 * like do_page_fault/do_trap/etc sets thread.trap_nr != -1.
851 *
852 * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr,
853 * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to
854 * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol().
855 */
arch_uprobe_xol_was_trapped(struct task_struct * t)856 bool arch_uprobe_xol_was_trapped(struct task_struct *t)
857 {
858 if (t->thread.trap_nr != UPROBE_TRAP_NR)
859 return true;
860
861 return false;
862 }
863
864 /*
865 * Called after single-stepping. To avoid the SMP problems that can
866 * occur when we temporarily put back the original opcode to
867 * single-step, we single-stepped a copy of the instruction.
868 *
869 * This function prepares to resume execution after the single-step.
870 */
arch_uprobe_post_xol(struct arch_uprobe * auprobe,struct pt_regs * regs)871 int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
872 {
873 struct uprobe_task *utask = current->utask;
874 bool send_sigtrap = utask->autask.saved_tf;
875 int err = 0;
876
877 WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR);
878 current->thread.trap_nr = utask->autask.saved_trap_nr;
879
880 if (auprobe->ops->post_xol) {
881 err = auprobe->ops->post_xol(auprobe, regs);
882 if (err) {
883 /*
884 * Restore ->ip for restart or post mortem analysis.
885 * ->post_xol() must not return -ERESTART unless this
886 * is really possible.
887 */
888 regs->ip = utask->vaddr;
889 if (err == -ERESTART)
890 err = 0;
891 send_sigtrap = false;
892 }
893 }
894 /*
895 * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP
896 * so we can get an extra SIGTRAP if we do not clear TF. We need
897 * to examine the opcode to make it right.
898 */
899 if (send_sigtrap)
900 send_sig(SIGTRAP, current, 0);
901
902 if (!utask->autask.saved_tf)
903 regs->flags &= ~X86_EFLAGS_TF;
904
905 return err;
906 }
907
908 /* callback routine for handling exceptions. */
arch_uprobe_exception_notify(struct notifier_block * self,unsigned long val,void * data)909 int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data)
910 {
911 struct die_args *args = data;
912 struct pt_regs *regs = args->regs;
913 int ret = NOTIFY_DONE;
914
915 /* We are only interested in userspace traps */
916 if (regs && !user_mode(regs))
917 return NOTIFY_DONE;
918
919 switch (val) {
920 case DIE_INT3:
921 if (uprobe_pre_sstep_notifier(regs))
922 ret = NOTIFY_STOP;
923
924 break;
925
926 case DIE_DEBUG:
927 if (uprobe_post_sstep_notifier(regs))
928 ret = NOTIFY_STOP;
929
930 default:
931 break;
932 }
933
934 return ret;
935 }
936
937 /*
938 * This function gets called when XOL instruction either gets trapped or
939 * the thread has a fatal signal. Reset the instruction pointer to its
940 * probed address for the potential restart or for post mortem analysis.
941 */
arch_uprobe_abort_xol(struct arch_uprobe * auprobe,struct pt_regs * regs)942 void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
943 {
944 struct uprobe_task *utask = current->utask;
945
946 if (auprobe->ops->abort)
947 auprobe->ops->abort(auprobe, regs);
948
949 current->thread.trap_nr = utask->autask.saved_trap_nr;
950 regs->ip = utask->vaddr;
951 /* clear TF if it was set by us in arch_uprobe_pre_xol() */
952 if (!utask->autask.saved_tf)
953 regs->flags &= ~X86_EFLAGS_TF;
954 }
955
__skip_sstep(struct arch_uprobe * auprobe,struct pt_regs * regs)956 static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
957 {
958 if (auprobe->ops->emulate)
959 return auprobe->ops->emulate(auprobe, regs);
960 return false;
961 }
962
arch_uprobe_skip_sstep(struct arch_uprobe * auprobe,struct pt_regs * regs)963 bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
964 {
965 bool ret = __skip_sstep(auprobe, regs);
966 if (ret && (regs->flags & X86_EFLAGS_TF))
967 send_sig(SIGTRAP, current, 0);
968 return ret;
969 }
970
971 unsigned long
arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr,struct pt_regs * regs)972 arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs)
973 {
974 int rasize = sizeof_long(regs), nleft;
975 unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */
976
977 if (copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize))
978 return -1;
979
980 /* check whether address has been already hijacked */
981 if (orig_ret_vaddr == trampoline_vaddr)
982 return orig_ret_vaddr;
983
984 nleft = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize);
985 if (likely(!nleft))
986 return orig_ret_vaddr;
987
988 if (nleft != rasize) {
989 pr_err("uprobe: return address clobbered: pid=%d, %%sp=%#lx, "
990 "%%ip=%#lx\n", current->pid, regs->sp, regs->ip);
991
992 force_sig(SIGSEGV, current);
993 }
994
995 return -1;
996 }
997
arch_uretprobe_is_alive(struct return_instance * ret,enum rp_check ctx,struct pt_regs * regs)998 bool arch_uretprobe_is_alive(struct return_instance *ret, enum rp_check ctx,
999 struct pt_regs *regs)
1000 {
1001 if (ctx == RP_CHECK_CALL) /* sp was just decremented by "call" insn */
1002 return regs->sp < ret->stack;
1003 else
1004 return regs->sp <= ret->stack;
1005 }
1006