1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #include <linux/phy.h>
118 #include <linux/mdio.h>
119 #include <linux/clk.h>
120 #include <linux/bitrev.h>
121 #include <linux/crc32.h>
122
123 #include "xgbe.h"
124 #include "xgbe-common.h"
125
xgbe_usec_to_riwt(struct xgbe_prv_data * pdata,unsigned int usec)126 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
127 unsigned int usec)
128 {
129 unsigned long rate;
130 unsigned int ret;
131
132 DBGPR("-->xgbe_usec_to_riwt\n");
133
134 rate = pdata->sysclk_rate;
135
136 /*
137 * Convert the input usec value to the watchdog timer value. Each
138 * watchdog timer value is equivalent to 256 clock cycles.
139 * Calculate the required value as:
140 * ( usec * ( system_clock_mhz / 10^6 ) / 256
141 */
142 ret = (usec * (rate / 1000000)) / 256;
143
144 DBGPR("<--xgbe_usec_to_riwt\n");
145
146 return ret;
147 }
148
xgbe_riwt_to_usec(struct xgbe_prv_data * pdata,unsigned int riwt)149 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
150 unsigned int riwt)
151 {
152 unsigned long rate;
153 unsigned int ret;
154
155 DBGPR("-->xgbe_riwt_to_usec\n");
156
157 rate = pdata->sysclk_rate;
158
159 /*
160 * Convert the input watchdog timer value to the usec value. Each
161 * watchdog timer value is equivalent to 256 clock cycles.
162 * Calculate the required value as:
163 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 )
164 */
165 ret = (riwt * 256) / (rate / 1000000);
166
167 DBGPR("<--xgbe_riwt_to_usec\n");
168
169 return ret;
170 }
171
xgbe_config_pblx8(struct xgbe_prv_data * pdata)172 static int xgbe_config_pblx8(struct xgbe_prv_data *pdata)
173 {
174 struct xgbe_channel *channel;
175 unsigned int i;
176
177 channel = pdata->channel;
178 for (i = 0; i < pdata->channel_count; i++, channel++)
179 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8,
180 pdata->pblx8);
181
182 return 0;
183 }
184
xgbe_get_tx_pbl_val(struct xgbe_prv_data * pdata)185 static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata)
186 {
187 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL);
188 }
189
xgbe_config_tx_pbl_val(struct xgbe_prv_data * pdata)190 static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata)
191 {
192 struct xgbe_channel *channel;
193 unsigned int i;
194
195 channel = pdata->channel;
196 for (i = 0; i < pdata->channel_count; i++, channel++) {
197 if (!channel->tx_ring)
198 break;
199
200 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL,
201 pdata->tx_pbl);
202 }
203
204 return 0;
205 }
206
xgbe_get_rx_pbl_val(struct xgbe_prv_data * pdata)207 static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata)
208 {
209 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL);
210 }
211
xgbe_config_rx_pbl_val(struct xgbe_prv_data * pdata)212 static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata)
213 {
214 struct xgbe_channel *channel;
215 unsigned int i;
216
217 channel = pdata->channel;
218 for (i = 0; i < pdata->channel_count; i++, channel++) {
219 if (!channel->rx_ring)
220 break;
221
222 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL,
223 pdata->rx_pbl);
224 }
225
226 return 0;
227 }
228
xgbe_config_osp_mode(struct xgbe_prv_data * pdata)229 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata)
230 {
231 struct xgbe_channel *channel;
232 unsigned int i;
233
234 channel = pdata->channel;
235 for (i = 0; i < pdata->channel_count; i++, channel++) {
236 if (!channel->tx_ring)
237 break;
238
239 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP,
240 pdata->tx_osp_mode);
241 }
242
243 return 0;
244 }
245
xgbe_config_rsf_mode(struct xgbe_prv_data * pdata,unsigned int val)246 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
247 {
248 unsigned int i;
249
250 for (i = 0; i < pdata->rx_q_count; i++)
251 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
252
253 return 0;
254 }
255
xgbe_config_tsf_mode(struct xgbe_prv_data * pdata,unsigned int val)256 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
257 {
258 unsigned int i;
259
260 for (i = 0; i < pdata->tx_q_count; i++)
261 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
262
263 return 0;
264 }
265
xgbe_config_rx_threshold(struct xgbe_prv_data * pdata,unsigned int val)266 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata,
267 unsigned int val)
268 {
269 unsigned int i;
270
271 for (i = 0; i < pdata->rx_q_count; i++)
272 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
273
274 return 0;
275 }
276
xgbe_config_tx_threshold(struct xgbe_prv_data * pdata,unsigned int val)277 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata,
278 unsigned int val)
279 {
280 unsigned int i;
281
282 for (i = 0; i < pdata->tx_q_count; i++)
283 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
284
285 return 0;
286 }
287
xgbe_config_rx_coalesce(struct xgbe_prv_data * pdata)288 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)
289 {
290 struct xgbe_channel *channel;
291 unsigned int i;
292
293 channel = pdata->channel;
294 for (i = 0; i < pdata->channel_count; i++, channel++) {
295 if (!channel->rx_ring)
296 break;
297
298 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT,
299 pdata->rx_riwt);
300 }
301
302 return 0;
303 }
304
xgbe_config_tx_coalesce(struct xgbe_prv_data * pdata)305 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata)
306 {
307 return 0;
308 }
309
xgbe_config_rx_buffer_size(struct xgbe_prv_data * pdata)310 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)
311 {
312 struct xgbe_channel *channel;
313 unsigned int i;
314
315 channel = pdata->channel;
316 for (i = 0; i < pdata->channel_count; i++, channel++) {
317 if (!channel->rx_ring)
318 break;
319
320 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ,
321 pdata->rx_buf_size);
322 }
323 }
324
xgbe_config_tso_mode(struct xgbe_prv_data * pdata)325 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata)
326 {
327 struct xgbe_channel *channel;
328 unsigned int i;
329
330 channel = pdata->channel;
331 for (i = 0; i < pdata->channel_count; i++, channel++) {
332 if (!channel->tx_ring)
333 break;
334
335 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1);
336 }
337 }
338
xgbe_config_sph_mode(struct xgbe_prv_data * pdata)339 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata)
340 {
341 struct xgbe_channel *channel;
342 unsigned int i;
343
344 channel = pdata->channel;
345 for (i = 0; i < pdata->channel_count; i++, channel++) {
346 if (!channel->rx_ring)
347 break;
348
349 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, SPH, 1);
350 }
351
352 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE);
353 }
354
xgbe_write_rss_reg(struct xgbe_prv_data * pdata,unsigned int type,unsigned int index,unsigned int val)355 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type,
356 unsigned int index, unsigned int val)
357 {
358 unsigned int wait;
359 int ret = 0;
360
361 mutex_lock(&pdata->rss_mutex);
362
363 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) {
364 ret = -EBUSY;
365 goto unlock;
366 }
367
368 XGMAC_IOWRITE(pdata, MAC_RSSDR, val);
369
370 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index);
371 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type);
372 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0);
373 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1);
374
375 wait = 1000;
376 while (wait--) {
377 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB))
378 goto unlock;
379
380 usleep_range(1000, 1500);
381 }
382
383 ret = -EBUSY;
384
385 unlock:
386 mutex_unlock(&pdata->rss_mutex);
387
388 return ret;
389 }
390
xgbe_write_rss_hash_key(struct xgbe_prv_data * pdata)391 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata)
392 {
393 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32);
394 unsigned int *key = (unsigned int *)&pdata->rss_key;
395 int ret;
396
397 while (key_regs--) {
398 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE,
399 key_regs, *key++);
400 if (ret)
401 return ret;
402 }
403
404 return 0;
405 }
406
xgbe_write_rss_lookup_table(struct xgbe_prv_data * pdata)407 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata)
408 {
409 unsigned int i;
410 int ret;
411
412 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
413 ret = xgbe_write_rss_reg(pdata,
414 XGBE_RSS_LOOKUP_TABLE_TYPE, i,
415 pdata->rss_table[i]);
416 if (ret)
417 return ret;
418 }
419
420 return 0;
421 }
422
xgbe_set_rss_hash_key(struct xgbe_prv_data * pdata,const u8 * key)423 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key)
424 {
425 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key));
426
427 return xgbe_write_rss_hash_key(pdata);
428 }
429
xgbe_set_rss_lookup_table(struct xgbe_prv_data * pdata,const u32 * table)430 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata,
431 const u32 *table)
432 {
433 unsigned int i;
434
435 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++)
436 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]);
437
438 return xgbe_write_rss_lookup_table(pdata);
439 }
440
xgbe_enable_rss(struct xgbe_prv_data * pdata)441 static int xgbe_enable_rss(struct xgbe_prv_data *pdata)
442 {
443 int ret;
444
445 if (!pdata->hw_feat.rss)
446 return -EOPNOTSUPP;
447
448 /* Program the hash key */
449 ret = xgbe_write_rss_hash_key(pdata);
450 if (ret)
451 return ret;
452
453 /* Program the lookup table */
454 ret = xgbe_write_rss_lookup_table(pdata);
455 if (ret)
456 return ret;
457
458 /* Set the RSS options */
459 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
460
461 /* Enable RSS */
462 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1);
463
464 return 0;
465 }
466
xgbe_disable_rss(struct xgbe_prv_data * pdata)467 static int xgbe_disable_rss(struct xgbe_prv_data *pdata)
468 {
469 if (!pdata->hw_feat.rss)
470 return -EOPNOTSUPP;
471
472 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0);
473
474 return 0;
475 }
476
xgbe_config_rss(struct xgbe_prv_data * pdata)477 static void xgbe_config_rss(struct xgbe_prv_data *pdata)
478 {
479 int ret;
480
481 if (!pdata->hw_feat.rss)
482 return;
483
484 if (pdata->netdev->features & NETIF_F_RXHASH)
485 ret = xgbe_enable_rss(pdata);
486 else
487 ret = xgbe_disable_rss(pdata);
488
489 if (ret)
490 netdev_err(pdata->netdev,
491 "error configuring RSS, RSS disabled\n");
492 }
493
xgbe_disable_tx_flow_control(struct xgbe_prv_data * pdata)494 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
495 {
496 unsigned int max_q_count, q_count;
497 unsigned int reg, reg_val;
498 unsigned int i;
499
500 /* Clear MTL flow control */
501 for (i = 0; i < pdata->rx_q_count; i++)
502 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
503
504 /* Clear MAC flow control */
505 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
506 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
507 reg = MAC_Q0TFCR;
508 for (i = 0; i < q_count; i++) {
509 reg_val = XGMAC_IOREAD(pdata, reg);
510 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);
511 XGMAC_IOWRITE(pdata, reg, reg_val);
512
513 reg += MAC_QTFCR_INC;
514 }
515
516 return 0;
517 }
518
xgbe_enable_tx_flow_control(struct xgbe_prv_data * pdata)519 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
520 {
521 unsigned int max_q_count, q_count;
522 unsigned int reg, reg_val;
523 unsigned int i;
524
525 /* Set MTL flow control */
526 for (i = 0; i < pdata->rx_q_count; i++)
527 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1);
528
529 /* Set MAC flow control */
530 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
531 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
532 reg = MAC_Q0TFCR;
533 for (i = 0; i < q_count; i++) {
534 reg_val = XGMAC_IOREAD(pdata, reg);
535
536 /* Enable transmit flow control */
537 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);
538 /* Set pause time */
539 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);
540
541 XGMAC_IOWRITE(pdata, reg, reg_val);
542
543 reg += MAC_QTFCR_INC;
544 }
545
546 return 0;
547 }
548
xgbe_disable_rx_flow_control(struct xgbe_prv_data * pdata)549 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata)
550 {
551 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0);
552
553 return 0;
554 }
555
xgbe_enable_rx_flow_control(struct xgbe_prv_data * pdata)556 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
557 {
558 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1);
559
560 return 0;
561 }
562
xgbe_config_tx_flow_control(struct xgbe_prv_data * pdata)563 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
564 {
565 struct ieee_pfc *pfc = pdata->pfc;
566
567 if (pdata->tx_pause || (pfc && pfc->pfc_en))
568 xgbe_enable_tx_flow_control(pdata);
569 else
570 xgbe_disable_tx_flow_control(pdata);
571
572 return 0;
573 }
574
xgbe_config_rx_flow_control(struct xgbe_prv_data * pdata)575 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
576 {
577 struct ieee_pfc *pfc = pdata->pfc;
578
579 if (pdata->rx_pause || (pfc && pfc->pfc_en))
580 xgbe_enable_rx_flow_control(pdata);
581 else
582 xgbe_disable_rx_flow_control(pdata);
583
584 return 0;
585 }
586
xgbe_config_flow_control(struct xgbe_prv_data * pdata)587 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata)
588 {
589 struct ieee_pfc *pfc = pdata->pfc;
590
591 xgbe_config_tx_flow_control(pdata);
592 xgbe_config_rx_flow_control(pdata);
593
594 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE,
595 (pfc && pfc->pfc_en) ? 1 : 0);
596 }
597
xgbe_enable_dma_interrupts(struct xgbe_prv_data * pdata)598 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
599 {
600 struct xgbe_channel *channel;
601 unsigned int dma_ch_isr, dma_ch_ier;
602 unsigned int i;
603
604 channel = pdata->channel;
605 for (i = 0; i < pdata->channel_count; i++, channel++) {
606 /* Clear all the interrupts which are set */
607 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
608 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
609
610 /* Clear all interrupt enable bits */
611 dma_ch_ier = 0;
612
613 /* Enable following interrupts
614 * NIE - Normal Interrupt Summary Enable
615 * AIE - Abnormal Interrupt Summary Enable
616 * FBEE - Fatal Bus Error Enable
617 */
618 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1);
619 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1);
620 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
621
622 if (channel->tx_ring) {
623 /* Enable the following Tx interrupts
624 * TIE - Transmit Interrupt Enable (unless using
625 * per channel interrupts)
626 */
627 if (!pdata->per_channel_irq)
628 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
629 }
630 if (channel->rx_ring) {
631 /* Enable following Rx interrupts
632 * RBUE - Receive Buffer Unavailable Enable
633 * RIE - Receive Interrupt Enable (unless using
634 * per channel interrupts)
635 */
636 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
637 if (!pdata->per_channel_irq)
638 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
639 }
640
641 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
642 }
643 }
644
xgbe_enable_mtl_interrupts(struct xgbe_prv_data * pdata)645 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
646 {
647 unsigned int mtl_q_isr;
648 unsigned int q_count, i;
649
650 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
651 for (i = 0; i < q_count; i++) {
652 /* Clear all the interrupts which are set */
653 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR);
654 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr);
655
656 /* No MTL interrupts to be enabled */
657 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0);
658 }
659 }
660
xgbe_enable_mac_interrupts(struct xgbe_prv_data * pdata)661 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
662 {
663 unsigned int mac_ier = 0;
664
665 /* Enable Timestamp interrupt */
666 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1);
667
668 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
669
670 /* Enable all counter interrupts */
671 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff);
672 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
673 }
674
xgbe_set_gmii_speed(struct xgbe_prv_data * pdata)675 static int xgbe_set_gmii_speed(struct xgbe_prv_data *pdata)
676 {
677 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x3)
678 return 0;
679
680 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3);
681
682 return 0;
683 }
684
xgbe_set_gmii_2500_speed(struct xgbe_prv_data * pdata)685 static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data *pdata)
686 {
687 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x2)
688 return 0;
689
690 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2);
691
692 return 0;
693 }
694
xgbe_set_xgmii_speed(struct xgbe_prv_data * pdata)695 static int xgbe_set_xgmii_speed(struct xgbe_prv_data *pdata)
696 {
697 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0)
698 return 0;
699
700 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0);
701
702 return 0;
703 }
704
xgbe_set_promiscuous_mode(struct xgbe_prv_data * pdata,unsigned int enable)705 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata,
706 unsigned int enable)
707 {
708 unsigned int val = enable ? 1 : 0;
709
710 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val)
711 return 0;
712
713 netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n",
714 enable ? "entering" : "leaving");
715 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val);
716
717 return 0;
718 }
719
xgbe_set_all_multicast_mode(struct xgbe_prv_data * pdata,unsigned int enable)720 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata,
721 unsigned int enable)
722 {
723 unsigned int val = enable ? 1 : 0;
724
725 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val)
726 return 0;
727
728 netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n",
729 enable ? "entering" : "leaving");
730 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val);
731
732 return 0;
733 }
734
xgbe_set_mac_reg(struct xgbe_prv_data * pdata,struct netdev_hw_addr * ha,unsigned int * mac_reg)735 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata,
736 struct netdev_hw_addr *ha, unsigned int *mac_reg)
737 {
738 unsigned int mac_addr_hi, mac_addr_lo;
739 u8 *mac_addr;
740
741 mac_addr_lo = 0;
742 mac_addr_hi = 0;
743
744 if (ha) {
745 mac_addr = (u8 *)&mac_addr_lo;
746 mac_addr[0] = ha->addr[0];
747 mac_addr[1] = ha->addr[1];
748 mac_addr[2] = ha->addr[2];
749 mac_addr[3] = ha->addr[3];
750 mac_addr = (u8 *)&mac_addr_hi;
751 mac_addr[0] = ha->addr[4];
752 mac_addr[1] = ha->addr[5];
753
754 netif_dbg(pdata, drv, pdata->netdev,
755 "adding mac address %pM at %#x\n",
756 ha->addr, *mac_reg);
757
758 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
759 }
760
761 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi);
762 *mac_reg += MAC_MACA_INC;
763 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo);
764 *mac_reg += MAC_MACA_INC;
765 }
766
xgbe_set_mac_addn_addrs(struct xgbe_prv_data * pdata)767 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata)
768 {
769 struct net_device *netdev = pdata->netdev;
770 struct netdev_hw_addr *ha;
771 unsigned int mac_reg;
772 unsigned int addn_macs;
773
774 mac_reg = MAC_MACA1HR;
775 addn_macs = pdata->hw_feat.addn_mac;
776
777 if (netdev_uc_count(netdev) > addn_macs) {
778 xgbe_set_promiscuous_mode(pdata, 1);
779 } else {
780 netdev_for_each_uc_addr(ha, netdev) {
781 xgbe_set_mac_reg(pdata, ha, &mac_reg);
782 addn_macs--;
783 }
784
785 if (netdev_mc_count(netdev) > addn_macs) {
786 xgbe_set_all_multicast_mode(pdata, 1);
787 } else {
788 netdev_for_each_mc_addr(ha, netdev) {
789 xgbe_set_mac_reg(pdata, ha, &mac_reg);
790 addn_macs--;
791 }
792 }
793 }
794
795 /* Clear remaining additional MAC address entries */
796 while (addn_macs--)
797 xgbe_set_mac_reg(pdata, NULL, &mac_reg);
798 }
799
xgbe_set_mac_hash_table(struct xgbe_prv_data * pdata)800 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata)
801 {
802 struct net_device *netdev = pdata->netdev;
803 struct netdev_hw_addr *ha;
804 unsigned int hash_reg;
805 unsigned int hash_table_shift, hash_table_count;
806 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE];
807 u32 crc;
808 unsigned int i;
809
810 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7);
811 hash_table_count = pdata->hw_feat.hash_table_size / 32;
812 memset(hash_table, 0, sizeof(hash_table));
813
814 /* Build the MAC Hash Table register values */
815 netdev_for_each_uc_addr(ha, netdev) {
816 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
817 crc >>= hash_table_shift;
818 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
819 }
820
821 netdev_for_each_mc_addr(ha, netdev) {
822 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
823 crc >>= hash_table_shift;
824 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
825 }
826
827 /* Set the MAC Hash Table registers */
828 hash_reg = MAC_HTR0;
829 for (i = 0; i < hash_table_count; i++) {
830 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]);
831 hash_reg += MAC_HTR_INC;
832 }
833 }
834
xgbe_add_mac_addresses(struct xgbe_prv_data * pdata)835 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata)
836 {
837 if (pdata->hw_feat.hash_table_size)
838 xgbe_set_mac_hash_table(pdata);
839 else
840 xgbe_set_mac_addn_addrs(pdata);
841
842 return 0;
843 }
844
xgbe_set_mac_address(struct xgbe_prv_data * pdata,u8 * addr)845 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr)
846 {
847 unsigned int mac_addr_hi, mac_addr_lo;
848
849 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0);
850 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) |
851 (addr[1] << 8) | (addr[0] << 0);
852
853 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi);
854 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo);
855
856 return 0;
857 }
858
xgbe_config_rx_mode(struct xgbe_prv_data * pdata)859 static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata)
860 {
861 struct net_device *netdev = pdata->netdev;
862 unsigned int pr_mode, am_mode;
863
864 pr_mode = ((netdev->flags & IFF_PROMISC) != 0);
865 am_mode = ((netdev->flags & IFF_ALLMULTI) != 0);
866
867 xgbe_set_promiscuous_mode(pdata, pr_mode);
868 xgbe_set_all_multicast_mode(pdata, am_mode);
869
870 xgbe_add_mac_addresses(pdata);
871
872 return 0;
873 }
874
xgbe_read_mmd_regs(struct xgbe_prv_data * pdata,int prtad,int mmd_reg)875 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
876 int mmd_reg)
877 {
878 unsigned int mmd_address;
879 int mmd_data;
880
881 if (mmd_reg & MII_ADDR_C45)
882 mmd_address = mmd_reg & ~MII_ADDR_C45;
883 else
884 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
885
886 /* The PCS registers are accessed using mmio. The underlying APB3
887 * management interface uses indirect addressing to access the MMD
888 * register sets. This requires accessing of the PCS register in two
889 * phases, an address phase and a data phase.
890 *
891 * The mmio interface is based on 32-bit offsets and values. All
892 * register offsets must therefore be adjusted by left shifting the
893 * offset 2 bits and reading 32 bits of data.
894 */
895 mutex_lock(&pdata->xpcs_mutex);
896 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
897 mmd_data = XPCS_IOREAD(pdata, (mmd_address & 0xff) << 2);
898 mutex_unlock(&pdata->xpcs_mutex);
899
900 return mmd_data;
901 }
902
xgbe_write_mmd_regs(struct xgbe_prv_data * pdata,int prtad,int mmd_reg,int mmd_data)903 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
904 int mmd_reg, int mmd_data)
905 {
906 unsigned int mmd_address;
907
908 if (mmd_reg & MII_ADDR_C45)
909 mmd_address = mmd_reg & ~MII_ADDR_C45;
910 else
911 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
912
913 /* The PCS registers are accessed using mmio. The underlying APB3
914 * management interface uses indirect addressing to access the MMD
915 * register sets. This requires accessing of the PCS register in two
916 * phases, an address phase and a data phase.
917 *
918 * The mmio interface is based on 32-bit offsets and values. All
919 * register offsets must therefore be adjusted by left shifting the
920 * offset 2 bits and reading 32 bits of data.
921 */
922 mutex_lock(&pdata->xpcs_mutex);
923 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
924 XPCS_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data);
925 mutex_unlock(&pdata->xpcs_mutex);
926 }
927
xgbe_tx_complete(struct xgbe_ring_desc * rdesc)928 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc)
929 {
930 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN);
931 }
932
xgbe_disable_rx_csum(struct xgbe_prv_data * pdata)933 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata)
934 {
935 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
936
937 return 0;
938 }
939
xgbe_enable_rx_csum(struct xgbe_prv_data * pdata)940 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata)
941 {
942 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1);
943
944 return 0;
945 }
946
xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data * pdata)947 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
948 {
949 /* Put the VLAN tag in the Rx descriptor */
950 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1);
951
952 /* Don't check the VLAN type */
953 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1);
954
955 /* Check only C-TAG (0x8100) packets */
956 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0);
957
958 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */
959 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0);
960
961 /* Enable VLAN tag stripping */
962 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3);
963
964 return 0;
965 }
966
xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data * pdata)967 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
968 {
969 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0);
970
971 return 0;
972 }
973
xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data * pdata)974 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
975 {
976 /* Enable VLAN filtering */
977 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
978
979 /* Enable VLAN Hash Table filtering */
980 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1);
981
982 /* Disable VLAN tag inverse matching */
983 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0);
984
985 /* Only filter on the lower 12-bits of the VLAN tag */
986 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1);
987
988 /* In order for the VLAN Hash Table filtering to be effective,
989 * the VLAN tag identifier in the VLAN Tag Register must not
990 * be zero. Set the VLAN tag identifier to "1" to enable the
991 * VLAN Hash Table filtering. This implies that a VLAN tag of
992 * 1 will always pass filtering.
993 */
994 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1);
995
996 return 0;
997 }
998
xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data * pdata)999 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
1000 {
1001 /* Disable VLAN filtering */
1002 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
1003
1004 return 0;
1005 }
1006
1007 #ifndef CRCPOLY_LE
1008 #define CRCPOLY_LE 0xedb88320
1009 #endif
xgbe_vid_crc32_le(__le16 vid_le)1010 static u32 xgbe_vid_crc32_le(__le16 vid_le)
1011 {
1012 u32 poly = CRCPOLY_LE;
1013 u32 crc = ~0;
1014 u32 temp = 0;
1015 unsigned char *data = (unsigned char *)&vid_le;
1016 unsigned char data_byte = 0;
1017 int i, bits;
1018
1019 bits = get_bitmask_order(VLAN_VID_MASK);
1020 for (i = 0; i < bits; i++) {
1021 if ((i % 8) == 0)
1022 data_byte = data[i / 8];
1023
1024 temp = ((crc & 1) ^ data_byte) & 1;
1025 crc >>= 1;
1026 data_byte >>= 1;
1027
1028 if (temp)
1029 crc ^= poly;
1030 }
1031
1032 return crc;
1033 }
1034
xgbe_update_vlan_hash_table(struct xgbe_prv_data * pdata)1035 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata)
1036 {
1037 u32 crc;
1038 u16 vid;
1039 __le16 vid_le;
1040 u16 vlan_hash_table = 0;
1041
1042 /* Generate the VLAN Hash Table value */
1043 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) {
1044 /* Get the CRC32 value of the VLAN ID */
1045 vid_le = cpu_to_le16(vid);
1046 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28;
1047
1048 vlan_hash_table |= (1 << crc);
1049 }
1050
1051 /* Set the VLAN Hash Table filtering register */
1052 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table);
1053
1054 return 0;
1055 }
1056
xgbe_tx_desc_reset(struct xgbe_ring_data * rdata)1057 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata)
1058 {
1059 struct xgbe_ring_desc *rdesc = rdata->rdesc;
1060
1061 /* Reset the Tx descriptor
1062 * Set buffer 1 (lo) address to zero
1063 * Set buffer 1 (hi) address to zero
1064 * Reset all other control bits (IC, TTSE, B2L & B1L)
1065 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc)
1066 */
1067 rdesc->desc0 = 0;
1068 rdesc->desc1 = 0;
1069 rdesc->desc2 = 0;
1070 rdesc->desc3 = 0;
1071
1072 /* Make sure ownership is written to the descriptor */
1073 dma_wmb();
1074 }
1075
xgbe_tx_desc_init(struct xgbe_channel * channel)1076 static void xgbe_tx_desc_init(struct xgbe_channel *channel)
1077 {
1078 struct xgbe_ring *ring = channel->tx_ring;
1079 struct xgbe_ring_data *rdata;
1080 int i;
1081 int start_index = ring->cur;
1082
1083 DBGPR("-->tx_desc_init\n");
1084
1085 /* Initialze all descriptors */
1086 for (i = 0; i < ring->rdesc_count; i++) {
1087 rdata = XGBE_GET_DESC_DATA(ring, i);
1088
1089 /* Initialize Tx descriptor */
1090 xgbe_tx_desc_reset(rdata);
1091 }
1092
1093 /* Update the total number of Tx descriptors */
1094 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
1095
1096 /* Update the starting address of descriptor ring */
1097 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1098 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI,
1099 upper_32_bits(rdata->rdesc_dma));
1100 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO,
1101 lower_32_bits(rdata->rdesc_dma));
1102
1103 DBGPR("<--tx_desc_init\n");
1104 }
1105
xgbe_rx_desc_reset(struct xgbe_prv_data * pdata,struct xgbe_ring_data * rdata,unsigned int index)1106 static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata,
1107 struct xgbe_ring_data *rdata, unsigned int index)
1108 {
1109 struct xgbe_ring_desc *rdesc = rdata->rdesc;
1110 unsigned int rx_usecs = pdata->rx_usecs;
1111 unsigned int rx_frames = pdata->rx_frames;
1112 unsigned int inte;
1113 dma_addr_t hdr_dma, buf_dma;
1114
1115 if (!rx_usecs && !rx_frames) {
1116 /* No coalescing, interrupt for every descriptor */
1117 inte = 1;
1118 } else {
1119 /* Set interrupt based on Rx frame coalescing setting */
1120 if (rx_frames && !((index + 1) % rx_frames))
1121 inte = 1;
1122 else
1123 inte = 0;
1124 }
1125
1126 /* Reset the Rx descriptor
1127 * Set buffer 1 (lo) address to header dma address (lo)
1128 * Set buffer 1 (hi) address to header dma address (hi)
1129 * Set buffer 2 (lo) address to buffer dma address (lo)
1130 * Set buffer 2 (hi) address to buffer dma address (hi) and
1131 * set control bits OWN and INTE
1132 */
1133 hdr_dma = rdata->rx.hdr.dma_base + rdata->rx.hdr.dma_off;
1134 buf_dma = rdata->rx.buf.dma_base + rdata->rx.buf.dma_off;
1135 rdesc->desc0 = cpu_to_le32(lower_32_bits(hdr_dma));
1136 rdesc->desc1 = cpu_to_le32(upper_32_bits(hdr_dma));
1137 rdesc->desc2 = cpu_to_le32(lower_32_bits(buf_dma));
1138 rdesc->desc3 = cpu_to_le32(upper_32_bits(buf_dma));
1139
1140 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte);
1141
1142 /* Since the Rx DMA engine is likely running, make sure everything
1143 * is written to the descriptor(s) before setting the OWN bit
1144 * for the descriptor
1145 */
1146 dma_wmb();
1147
1148 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
1149
1150 /* Make sure ownership is written to the descriptor */
1151 dma_wmb();
1152 }
1153
xgbe_rx_desc_init(struct xgbe_channel * channel)1154 static void xgbe_rx_desc_init(struct xgbe_channel *channel)
1155 {
1156 struct xgbe_prv_data *pdata = channel->pdata;
1157 struct xgbe_ring *ring = channel->rx_ring;
1158 struct xgbe_ring_data *rdata;
1159 unsigned int start_index = ring->cur;
1160 unsigned int i;
1161
1162 DBGPR("-->rx_desc_init\n");
1163
1164 /* Initialize all descriptors */
1165 for (i = 0; i < ring->rdesc_count; i++) {
1166 rdata = XGBE_GET_DESC_DATA(ring, i);
1167
1168 /* Initialize Rx descriptor */
1169 xgbe_rx_desc_reset(pdata, rdata, i);
1170 }
1171
1172 /* Update the total number of Rx descriptors */
1173 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
1174
1175 /* Update the starting address of descriptor ring */
1176 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1177 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI,
1178 upper_32_bits(rdata->rdesc_dma));
1179 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO,
1180 lower_32_bits(rdata->rdesc_dma));
1181
1182 /* Update the Rx Descriptor Tail Pointer */
1183 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1);
1184 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1185 lower_32_bits(rdata->rdesc_dma));
1186
1187 DBGPR("<--rx_desc_init\n");
1188 }
1189
xgbe_update_tstamp_addend(struct xgbe_prv_data * pdata,unsigned int addend)1190 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1191 unsigned int addend)
1192 {
1193 /* Set the addend register value and tell the device */
1194 XGMAC_IOWRITE(pdata, MAC_TSAR, addend);
1195 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
1196
1197 /* Wait for addend update to complete */
1198 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
1199 udelay(5);
1200 }
1201
xgbe_set_tstamp_time(struct xgbe_prv_data * pdata,unsigned int sec,unsigned int nsec)1202 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1203 unsigned int nsec)
1204 {
1205 /* Set the time values and tell the device */
1206 XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1207 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1208 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
1209
1210 /* Wait for time update to complete */
1211 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
1212 udelay(5);
1213 }
1214
xgbe_get_tstamp_time(struct xgbe_prv_data * pdata)1215 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
1216 {
1217 u64 nsec;
1218
1219 nsec = XGMAC_IOREAD(pdata, MAC_STSR);
1220 nsec *= NSEC_PER_SEC;
1221 nsec += XGMAC_IOREAD(pdata, MAC_STNR);
1222
1223 return nsec;
1224 }
1225
xgbe_get_tx_tstamp(struct xgbe_prv_data * pdata)1226 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
1227 {
1228 unsigned int tx_snr;
1229 u64 nsec;
1230
1231 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1232 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
1233 return 0;
1234
1235 nsec = XGMAC_IOREAD(pdata, MAC_TXSSR);
1236 nsec *= NSEC_PER_SEC;
1237 nsec += tx_snr;
1238
1239 return nsec;
1240 }
1241
xgbe_get_rx_tstamp(struct xgbe_packet_data * packet,struct xgbe_ring_desc * rdesc)1242 static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1243 struct xgbe_ring_desc *rdesc)
1244 {
1245 u64 nsec;
1246
1247 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) &&
1248 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) {
1249 nsec = le32_to_cpu(rdesc->desc1);
1250 nsec <<= 32;
1251 nsec |= le32_to_cpu(rdesc->desc0);
1252 if (nsec != 0xffffffffffffffffULL) {
1253 packet->rx_tstamp = nsec;
1254 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1255 RX_TSTAMP, 1);
1256 }
1257 }
1258 }
1259
xgbe_config_tstamp(struct xgbe_prv_data * pdata,unsigned int mac_tscr)1260 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata,
1261 unsigned int mac_tscr)
1262 {
1263 /* Set one nano-second accuracy */
1264 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
1265
1266 /* Set fine timestamp update */
1267 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
1268
1269 /* Overwrite earlier timestamps */
1270 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
1271
1272 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1273
1274 /* Exit if timestamping is not enabled */
1275 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA))
1276 return 0;
1277
1278 /* Initialize time registers */
1279 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC);
1280 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC);
1281 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
1282 xgbe_set_tstamp_time(pdata, 0, 0);
1283
1284 /* Initialize the timecounter */
1285 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
1286 ktime_to_ns(ktime_get_real()));
1287
1288 return 0;
1289 }
1290
xgbe_config_dcb_tc(struct xgbe_prv_data * pdata)1291 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata)
1292 {
1293 struct ieee_ets *ets = pdata->ets;
1294 unsigned int total_weight, min_weight, weight;
1295 unsigned int i;
1296
1297 if (!ets)
1298 return;
1299
1300 /* Set Tx to deficit weighted round robin scheduling algorithm (when
1301 * traffic class is using ETS algorithm)
1302 */
1303 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR);
1304
1305 /* Set Traffic Class algorithms */
1306 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt;
1307 min_weight = total_weight / 100;
1308 if (!min_weight)
1309 min_weight = 1;
1310
1311 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1312 switch (ets->tc_tsa[i]) {
1313 case IEEE_8021QAZ_TSA_STRICT:
1314 netif_dbg(pdata, drv, pdata->netdev,
1315 "TC%u using SP\n", i);
1316 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1317 MTL_TSA_SP);
1318 break;
1319 case IEEE_8021QAZ_TSA_ETS:
1320 weight = total_weight * ets->tc_tx_bw[i] / 100;
1321 weight = clamp(weight, min_weight, total_weight);
1322
1323 netif_dbg(pdata, drv, pdata->netdev,
1324 "TC%u using DWRR (weight %u)\n", i, weight);
1325 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1326 MTL_TSA_ETS);
1327 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW,
1328 weight);
1329 break;
1330 }
1331 }
1332 }
1333
xgbe_config_dcb_pfc(struct xgbe_prv_data * pdata)1334 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata)
1335 {
1336 struct ieee_pfc *pfc = pdata->pfc;
1337 struct ieee_ets *ets = pdata->ets;
1338 unsigned int mask, reg, reg_val;
1339 unsigned int tc, prio;
1340
1341 if (!pfc || !ets)
1342 return;
1343
1344 for (tc = 0; tc < pdata->hw_feat.tc_cnt; tc++) {
1345 mask = 0;
1346 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
1347 if ((pfc->pfc_en & (1 << prio)) &&
1348 (ets->prio_tc[prio] == tc))
1349 mask |= (1 << prio);
1350 }
1351 mask &= 0xff;
1352
1353 netif_dbg(pdata, drv, pdata->netdev, "TC%u PFC mask=%#x\n",
1354 tc, mask);
1355 reg = MTL_TCPM0R + (MTL_TCPM_INC * (tc / MTL_TCPM_TC_PER_REG));
1356 reg_val = XGMAC_IOREAD(pdata, reg);
1357
1358 reg_val &= ~(0xff << ((tc % MTL_TCPM_TC_PER_REG) << 3));
1359 reg_val |= (mask << ((tc % MTL_TCPM_TC_PER_REG) << 3));
1360
1361 XGMAC_IOWRITE(pdata, reg, reg_val);
1362 }
1363
1364 xgbe_config_flow_control(pdata);
1365 }
1366
xgbe_tx_start_xmit(struct xgbe_channel * channel,struct xgbe_ring * ring)1367 static void xgbe_tx_start_xmit(struct xgbe_channel *channel,
1368 struct xgbe_ring *ring)
1369 {
1370 struct xgbe_prv_data *pdata = channel->pdata;
1371 struct xgbe_ring_data *rdata;
1372
1373 /* Make sure everything is written before the register write */
1374 wmb();
1375
1376 /* Issue a poll command to Tx DMA by writing address
1377 * of next immediate free descriptor */
1378 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1379 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
1380 lower_32_bits(rdata->rdesc_dma));
1381
1382 /* Start the Tx timer */
1383 if (pdata->tx_usecs && !channel->tx_timer_active) {
1384 channel->tx_timer_active = 1;
1385 mod_timer(&channel->tx_timer,
1386 jiffies + usecs_to_jiffies(pdata->tx_usecs));
1387 }
1388
1389 ring->tx.xmit_more = 0;
1390 }
1391
xgbe_dev_xmit(struct xgbe_channel * channel)1392 static void xgbe_dev_xmit(struct xgbe_channel *channel)
1393 {
1394 struct xgbe_prv_data *pdata = channel->pdata;
1395 struct xgbe_ring *ring = channel->tx_ring;
1396 struct xgbe_ring_data *rdata;
1397 struct xgbe_ring_desc *rdesc;
1398 struct xgbe_packet_data *packet = &ring->packet_data;
1399 unsigned int csum, tso, vlan;
1400 unsigned int tso_context, vlan_context;
1401 unsigned int tx_set_ic;
1402 int start_index = ring->cur;
1403 int cur_index = ring->cur;
1404 int i;
1405
1406 DBGPR("-->xgbe_dev_xmit\n");
1407
1408 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1409 CSUM_ENABLE);
1410 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1411 TSO_ENABLE);
1412 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1413 VLAN_CTAG);
1414
1415 if (tso && (packet->mss != ring->tx.cur_mss))
1416 tso_context = 1;
1417 else
1418 tso_context = 0;
1419
1420 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag))
1421 vlan_context = 1;
1422 else
1423 vlan_context = 0;
1424
1425 /* Determine if an interrupt should be generated for this Tx:
1426 * Interrupt:
1427 * - Tx frame count exceeds the frame count setting
1428 * - Addition of Tx frame count to the frame count since the
1429 * last interrupt was set exceeds the frame count setting
1430 * No interrupt:
1431 * - No frame count setting specified (ethtool -C ethX tx-frames 0)
1432 * - Addition of Tx frame count to the frame count since the
1433 * last interrupt was set does not exceed the frame count setting
1434 */
1435 ring->coalesce_count += packet->tx_packets;
1436 if (!pdata->tx_frames)
1437 tx_set_ic = 0;
1438 else if (packet->tx_packets > pdata->tx_frames)
1439 tx_set_ic = 1;
1440 else if ((ring->coalesce_count % pdata->tx_frames) <
1441 packet->tx_packets)
1442 tx_set_ic = 1;
1443 else
1444 tx_set_ic = 0;
1445
1446 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1447 rdesc = rdata->rdesc;
1448
1449 /* Create a context descriptor if this is a TSO packet */
1450 if (tso_context || vlan_context) {
1451 if (tso_context) {
1452 netif_dbg(pdata, tx_queued, pdata->netdev,
1453 "TSO context descriptor, mss=%u\n",
1454 packet->mss);
1455
1456 /* Set the MSS size */
1457 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2,
1458 MSS, packet->mss);
1459
1460 /* Mark it as a CONTEXT descriptor */
1461 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1462 CTXT, 1);
1463
1464 /* Indicate this descriptor contains the MSS */
1465 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1466 TCMSSV, 1);
1467
1468 ring->tx.cur_mss = packet->mss;
1469 }
1470
1471 if (vlan_context) {
1472 netif_dbg(pdata, tx_queued, pdata->netdev,
1473 "VLAN context descriptor, ctag=%u\n",
1474 packet->vlan_ctag);
1475
1476 /* Mark it as a CONTEXT descriptor */
1477 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1478 CTXT, 1);
1479
1480 /* Set the VLAN tag */
1481 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1482 VT, packet->vlan_ctag);
1483
1484 /* Indicate this descriptor contains the VLAN tag */
1485 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1486 VLTV, 1);
1487
1488 ring->tx.cur_vlan_ctag = packet->vlan_ctag;
1489 }
1490
1491 cur_index++;
1492 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1493 rdesc = rdata->rdesc;
1494 }
1495
1496 /* Update buffer address (for TSO this is the header) */
1497 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1498 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1499
1500 /* Update the buffer length */
1501 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1502 rdata->skb_dma_len);
1503
1504 /* VLAN tag insertion check */
1505 if (vlan)
1506 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR,
1507 TX_NORMAL_DESC2_VLAN_INSERT);
1508
1509 /* Timestamp enablement check */
1510 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1511 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1);
1512
1513 /* Mark it as First Descriptor */
1514 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1);
1515
1516 /* Mark it as a NORMAL descriptor */
1517 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1518
1519 /* Set OWN bit if not the first descriptor */
1520 if (cur_index != start_index)
1521 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1522
1523 if (tso) {
1524 /* Enable TSO */
1525 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1);
1526 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL,
1527 packet->tcp_payload_len);
1528 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN,
1529 packet->tcp_header_len / 4);
1530
1531 pdata->ext_stats.tx_tso_packets++;
1532 } else {
1533 /* Enable CRC and Pad Insertion */
1534 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0);
1535
1536 /* Enable HW CSUM */
1537 if (csum)
1538 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1539 CIC, 0x3);
1540
1541 /* Set the total length to be transmitted */
1542 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL,
1543 packet->length);
1544 }
1545
1546 for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) {
1547 cur_index++;
1548 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
1549 rdesc = rdata->rdesc;
1550
1551 /* Update buffer address */
1552 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1553 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1554
1555 /* Update the buffer length */
1556 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1557 rdata->skb_dma_len);
1558
1559 /* Set OWN bit */
1560 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1561
1562 /* Mark it as NORMAL descriptor */
1563 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1564
1565 /* Enable HW CSUM */
1566 if (csum)
1567 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1568 CIC, 0x3);
1569 }
1570
1571 /* Set LAST bit for the last descriptor */
1572 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1);
1573
1574 /* Set IC bit based on Tx coalescing settings */
1575 if (tx_set_ic)
1576 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
1577
1578 /* Save the Tx info to report back during cleanup */
1579 rdata->tx.packets = packet->tx_packets;
1580 rdata->tx.bytes = packet->tx_bytes;
1581
1582 /* In case the Tx DMA engine is running, make sure everything
1583 * is written to the descriptor(s) before setting the OWN bit
1584 * for the first descriptor
1585 */
1586 dma_wmb();
1587
1588 /* Set OWN bit for the first descriptor */
1589 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1590 rdesc = rdata->rdesc;
1591 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1592
1593 if (netif_msg_tx_queued(pdata))
1594 xgbe_dump_tx_desc(pdata, ring, start_index,
1595 packet->rdesc_count, 1);
1596
1597 /* Make sure ownership is written to the descriptor */
1598 smp_wmb();
1599
1600 ring->cur = cur_index + 1;
1601 if (!packet->skb->xmit_more ||
1602 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev,
1603 channel->queue_index)))
1604 xgbe_tx_start_xmit(channel, ring);
1605 else
1606 ring->tx.xmit_more = 1;
1607
1608 DBGPR(" %s: descriptors %u to %u written\n",
1609 channel->name, start_index & (ring->rdesc_count - 1),
1610 (ring->cur - 1) & (ring->rdesc_count - 1));
1611
1612 DBGPR("<--xgbe_dev_xmit\n");
1613 }
1614
xgbe_dev_read(struct xgbe_channel * channel)1615 static int xgbe_dev_read(struct xgbe_channel *channel)
1616 {
1617 struct xgbe_prv_data *pdata = channel->pdata;
1618 struct xgbe_ring *ring = channel->rx_ring;
1619 struct xgbe_ring_data *rdata;
1620 struct xgbe_ring_desc *rdesc;
1621 struct xgbe_packet_data *packet = &ring->packet_data;
1622 struct net_device *netdev = pdata->netdev;
1623 unsigned int err, etlt, l34t;
1624
1625 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur);
1626
1627 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1628 rdesc = rdata->rdesc;
1629
1630 /* Check for data availability */
1631 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
1632 return 1;
1633
1634 /* Make sure descriptor fields are read after reading the OWN bit */
1635 dma_rmb();
1636
1637 if (netif_msg_rx_status(pdata))
1638 xgbe_dump_rx_desc(pdata, ring, ring->cur);
1639
1640 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) {
1641 /* Timestamp Context Descriptor */
1642 xgbe_get_rx_tstamp(packet, rdesc);
1643
1644 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1645 CONTEXT, 1);
1646 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1647 CONTEXT_NEXT, 0);
1648 return 0;
1649 }
1650
1651 /* Normal Descriptor, be sure Context Descriptor bit is off */
1652 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
1653
1654 /* Indicate if a Context Descriptor is next */
1655 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
1656 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1657 CONTEXT_NEXT, 1);
1658
1659 /* Get the header length */
1660 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) {
1661 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1662 FIRST, 1);
1663 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2,
1664 RX_NORMAL_DESC2, HL);
1665 if (rdata->rx.hdr_len)
1666 pdata->ext_stats.rx_split_header_packets++;
1667 } else {
1668 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1669 FIRST, 0);
1670 }
1671
1672 /* Get the RSS hash */
1673 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) {
1674 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1675 RSS_HASH, 1);
1676
1677 packet->rss_hash = le32_to_cpu(rdesc->desc1);
1678
1679 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T);
1680 switch (l34t) {
1681 case RX_DESC3_L34T_IPV4_TCP:
1682 case RX_DESC3_L34T_IPV4_UDP:
1683 case RX_DESC3_L34T_IPV6_TCP:
1684 case RX_DESC3_L34T_IPV6_UDP:
1685 packet->rss_hash_type = PKT_HASH_TYPE_L4;
1686 break;
1687 default:
1688 packet->rss_hash_type = PKT_HASH_TYPE_L3;
1689 }
1690 }
1691
1692 /* Not all the data has been transferred for this packet */
1693 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD))
1694 return 0;
1695
1696 /* This is the last of the data for this packet */
1697 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1698 LAST, 1);
1699
1700 /* Get the packet length */
1701 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
1702
1703 /* Set checksum done indicator as appropriate */
1704 if (netdev->features & NETIF_F_RXCSUM)
1705 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1706 CSUM_DONE, 1);
1707
1708 /* Check for errors (only valid in last descriptor) */
1709 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES);
1710 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT);
1711 netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt);
1712
1713 if (!err || !etlt) {
1714 /* No error if err is 0 or etlt is 0 */
1715 if ((etlt == 0x09) &&
1716 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1717 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1718 VLAN_CTAG, 1);
1719 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0,
1720 RX_NORMAL_DESC0,
1721 OVT);
1722 netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n",
1723 packet->vlan_ctag);
1724 }
1725 } else {
1726 if ((etlt == 0x05) || (etlt == 0x06))
1727 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1728 CSUM_DONE, 0);
1729 else
1730 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
1731 FRAME, 1);
1732 }
1733
1734 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name,
1735 ring->cur & (ring->rdesc_count - 1), ring->cur);
1736
1737 return 0;
1738 }
1739
xgbe_is_context_desc(struct xgbe_ring_desc * rdesc)1740 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc)
1741 {
1742 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */
1743 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT);
1744 }
1745
xgbe_is_last_desc(struct xgbe_ring_desc * rdesc)1746 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc)
1747 {
1748 /* Rx and Tx share LD bit, so check TDES3.LD bit */
1749 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD);
1750 }
1751
xgbe_enable_int(struct xgbe_channel * channel,enum xgbe_int int_id)1752 static int xgbe_enable_int(struct xgbe_channel *channel,
1753 enum xgbe_int int_id)
1754 {
1755 unsigned int dma_ch_ier;
1756
1757 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1758
1759 switch (int_id) {
1760 case XGMAC_INT_DMA_CH_SR_TI:
1761 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1762 break;
1763 case XGMAC_INT_DMA_CH_SR_TPS:
1764 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1);
1765 break;
1766 case XGMAC_INT_DMA_CH_SR_TBU:
1767 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1);
1768 break;
1769 case XGMAC_INT_DMA_CH_SR_RI:
1770 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
1771 break;
1772 case XGMAC_INT_DMA_CH_SR_RBU:
1773 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
1774 break;
1775 case XGMAC_INT_DMA_CH_SR_RPS:
1776 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1);
1777 break;
1778 case XGMAC_INT_DMA_CH_SR_TI_RI:
1779 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1780 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
1781 break;
1782 case XGMAC_INT_DMA_CH_SR_FBE:
1783 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
1784 break;
1785 case XGMAC_INT_DMA_ALL:
1786 dma_ch_ier |= channel->saved_ier;
1787 break;
1788 default:
1789 return -1;
1790 }
1791
1792 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1793
1794 return 0;
1795 }
1796
xgbe_disable_int(struct xgbe_channel * channel,enum xgbe_int int_id)1797 static int xgbe_disable_int(struct xgbe_channel *channel,
1798 enum xgbe_int int_id)
1799 {
1800 unsigned int dma_ch_ier;
1801
1802 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1803
1804 switch (int_id) {
1805 case XGMAC_INT_DMA_CH_SR_TI:
1806 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1807 break;
1808 case XGMAC_INT_DMA_CH_SR_TPS:
1809 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0);
1810 break;
1811 case XGMAC_INT_DMA_CH_SR_TBU:
1812 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0);
1813 break;
1814 case XGMAC_INT_DMA_CH_SR_RI:
1815 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
1816 break;
1817 case XGMAC_INT_DMA_CH_SR_RBU:
1818 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0);
1819 break;
1820 case XGMAC_INT_DMA_CH_SR_RPS:
1821 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0);
1822 break;
1823 case XGMAC_INT_DMA_CH_SR_TI_RI:
1824 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1825 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
1826 break;
1827 case XGMAC_INT_DMA_CH_SR_FBE:
1828 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0);
1829 break;
1830 case XGMAC_INT_DMA_ALL:
1831 channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK;
1832 dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK;
1833 break;
1834 default:
1835 return -1;
1836 }
1837
1838 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1839
1840 return 0;
1841 }
1842
xgbe_exit(struct xgbe_prv_data * pdata)1843 static int xgbe_exit(struct xgbe_prv_data *pdata)
1844 {
1845 unsigned int count = 2000;
1846
1847 DBGPR("-->xgbe_exit\n");
1848
1849 /* Issue a software reset */
1850 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1);
1851 usleep_range(10, 15);
1852
1853 /* Poll Until Poll Condition */
1854 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
1855 usleep_range(500, 600);
1856
1857 if (!count)
1858 return -EBUSY;
1859
1860 DBGPR("<--xgbe_exit\n");
1861
1862 return 0;
1863 }
1864
xgbe_flush_tx_queues(struct xgbe_prv_data * pdata)1865 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
1866 {
1867 unsigned int i, count;
1868
1869 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21)
1870 return 0;
1871
1872 for (i = 0; i < pdata->tx_q_count; i++)
1873 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
1874
1875 /* Poll Until Poll Condition */
1876 for (i = 0; i < pdata->tx_q_count; i++) {
1877 count = 2000;
1878 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i,
1879 MTL_Q_TQOMR, FTQ))
1880 usleep_range(500, 600);
1881
1882 if (!count)
1883 return -EBUSY;
1884 }
1885
1886 return 0;
1887 }
1888
xgbe_config_dma_bus(struct xgbe_prv_data * pdata)1889 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
1890 {
1891 /* Set enhanced addressing mode */
1892 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1);
1893
1894 /* Set the System Bus mode */
1895 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1);
1896 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1);
1897 }
1898
xgbe_config_dma_cache(struct xgbe_prv_data * pdata)1899 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
1900 {
1901 unsigned int arcache, awcache;
1902
1903 arcache = 0;
1904 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache);
1905 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain);
1906 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache);
1907 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain);
1908 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache);
1909 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain);
1910 XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache);
1911
1912 awcache = 0;
1913 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache);
1914 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain);
1915 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache);
1916 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain);
1917 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache);
1918 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain);
1919 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache);
1920 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain);
1921 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache);
1922 }
1923
xgbe_config_mtl_mode(struct xgbe_prv_data * pdata)1924 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
1925 {
1926 unsigned int i;
1927
1928 /* Set Tx to weighted round robin scheduling algorithm */
1929 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
1930
1931 /* Set Tx traffic classes to use WRR algorithm with equal weights */
1932 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1933 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1934 MTL_TSA_ETS);
1935 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1);
1936 }
1937
1938 /* Set Rx to strict priority algorithm */
1939 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
1940 }
1941
xgbe_calculate_per_queue_fifo(unsigned int fifo_size,unsigned int queue_count)1942 static unsigned int xgbe_calculate_per_queue_fifo(unsigned int fifo_size,
1943 unsigned int queue_count)
1944 {
1945 unsigned int q_fifo_size;
1946 unsigned int p_fifo;
1947
1948 /* Calculate the configured fifo size */
1949 q_fifo_size = 1 << (fifo_size + 7);
1950
1951 /* The configured value may not be the actual amount of fifo RAM */
1952 q_fifo_size = min_t(unsigned int, XGBE_FIFO_MAX, q_fifo_size);
1953
1954 q_fifo_size = q_fifo_size / queue_count;
1955
1956 /* Each increment in the queue fifo size represents 256 bytes of
1957 * fifo, with 0 representing 256 bytes. Distribute the fifo equally
1958 * between the queues.
1959 */
1960 p_fifo = q_fifo_size / 256;
1961 if (p_fifo)
1962 p_fifo--;
1963
1964 return p_fifo;
1965 }
1966
xgbe_config_tx_fifo_size(struct xgbe_prv_data * pdata)1967 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
1968 {
1969 unsigned int fifo_size;
1970 unsigned int i;
1971
1972 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size,
1973 pdata->tx_q_count);
1974
1975 for (i = 0; i < pdata->tx_q_count; i++)
1976 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size);
1977
1978 netif_info(pdata, drv, pdata->netdev,
1979 "%d Tx hardware queues, %d byte fifo per queue\n",
1980 pdata->tx_q_count, ((fifo_size + 1) * 256));
1981 }
1982
xgbe_config_rx_fifo_size(struct xgbe_prv_data * pdata)1983 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
1984 {
1985 unsigned int fifo_size;
1986 unsigned int i;
1987
1988 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size,
1989 pdata->rx_q_count);
1990
1991 for (i = 0; i < pdata->rx_q_count; i++)
1992 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size);
1993
1994 netif_info(pdata, drv, pdata->netdev,
1995 "%d Rx hardware queues, %d byte fifo per queue\n",
1996 pdata->rx_q_count, ((fifo_size + 1) * 256));
1997 }
1998
xgbe_config_queue_mapping(struct xgbe_prv_data * pdata)1999 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
2000 {
2001 unsigned int qptc, qptc_extra, queue;
2002 unsigned int prio_queues;
2003 unsigned int ppq, ppq_extra, prio;
2004 unsigned int mask;
2005 unsigned int i, j, reg, reg_val;
2006
2007 /* Map the MTL Tx Queues to Traffic Classes
2008 * Note: Tx Queues >= Traffic Classes
2009 */
2010 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
2011 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
2012
2013 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
2014 for (j = 0; j < qptc; j++) {
2015 netif_dbg(pdata, drv, pdata->netdev,
2016 "TXq%u mapped to TC%u\n", queue, i);
2017 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2018 Q2TCMAP, i);
2019 pdata->q2tc_map[queue++] = i;
2020 }
2021
2022 if (i < qptc_extra) {
2023 netif_dbg(pdata, drv, pdata->netdev,
2024 "TXq%u mapped to TC%u\n", queue, i);
2025 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2026 Q2TCMAP, i);
2027 pdata->q2tc_map[queue++] = i;
2028 }
2029 }
2030
2031 /* Map the 8 VLAN priority values to available MTL Rx queues */
2032 prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS,
2033 pdata->rx_q_count);
2034 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues;
2035 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues;
2036
2037 reg = MAC_RQC2R;
2038 reg_val = 0;
2039 for (i = 0, prio = 0; i < prio_queues;) {
2040 mask = 0;
2041 for (j = 0; j < ppq; j++) {
2042 netif_dbg(pdata, drv, pdata->netdev,
2043 "PRIO%u mapped to RXq%u\n", prio, i);
2044 mask |= (1 << prio);
2045 pdata->prio2q_map[prio++] = i;
2046 }
2047
2048 if (i < ppq_extra) {
2049 netif_dbg(pdata, drv, pdata->netdev,
2050 "PRIO%u mapped to RXq%u\n", prio, i);
2051 mask |= (1 << prio);
2052 pdata->prio2q_map[prio++] = i;
2053 }
2054
2055 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
2056
2057 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues))
2058 continue;
2059
2060 XGMAC_IOWRITE(pdata, reg, reg_val);
2061 reg += MAC_RQC2_INC;
2062 reg_val = 0;
2063 }
2064
2065 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
2066 reg = MTL_RQDCM0R;
2067 reg_val = 0;
2068 for (i = 0; i < pdata->rx_q_count;) {
2069 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));
2070
2071 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
2072 continue;
2073
2074 XGMAC_IOWRITE(pdata, reg, reg_val);
2075
2076 reg += MTL_RQDCM_INC;
2077 reg_val = 0;
2078 }
2079 }
2080
xgbe_config_flow_control_threshold(struct xgbe_prv_data * pdata)2081 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
2082 {
2083 unsigned int i;
2084
2085 for (i = 0; i < pdata->rx_q_count; i++) {
2086 /* Activate flow control when less than 4k left in fifo */
2087 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 2);
2088
2089 /* De-activate flow control when more than 6k left in fifo */
2090 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 4);
2091 }
2092 }
2093
xgbe_config_mac_address(struct xgbe_prv_data * pdata)2094 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata)
2095 {
2096 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr);
2097
2098 /* Filtering is done using perfect filtering and hash filtering */
2099 if (pdata->hw_feat.hash_table_size) {
2100 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
2101 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
2102 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1);
2103 }
2104 }
2105
xgbe_config_jumbo_enable(struct xgbe_prv_data * pdata)2106 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
2107 {
2108 unsigned int val;
2109
2110 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0;
2111
2112 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
2113 }
2114
xgbe_config_mac_speed(struct xgbe_prv_data * pdata)2115 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata)
2116 {
2117 switch (pdata->phy_speed) {
2118 case SPEED_10000:
2119 xgbe_set_xgmii_speed(pdata);
2120 break;
2121
2122 case SPEED_2500:
2123 xgbe_set_gmii_2500_speed(pdata);
2124 break;
2125
2126 case SPEED_1000:
2127 xgbe_set_gmii_speed(pdata);
2128 break;
2129 }
2130 }
2131
xgbe_config_checksum_offload(struct xgbe_prv_data * pdata)2132 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata)
2133 {
2134 if (pdata->netdev->features & NETIF_F_RXCSUM)
2135 xgbe_enable_rx_csum(pdata);
2136 else
2137 xgbe_disable_rx_csum(pdata);
2138 }
2139
xgbe_config_vlan_support(struct xgbe_prv_data * pdata)2140 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata)
2141 {
2142 /* Indicate that VLAN Tx CTAGs come from context descriptors */
2143 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
2144 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
2145
2146 /* Set the current VLAN Hash Table register value */
2147 xgbe_update_vlan_hash_table(pdata);
2148
2149 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
2150 xgbe_enable_rx_vlan_filtering(pdata);
2151 else
2152 xgbe_disable_rx_vlan_filtering(pdata);
2153
2154 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2155 xgbe_enable_rx_vlan_stripping(pdata);
2156 else
2157 xgbe_disable_rx_vlan_stripping(pdata);
2158 }
2159
xgbe_mmc_read(struct xgbe_prv_data * pdata,unsigned int reg_lo)2160 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo)
2161 {
2162 bool read_hi;
2163 u64 val;
2164
2165 switch (reg_lo) {
2166 /* These registers are always 64 bit */
2167 case MMC_TXOCTETCOUNT_GB_LO:
2168 case MMC_TXOCTETCOUNT_G_LO:
2169 case MMC_RXOCTETCOUNT_GB_LO:
2170 case MMC_RXOCTETCOUNT_G_LO:
2171 read_hi = true;
2172 break;
2173
2174 default:
2175 read_hi = false;
2176 }
2177
2178 val = XGMAC_IOREAD(pdata, reg_lo);
2179
2180 if (read_hi)
2181 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32);
2182
2183 return val;
2184 }
2185
xgbe_tx_mmc_int(struct xgbe_prv_data * pdata)2186 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata)
2187 {
2188 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2189 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR);
2190
2191 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB))
2192 stats->txoctetcount_gb +=
2193 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2194
2195 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB))
2196 stats->txframecount_gb +=
2197 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2198
2199 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G))
2200 stats->txbroadcastframes_g +=
2201 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2202
2203 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G))
2204 stats->txmulticastframes_g +=
2205 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2206
2207 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB))
2208 stats->tx64octets_gb +=
2209 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2210
2211 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB))
2212 stats->tx65to127octets_gb +=
2213 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2214
2215 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB))
2216 stats->tx128to255octets_gb +=
2217 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2218
2219 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB))
2220 stats->tx256to511octets_gb +=
2221 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2222
2223 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB))
2224 stats->tx512to1023octets_gb +=
2225 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2226
2227 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB))
2228 stats->tx1024tomaxoctets_gb +=
2229 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2230
2231 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB))
2232 stats->txunicastframes_gb +=
2233 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2234
2235 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB))
2236 stats->txmulticastframes_gb +=
2237 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2238
2239 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB))
2240 stats->txbroadcastframes_g +=
2241 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2242
2243 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR))
2244 stats->txunderflowerror +=
2245 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2246
2247 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G))
2248 stats->txoctetcount_g +=
2249 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2250
2251 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G))
2252 stats->txframecount_g +=
2253 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2254
2255 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES))
2256 stats->txpauseframes +=
2257 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2258
2259 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G))
2260 stats->txvlanframes_g +=
2261 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2262 }
2263
xgbe_rx_mmc_int(struct xgbe_prv_data * pdata)2264 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata)
2265 {
2266 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2267 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR);
2268
2269 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB))
2270 stats->rxframecount_gb +=
2271 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2272
2273 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB))
2274 stats->rxoctetcount_gb +=
2275 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2276
2277 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G))
2278 stats->rxoctetcount_g +=
2279 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2280
2281 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G))
2282 stats->rxbroadcastframes_g +=
2283 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2284
2285 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G))
2286 stats->rxmulticastframes_g +=
2287 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2288
2289 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR))
2290 stats->rxcrcerror +=
2291 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
2292
2293 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR))
2294 stats->rxrunterror +=
2295 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
2296
2297 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR))
2298 stats->rxjabbererror +=
2299 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
2300
2301 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G))
2302 stats->rxundersize_g +=
2303 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2304
2305 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G))
2306 stats->rxoversize_g +=
2307 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
2308
2309 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB))
2310 stats->rx64octets_gb +=
2311 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2312
2313 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB))
2314 stats->rx65to127octets_gb +=
2315 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2316
2317 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB))
2318 stats->rx128to255octets_gb +=
2319 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2320
2321 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB))
2322 stats->rx256to511octets_gb +=
2323 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2324
2325 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB))
2326 stats->rx512to1023octets_gb +=
2327 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2328
2329 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB))
2330 stats->rx1024tomaxoctets_gb +=
2331 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2332
2333 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G))
2334 stats->rxunicastframes_g +=
2335 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
2336
2337 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR))
2338 stats->rxlengtherror +=
2339 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
2340
2341 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE))
2342 stats->rxoutofrangetype +=
2343 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
2344
2345 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES))
2346 stats->rxpauseframes +=
2347 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
2348
2349 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW))
2350 stats->rxfifooverflow +=
2351 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
2352
2353 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB))
2354 stats->rxvlanframes_gb +=
2355 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
2356
2357 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR))
2358 stats->rxwatchdogerror +=
2359 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
2360 }
2361
xgbe_read_mmc_stats(struct xgbe_prv_data * pdata)2362 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
2363 {
2364 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2365
2366 /* Freeze counters */
2367 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
2368
2369 stats->txoctetcount_gb +=
2370 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2371
2372 stats->txframecount_gb +=
2373 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2374
2375 stats->txbroadcastframes_g +=
2376 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2377
2378 stats->txmulticastframes_g +=
2379 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2380
2381 stats->tx64octets_gb +=
2382 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2383
2384 stats->tx65to127octets_gb +=
2385 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2386
2387 stats->tx128to255octets_gb +=
2388 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2389
2390 stats->tx256to511octets_gb +=
2391 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2392
2393 stats->tx512to1023octets_gb +=
2394 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2395
2396 stats->tx1024tomaxoctets_gb +=
2397 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2398
2399 stats->txunicastframes_gb +=
2400 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2401
2402 stats->txmulticastframes_gb +=
2403 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2404
2405 stats->txbroadcastframes_g +=
2406 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2407
2408 stats->txunderflowerror +=
2409 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2410
2411 stats->txoctetcount_g +=
2412 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2413
2414 stats->txframecount_g +=
2415 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2416
2417 stats->txpauseframes +=
2418 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2419
2420 stats->txvlanframes_g +=
2421 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2422
2423 stats->rxframecount_gb +=
2424 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2425
2426 stats->rxoctetcount_gb +=
2427 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2428
2429 stats->rxoctetcount_g +=
2430 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2431
2432 stats->rxbroadcastframes_g +=
2433 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2434
2435 stats->rxmulticastframes_g +=
2436 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2437
2438 stats->rxcrcerror +=
2439 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
2440
2441 stats->rxrunterror +=
2442 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
2443
2444 stats->rxjabbererror +=
2445 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
2446
2447 stats->rxundersize_g +=
2448 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2449
2450 stats->rxoversize_g +=
2451 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
2452
2453 stats->rx64octets_gb +=
2454 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2455
2456 stats->rx65to127octets_gb +=
2457 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2458
2459 stats->rx128to255octets_gb +=
2460 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2461
2462 stats->rx256to511octets_gb +=
2463 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2464
2465 stats->rx512to1023octets_gb +=
2466 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2467
2468 stats->rx1024tomaxoctets_gb +=
2469 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2470
2471 stats->rxunicastframes_g +=
2472 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
2473
2474 stats->rxlengtherror +=
2475 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
2476
2477 stats->rxoutofrangetype +=
2478 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
2479
2480 stats->rxpauseframes +=
2481 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
2482
2483 stats->rxfifooverflow +=
2484 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
2485
2486 stats->rxvlanframes_gb +=
2487 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
2488
2489 stats->rxwatchdogerror +=
2490 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
2491
2492 /* Un-freeze counters */
2493 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
2494 }
2495
xgbe_config_mmc(struct xgbe_prv_data * pdata)2496 static void xgbe_config_mmc(struct xgbe_prv_data *pdata)
2497 {
2498 /* Set counters to reset on read */
2499 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
2500
2501 /* Reset the counters */
2502 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
2503 }
2504
xgbe_prepare_tx_stop(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)2505 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata,
2506 struct xgbe_channel *channel)
2507 {
2508 unsigned int tx_dsr, tx_pos, tx_qidx;
2509 unsigned int tx_status;
2510 unsigned long tx_timeout;
2511
2512 /* Calculate the status register to read and the position within */
2513 if (channel->queue_index < DMA_DSRX_FIRST_QUEUE) {
2514 tx_dsr = DMA_DSR0;
2515 tx_pos = (channel->queue_index * DMA_DSR_Q_WIDTH) +
2516 DMA_DSR0_TPS_START;
2517 } else {
2518 tx_qidx = channel->queue_index - DMA_DSRX_FIRST_QUEUE;
2519
2520 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC);
2521 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) +
2522 DMA_DSRX_TPS_START;
2523 }
2524
2525 /* The Tx engine cannot be stopped if it is actively processing
2526 * descriptors. Wait for the Tx engine to enter the stopped or
2527 * suspended state. Don't wait forever though...
2528 */
2529 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
2530 while (time_before(jiffies, tx_timeout)) {
2531 tx_status = XGMAC_IOREAD(pdata, tx_dsr);
2532 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH);
2533 if ((tx_status == DMA_TPS_STOPPED) ||
2534 (tx_status == DMA_TPS_SUSPENDED))
2535 break;
2536
2537 usleep_range(500, 1000);
2538 }
2539
2540 if (!time_before(jiffies, tx_timeout))
2541 netdev_info(pdata->netdev,
2542 "timed out waiting for Tx DMA channel %u to stop\n",
2543 channel->queue_index);
2544 }
2545
xgbe_enable_tx(struct xgbe_prv_data * pdata)2546 static void xgbe_enable_tx(struct xgbe_prv_data *pdata)
2547 {
2548 struct xgbe_channel *channel;
2549 unsigned int i;
2550
2551 /* Enable each Tx DMA channel */
2552 channel = pdata->channel;
2553 for (i = 0; i < pdata->channel_count; i++, channel++) {
2554 if (!channel->tx_ring)
2555 break;
2556
2557 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2558 }
2559
2560 /* Enable each Tx queue */
2561 for (i = 0; i < pdata->tx_q_count; i++)
2562 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
2563 MTL_Q_ENABLED);
2564
2565 /* Enable MAC Tx */
2566 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2567 }
2568
xgbe_disable_tx(struct xgbe_prv_data * pdata)2569 static void xgbe_disable_tx(struct xgbe_prv_data *pdata)
2570 {
2571 struct xgbe_channel *channel;
2572 unsigned int i;
2573
2574 /* Prepare for Tx DMA channel stop */
2575 channel = pdata->channel;
2576 for (i = 0; i < pdata->channel_count; i++, channel++) {
2577 if (!channel->tx_ring)
2578 break;
2579
2580 xgbe_prepare_tx_stop(pdata, channel);
2581 }
2582
2583 /* Disable MAC Tx */
2584 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2585
2586 /* Disable each Tx queue */
2587 for (i = 0; i < pdata->tx_q_count; i++)
2588 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
2589
2590 /* Disable each Tx DMA channel */
2591 channel = pdata->channel;
2592 for (i = 0; i < pdata->channel_count; i++, channel++) {
2593 if (!channel->tx_ring)
2594 break;
2595
2596 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2597 }
2598 }
2599
xgbe_enable_rx(struct xgbe_prv_data * pdata)2600 static void xgbe_enable_rx(struct xgbe_prv_data *pdata)
2601 {
2602 struct xgbe_channel *channel;
2603 unsigned int reg_val, i;
2604
2605 /* Enable each Rx DMA channel */
2606 channel = pdata->channel;
2607 for (i = 0; i < pdata->channel_count; i++, channel++) {
2608 if (!channel->rx_ring)
2609 break;
2610
2611 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2612 }
2613
2614 /* Enable each Rx queue */
2615 reg_val = 0;
2616 for (i = 0; i < pdata->rx_q_count; i++)
2617 reg_val |= (0x02 << (i << 1));
2618 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
2619
2620 /* Enable MAC Rx */
2621 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
2622 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
2623 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
2624 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
2625 }
2626
xgbe_disable_rx(struct xgbe_prv_data * pdata)2627 static void xgbe_disable_rx(struct xgbe_prv_data *pdata)
2628 {
2629 struct xgbe_channel *channel;
2630 unsigned int i;
2631
2632 /* Disable MAC Rx */
2633 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
2634 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
2635 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
2636 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
2637
2638 /* Disable each Rx queue */
2639 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
2640
2641 /* Disable each Rx DMA channel */
2642 channel = pdata->channel;
2643 for (i = 0; i < pdata->channel_count; i++, channel++) {
2644 if (!channel->rx_ring)
2645 break;
2646
2647 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2648 }
2649 }
2650
xgbe_powerup_tx(struct xgbe_prv_data * pdata)2651 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata)
2652 {
2653 struct xgbe_channel *channel;
2654 unsigned int i;
2655
2656 /* Enable each Tx DMA channel */
2657 channel = pdata->channel;
2658 for (i = 0; i < pdata->channel_count; i++, channel++) {
2659 if (!channel->tx_ring)
2660 break;
2661
2662 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2663 }
2664
2665 /* Enable MAC Tx */
2666 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2667 }
2668
xgbe_powerdown_tx(struct xgbe_prv_data * pdata)2669 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata)
2670 {
2671 struct xgbe_channel *channel;
2672 unsigned int i;
2673
2674 /* Prepare for Tx DMA channel stop */
2675 channel = pdata->channel;
2676 for (i = 0; i < pdata->channel_count; i++, channel++) {
2677 if (!channel->tx_ring)
2678 break;
2679
2680 xgbe_prepare_tx_stop(pdata, channel);
2681 }
2682
2683 /* Disable MAC Tx */
2684 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2685
2686 /* Disable each Tx DMA channel */
2687 channel = pdata->channel;
2688 for (i = 0; i < pdata->channel_count; i++, channel++) {
2689 if (!channel->tx_ring)
2690 break;
2691
2692 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2693 }
2694 }
2695
xgbe_powerup_rx(struct xgbe_prv_data * pdata)2696 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata)
2697 {
2698 struct xgbe_channel *channel;
2699 unsigned int i;
2700
2701 /* Enable each Rx DMA channel */
2702 channel = pdata->channel;
2703 for (i = 0; i < pdata->channel_count; i++, channel++) {
2704 if (!channel->rx_ring)
2705 break;
2706
2707 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2708 }
2709 }
2710
xgbe_powerdown_rx(struct xgbe_prv_data * pdata)2711 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata)
2712 {
2713 struct xgbe_channel *channel;
2714 unsigned int i;
2715
2716 /* Disable each Rx DMA channel */
2717 channel = pdata->channel;
2718 for (i = 0; i < pdata->channel_count; i++, channel++) {
2719 if (!channel->rx_ring)
2720 break;
2721
2722 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2723 }
2724 }
2725
xgbe_init(struct xgbe_prv_data * pdata)2726 static int xgbe_init(struct xgbe_prv_data *pdata)
2727 {
2728 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2729 int ret;
2730
2731 DBGPR("-->xgbe_init\n");
2732
2733 /* Flush Tx queues */
2734 ret = xgbe_flush_tx_queues(pdata);
2735 if (ret) {
2736 netdev_err(pdata->netdev, "error flushing TX queues\n");
2737 return ret;
2738 }
2739
2740 /*
2741 * Initialize DMA related features
2742 */
2743 xgbe_config_dma_bus(pdata);
2744 xgbe_config_dma_cache(pdata);
2745 xgbe_config_osp_mode(pdata);
2746 xgbe_config_pblx8(pdata);
2747 xgbe_config_tx_pbl_val(pdata);
2748 xgbe_config_rx_pbl_val(pdata);
2749 xgbe_config_rx_coalesce(pdata);
2750 xgbe_config_tx_coalesce(pdata);
2751 xgbe_config_rx_buffer_size(pdata);
2752 xgbe_config_tso_mode(pdata);
2753 xgbe_config_sph_mode(pdata);
2754 xgbe_config_rss(pdata);
2755 desc_if->wrapper_tx_desc_init(pdata);
2756 desc_if->wrapper_rx_desc_init(pdata);
2757 xgbe_enable_dma_interrupts(pdata);
2758
2759 /*
2760 * Initialize MTL related features
2761 */
2762 xgbe_config_mtl_mode(pdata);
2763 xgbe_config_queue_mapping(pdata);
2764 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
2765 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
2766 xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
2767 xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
2768 xgbe_config_tx_fifo_size(pdata);
2769 xgbe_config_rx_fifo_size(pdata);
2770 xgbe_config_flow_control_threshold(pdata);
2771 /*TODO: Error Packet and undersized good Packet forwarding enable
2772 (FEP and FUP)
2773 */
2774 xgbe_config_dcb_tc(pdata);
2775 xgbe_config_dcb_pfc(pdata);
2776 xgbe_enable_mtl_interrupts(pdata);
2777
2778 /*
2779 * Initialize MAC related features
2780 */
2781 xgbe_config_mac_address(pdata);
2782 xgbe_config_rx_mode(pdata);
2783 xgbe_config_jumbo_enable(pdata);
2784 xgbe_config_flow_control(pdata);
2785 xgbe_config_mac_speed(pdata);
2786 xgbe_config_checksum_offload(pdata);
2787 xgbe_config_vlan_support(pdata);
2788 xgbe_config_mmc(pdata);
2789 xgbe_enable_mac_interrupts(pdata);
2790
2791 DBGPR("<--xgbe_init\n");
2792
2793 return 0;
2794 }
2795
xgbe_init_function_ptrs_dev(struct xgbe_hw_if * hw_if)2796 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
2797 {
2798 DBGPR("-->xgbe_init_function_ptrs\n");
2799
2800 hw_if->tx_complete = xgbe_tx_complete;
2801
2802 hw_if->set_mac_address = xgbe_set_mac_address;
2803 hw_if->config_rx_mode = xgbe_config_rx_mode;
2804
2805 hw_if->enable_rx_csum = xgbe_enable_rx_csum;
2806 hw_if->disable_rx_csum = xgbe_disable_rx_csum;
2807
2808 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping;
2809 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping;
2810 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering;
2811 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering;
2812 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table;
2813
2814 hw_if->read_mmd_regs = xgbe_read_mmd_regs;
2815 hw_if->write_mmd_regs = xgbe_write_mmd_regs;
2816
2817 hw_if->set_gmii_speed = xgbe_set_gmii_speed;
2818 hw_if->set_gmii_2500_speed = xgbe_set_gmii_2500_speed;
2819 hw_if->set_xgmii_speed = xgbe_set_xgmii_speed;
2820
2821 hw_if->enable_tx = xgbe_enable_tx;
2822 hw_if->disable_tx = xgbe_disable_tx;
2823 hw_if->enable_rx = xgbe_enable_rx;
2824 hw_if->disable_rx = xgbe_disable_rx;
2825
2826 hw_if->powerup_tx = xgbe_powerup_tx;
2827 hw_if->powerdown_tx = xgbe_powerdown_tx;
2828 hw_if->powerup_rx = xgbe_powerup_rx;
2829 hw_if->powerdown_rx = xgbe_powerdown_rx;
2830
2831 hw_if->dev_xmit = xgbe_dev_xmit;
2832 hw_if->dev_read = xgbe_dev_read;
2833 hw_if->enable_int = xgbe_enable_int;
2834 hw_if->disable_int = xgbe_disable_int;
2835 hw_if->init = xgbe_init;
2836 hw_if->exit = xgbe_exit;
2837
2838 /* Descriptor related Sequences have to be initialized here */
2839 hw_if->tx_desc_init = xgbe_tx_desc_init;
2840 hw_if->rx_desc_init = xgbe_rx_desc_init;
2841 hw_if->tx_desc_reset = xgbe_tx_desc_reset;
2842 hw_if->rx_desc_reset = xgbe_rx_desc_reset;
2843 hw_if->is_last_desc = xgbe_is_last_desc;
2844 hw_if->is_context_desc = xgbe_is_context_desc;
2845 hw_if->tx_start_xmit = xgbe_tx_start_xmit;
2846
2847 /* For FLOW ctrl */
2848 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control;
2849 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control;
2850
2851 /* For RX coalescing */
2852 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce;
2853 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce;
2854 hw_if->usec_to_riwt = xgbe_usec_to_riwt;
2855 hw_if->riwt_to_usec = xgbe_riwt_to_usec;
2856
2857 /* For RX and TX threshold config */
2858 hw_if->config_rx_threshold = xgbe_config_rx_threshold;
2859 hw_if->config_tx_threshold = xgbe_config_tx_threshold;
2860
2861 /* For RX and TX Store and Forward Mode config */
2862 hw_if->config_rsf_mode = xgbe_config_rsf_mode;
2863 hw_if->config_tsf_mode = xgbe_config_tsf_mode;
2864
2865 /* For TX DMA Operating on Second Frame config */
2866 hw_if->config_osp_mode = xgbe_config_osp_mode;
2867
2868 /* For RX and TX PBL config */
2869 hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val;
2870 hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val;
2871 hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val;
2872 hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val;
2873 hw_if->config_pblx8 = xgbe_config_pblx8;
2874
2875 /* For MMC statistics support */
2876 hw_if->tx_mmc_int = xgbe_tx_mmc_int;
2877 hw_if->rx_mmc_int = xgbe_rx_mmc_int;
2878 hw_if->read_mmc_stats = xgbe_read_mmc_stats;
2879
2880 /* For PTP config */
2881 hw_if->config_tstamp = xgbe_config_tstamp;
2882 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend;
2883 hw_if->set_tstamp_time = xgbe_set_tstamp_time;
2884 hw_if->get_tstamp_time = xgbe_get_tstamp_time;
2885 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp;
2886
2887 /* For Data Center Bridging config */
2888 hw_if->config_dcb_tc = xgbe_config_dcb_tc;
2889 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc;
2890
2891 /* For Receive Side Scaling */
2892 hw_if->enable_rss = xgbe_enable_rss;
2893 hw_if->disable_rss = xgbe_disable_rss;
2894 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key;
2895 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table;
2896
2897 DBGPR("<--xgbe_init_function_ptrs\n");
2898 }
2899