1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #include <linux/platform_device.h>
118 #include <linux/spinlock.h>
119 #include <linux/tcp.h>
120 #include <linux/if_vlan.h>
121 #include <net/busy_poll.h>
122 #include <linux/clk.h>
123 #include <linux/if_ether.h>
124 #include <linux/net_tstamp.h>
125 #include <linux/phy.h>
126
127 #include "xgbe.h"
128 #include "xgbe-common.h"
129
130 static int xgbe_one_poll(struct napi_struct *, int);
131 static int xgbe_all_poll(struct napi_struct *, int);
132
xgbe_alloc_channels(struct xgbe_prv_data * pdata)133 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
134 {
135 struct xgbe_channel *channel_mem, *channel;
136 struct xgbe_ring *tx_ring, *rx_ring;
137 unsigned int count, i;
138 int ret = -ENOMEM;
139
140 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
141
142 channel_mem = kcalloc(count, sizeof(struct xgbe_channel), GFP_KERNEL);
143 if (!channel_mem)
144 goto err_channel;
145
146 tx_ring = kcalloc(pdata->tx_ring_count, sizeof(struct xgbe_ring),
147 GFP_KERNEL);
148 if (!tx_ring)
149 goto err_tx_ring;
150
151 rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct xgbe_ring),
152 GFP_KERNEL);
153 if (!rx_ring)
154 goto err_rx_ring;
155
156 for (i = 0, channel = channel_mem; i < count; i++, channel++) {
157 snprintf(channel->name, sizeof(channel->name), "channel-%d", i);
158 channel->pdata = pdata;
159 channel->queue_index = i;
160 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
161 (DMA_CH_INC * i);
162
163 if (pdata->per_channel_irq) {
164 /* Get the DMA interrupt (offset 1) */
165 ret = platform_get_irq(pdata->pdev, i + 1);
166 if (ret < 0) {
167 netdev_err(pdata->netdev,
168 "platform_get_irq %u failed\n",
169 i + 1);
170 goto err_irq;
171 }
172
173 channel->dma_irq = ret;
174 }
175
176 if (i < pdata->tx_ring_count) {
177 spin_lock_init(&tx_ring->lock);
178 channel->tx_ring = tx_ring++;
179 }
180
181 if (i < pdata->rx_ring_count) {
182 spin_lock_init(&rx_ring->lock);
183 channel->rx_ring = rx_ring++;
184 }
185
186 netif_dbg(pdata, drv, pdata->netdev,
187 "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
188 channel->name, channel->dma_regs, channel->dma_irq,
189 channel->tx_ring, channel->rx_ring);
190 }
191
192 pdata->channel = channel_mem;
193 pdata->channel_count = count;
194
195 return 0;
196
197 err_irq:
198 kfree(rx_ring);
199
200 err_rx_ring:
201 kfree(tx_ring);
202
203 err_tx_ring:
204 kfree(channel_mem);
205
206 err_channel:
207 return ret;
208 }
209
xgbe_free_channels(struct xgbe_prv_data * pdata)210 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
211 {
212 if (!pdata->channel)
213 return;
214
215 kfree(pdata->channel->rx_ring);
216 kfree(pdata->channel->tx_ring);
217 kfree(pdata->channel);
218
219 pdata->channel = NULL;
220 pdata->channel_count = 0;
221 }
222
xgbe_tx_avail_desc(struct xgbe_ring * ring)223 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
224 {
225 return (ring->rdesc_count - (ring->cur - ring->dirty));
226 }
227
xgbe_rx_dirty_desc(struct xgbe_ring * ring)228 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
229 {
230 return (ring->cur - ring->dirty);
231 }
232
xgbe_maybe_stop_tx_queue(struct xgbe_channel * channel,struct xgbe_ring * ring,unsigned int count)233 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
234 struct xgbe_ring *ring, unsigned int count)
235 {
236 struct xgbe_prv_data *pdata = channel->pdata;
237
238 if (count > xgbe_tx_avail_desc(ring)) {
239 netif_info(pdata, drv, pdata->netdev,
240 "Tx queue stopped, not enough descriptors available\n");
241 netif_stop_subqueue(pdata->netdev, channel->queue_index);
242 ring->tx.queue_stopped = 1;
243
244 /* If we haven't notified the hardware because of xmit_more
245 * support, tell it now
246 */
247 if (ring->tx.xmit_more)
248 pdata->hw_if.tx_start_xmit(channel, ring);
249
250 return NETDEV_TX_BUSY;
251 }
252
253 return 0;
254 }
255
xgbe_calc_rx_buf_size(struct net_device * netdev,unsigned int mtu)256 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
257 {
258 unsigned int rx_buf_size;
259
260 if (mtu > XGMAC_JUMBO_PACKET_MTU) {
261 netdev_alert(netdev, "MTU exceeds maximum supported value\n");
262 return -EINVAL;
263 }
264
265 rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
266 rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
267
268 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
269 ~(XGBE_RX_BUF_ALIGN - 1);
270
271 return rx_buf_size;
272 }
273
xgbe_enable_rx_tx_ints(struct xgbe_prv_data * pdata)274 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
275 {
276 struct xgbe_hw_if *hw_if = &pdata->hw_if;
277 struct xgbe_channel *channel;
278 enum xgbe_int int_id;
279 unsigned int i;
280
281 channel = pdata->channel;
282 for (i = 0; i < pdata->channel_count; i++, channel++) {
283 if (channel->tx_ring && channel->rx_ring)
284 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
285 else if (channel->tx_ring)
286 int_id = XGMAC_INT_DMA_CH_SR_TI;
287 else if (channel->rx_ring)
288 int_id = XGMAC_INT_DMA_CH_SR_RI;
289 else
290 continue;
291
292 hw_if->enable_int(channel, int_id);
293 }
294 }
295
xgbe_disable_rx_tx_ints(struct xgbe_prv_data * pdata)296 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
297 {
298 struct xgbe_hw_if *hw_if = &pdata->hw_if;
299 struct xgbe_channel *channel;
300 enum xgbe_int int_id;
301 unsigned int i;
302
303 channel = pdata->channel;
304 for (i = 0; i < pdata->channel_count; i++, channel++) {
305 if (channel->tx_ring && channel->rx_ring)
306 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
307 else if (channel->tx_ring)
308 int_id = XGMAC_INT_DMA_CH_SR_TI;
309 else if (channel->rx_ring)
310 int_id = XGMAC_INT_DMA_CH_SR_RI;
311 else
312 continue;
313
314 hw_if->disable_int(channel, int_id);
315 }
316 }
317
xgbe_isr(int irq,void * data)318 static irqreturn_t xgbe_isr(int irq, void *data)
319 {
320 struct xgbe_prv_data *pdata = data;
321 struct xgbe_hw_if *hw_if = &pdata->hw_if;
322 struct xgbe_channel *channel;
323 unsigned int dma_isr, dma_ch_isr;
324 unsigned int mac_isr, mac_tssr;
325 unsigned int i;
326
327 /* The DMA interrupt status register also reports MAC and MTL
328 * interrupts. So for polling mode, we just need to check for
329 * this register to be non-zero
330 */
331 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
332 if (!dma_isr)
333 goto isr_done;
334
335 netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
336
337 for (i = 0; i < pdata->channel_count; i++) {
338 if (!(dma_isr & (1 << i)))
339 continue;
340
341 channel = pdata->channel + i;
342
343 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
344 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
345 i, dma_ch_isr);
346
347 /* The TI or RI interrupt bits may still be set even if using
348 * per channel DMA interrupts. Check to be sure those are not
349 * enabled before using the private data napi structure.
350 */
351 if (!pdata->per_channel_irq &&
352 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
353 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
354 if (napi_schedule_prep(&pdata->napi)) {
355 /* Disable Tx and Rx interrupts */
356 xgbe_disable_rx_tx_ints(pdata);
357
358 /* Turn on polling */
359 __napi_schedule(&pdata->napi);
360 }
361 }
362
363 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
364 pdata->ext_stats.rx_buffer_unavailable++;
365
366 /* Restart the device on a Fatal Bus Error */
367 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
368 schedule_work(&pdata->restart_work);
369
370 /* Clear all interrupt signals */
371 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
372 }
373
374 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
375 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
376
377 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
378 hw_if->tx_mmc_int(pdata);
379
380 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
381 hw_if->rx_mmc_int(pdata);
382
383 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
384 mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
385
386 if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
387 /* Read Tx Timestamp to clear interrupt */
388 pdata->tx_tstamp =
389 hw_if->get_tx_tstamp(pdata);
390 queue_work(pdata->dev_workqueue,
391 &pdata->tx_tstamp_work);
392 }
393 }
394 }
395
396 isr_done:
397 return IRQ_HANDLED;
398 }
399
xgbe_dma_isr(int irq,void * data)400 static irqreturn_t xgbe_dma_isr(int irq, void *data)
401 {
402 struct xgbe_channel *channel = data;
403
404 /* Per channel DMA interrupts are enabled, so we use the per
405 * channel napi structure and not the private data napi structure
406 */
407 if (napi_schedule_prep(&channel->napi)) {
408 /* Disable Tx and Rx interrupts */
409 disable_irq_nosync(channel->dma_irq);
410
411 /* Turn on polling */
412 __napi_schedule(&channel->napi);
413 }
414
415 return IRQ_HANDLED;
416 }
417
xgbe_tx_timer(unsigned long data)418 static void xgbe_tx_timer(unsigned long data)
419 {
420 struct xgbe_channel *channel = (struct xgbe_channel *)data;
421 struct xgbe_prv_data *pdata = channel->pdata;
422 struct napi_struct *napi;
423
424 DBGPR("-->xgbe_tx_timer\n");
425
426 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
427
428 if (napi_schedule_prep(napi)) {
429 /* Disable Tx and Rx interrupts */
430 if (pdata->per_channel_irq)
431 disable_irq_nosync(channel->dma_irq);
432 else
433 xgbe_disable_rx_tx_ints(pdata);
434
435 /* Turn on polling */
436 __napi_schedule(napi);
437 }
438
439 channel->tx_timer_active = 0;
440
441 DBGPR("<--xgbe_tx_timer\n");
442 }
443
xgbe_service(struct work_struct * work)444 static void xgbe_service(struct work_struct *work)
445 {
446 struct xgbe_prv_data *pdata = container_of(work,
447 struct xgbe_prv_data,
448 service_work);
449
450 pdata->phy_if.phy_status(pdata);
451 }
452
xgbe_service_timer(unsigned long data)453 static void xgbe_service_timer(unsigned long data)
454 {
455 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
456
457 queue_work(pdata->dev_workqueue, &pdata->service_work);
458
459 mod_timer(&pdata->service_timer, jiffies + HZ);
460 }
461
xgbe_init_timers(struct xgbe_prv_data * pdata)462 static void xgbe_init_timers(struct xgbe_prv_data *pdata)
463 {
464 struct xgbe_channel *channel;
465 unsigned int i;
466
467 setup_timer(&pdata->service_timer, xgbe_service_timer,
468 (unsigned long)pdata);
469
470 channel = pdata->channel;
471 for (i = 0; i < pdata->channel_count; i++, channel++) {
472 if (!channel->tx_ring)
473 break;
474
475 setup_timer(&channel->tx_timer, xgbe_tx_timer,
476 (unsigned long)channel);
477 }
478 }
479
xgbe_start_timers(struct xgbe_prv_data * pdata)480 static void xgbe_start_timers(struct xgbe_prv_data *pdata)
481 {
482 mod_timer(&pdata->service_timer, jiffies + HZ);
483 }
484
xgbe_stop_timers(struct xgbe_prv_data * pdata)485 static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
486 {
487 struct xgbe_channel *channel;
488 unsigned int i;
489
490 del_timer_sync(&pdata->service_timer);
491
492 channel = pdata->channel;
493 for (i = 0; i < pdata->channel_count; i++, channel++) {
494 if (!channel->tx_ring)
495 break;
496
497 del_timer_sync(&channel->tx_timer);
498 }
499 }
500
xgbe_get_all_hw_features(struct xgbe_prv_data * pdata)501 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
502 {
503 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
504 struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
505
506 DBGPR("-->xgbe_get_all_hw_features\n");
507
508 mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
509 mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
510 mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
511
512 memset(hw_feat, 0, sizeof(*hw_feat));
513
514 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
515
516 /* Hardware feature register 0 */
517 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
518 hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
519 hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
520 hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
521 hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
522 hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
523 hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
524 hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
525 hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
526 hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
527 hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
528 hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
529 ADDMACADRSEL);
530 hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
531 hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
532
533 /* Hardware feature register 1 */
534 hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
535 RXFIFOSIZE);
536 hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
537 TXFIFOSIZE);
538 hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
539 hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
540 hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
541 hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
542 hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
543 hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
544 hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
545 hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
546 hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
547 HASHTBLSZ);
548 hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
549 L3L4FNUM);
550
551 /* Hardware feature register 2 */
552 hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
553 hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
554 hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
555 hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
556 hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
557 hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
558
559 /* Translate the Hash Table size into actual number */
560 switch (hw_feat->hash_table_size) {
561 case 0:
562 break;
563 case 1:
564 hw_feat->hash_table_size = 64;
565 break;
566 case 2:
567 hw_feat->hash_table_size = 128;
568 break;
569 case 3:
570 hw_feat->hash_table_size = 256;
571 break;
572 }
573
574 /* Translate the address width setting into actual number */
575 switch (hw_feat->dma_width) {
576 case 0:
577 hw_feat->dma_width = 32;
578 break;
579 case 1:
580 hw_feat->dma_width = 40;
581 break;
582 case 2:
583 hw_feat->dma_width = 48;
584 break;
585 default:
586 hw_feat->dma_width = 32;
587 }
588
589 /* The Queue, Channel and TC counts are zero based so increment them
590 * to get the actual number
591 */
592 hw_feat->rx_q_cnt++;
593 hw_feat->tx_q_cnt++;
594 hw_feat->rx_ch_cnt++;
595 hw_feat->tx_ch_cnt++;
596 hw_feat->tc_cnt++;
597
598 DBGPR("<--xgbe_get_all_hw_features\n");
599 }
600
xgbe_napi_enable(struct xgbe_prv_data * pdata,unsigned int add)601 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
602 {
603 struct xgbe_channel *channel;
604 unsigned int i;
605
606 if (pdata->per_channel_irq) {
607 channel = pdata->channel;
608 for (i = 0; i < pdata->channel_count; i++, channel++) {
609 if (add)
610 netif_napi_add(pdata->netdev, &channel->napi,
611 xgbe_one_poll, NAPI_POLL_WEIGHT);
612
613 napi_enable(&channel->napi);
614 }
615 } else {
616 if (add)
617 netif_napi_add(pdata->netdev, &pdata->napi,
618 xgbe_all_poll, NAPI_POLL_WEIGHT);
619
620 napi_enable(&pdata->napi);
621 }
622 }
623
xgbe_napi_disable(struct xgbe_prv_data * pdata,unsigned int del)624 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
625 {
626 struct xgbe_channel *channel;
627 unsigned int i;
628
629 if (pdata->per_channel_irq) {
630 channel = pdata->channel;
631 for (i = 0; i < pdata->channel_count; i++, channel++) {
632 napi_disable(&channel->napi);
633
634 if (del)
635 netif_napi_del(&channel->napi);
636 }
637 } else {
638 napi_disable(&pdata->napi);
639
640 if (del)
641 netif_napi_del(&pdata->napi);
642 }
643 }
644
xgbe_request_irqs(struct xgbe_prv_data * pdata)645 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
646 {
647 struct xgbe_channel *channel;
648 struct net_device *netdev = pdata->netdev;
649 unsigned int i;
650 int ret;
651
652 ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
653 netdev->name, pdata);
654 if (ret) {
655 netdev_alert(netdev, "error requesting irq %d\n",
656 pdata->dev_irq);
657 return ret;
658 }
659
660 if (!pdata->per_channel_irq)
661 return 0;
662
663 channel = pdata->channel;
664 for (i = 0; i < pdata->channel_count; i++, channel++) {
665 snprintf(channel->dma_irq_name,
666 sizeof(channel->dma_irq_name) - 1,
667 "%s-TxRx-%u", netdev_name(netdev),
668 channel->queue_index);
669
670 ret = devm_request_irq(pdata->dev, channel->dma_irq,
671 xgbe_dma_isr, 0,
672 channel->dma_irq_name, channel);
673 if (ret) {
674 netdev_alert(netdev, "error requesting irq %d\n",
675 channel->dma_irq);
676 goto err_irq;
677 }
678 }
679
680 return 0;
681
682 err_irq:
683 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
684 for (i--, channel--; i < pdata->channel_count; i--, channel--)
685 devm_free_irq(pdata->dev, channel->dma_irq, channel);
686
687 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
688
689 return ret;
690 }
691
xgbe_free_irqs(struct xgbe_prv_data * pdata)692 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
693 {
694 struct xgbe_channel *channel;
695 unsigned int i;
696
697 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
698
699 if (!pdata->per_channel_irq)
700 return;
701
702 channel = pdata->channel;
703 for (i = 0; i < pdata->channel_count; i++, channel++)
704 devm_free_irq(pdata->dev, channel->dma_irq, channel);
705 }
706
xgbe_init_tx_coalesce(struct xgbe_prv_data * pdata)707 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
708 {
709 struct xgbe_hw_if *hw_if = &pdata->hw_if;
710
711 DBGPR("-->xgbe_init_tx_coalesce\n");
712
713 pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
714 pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
715
716 hw_if->config_tx_coalesce(pdata);
717
718 DBGPR("<--xgbe_init_tx_coalesce\n");
719 }
720
xgbe_init_rx_coalesce(struct xgbe_prv_data * pdata)721 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
722 {
723 struct xgbe_hw_if *hw_if = &pdata->hw_if;
724
725 DBGPR("-->xgbe_init_rx_coalesce\n");
726
727 pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
728 pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
729 pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
730
731 hw_if->config_rx_coalesce(pdata);
732
733 DBGPR("<--xgbe_init_rx_coalesce\n");
734 }
735
xgbe_free_tx_data(struct xgbe_prv_data * pdata)736 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
737 {
738 struct xgbe_desc_if *desc_if = &pdata->desc_if;
739 struct xgbe_channel *channel;
740 struct xgbe_ring *ring;
741 struct xgbe_ring_data *rdata;
742 unsigned int i, j;
743
744 DBGPR("-->xgbe_free_tx_data\n");
745
746 channel = pdata->channel;
747 for (i = 0; i < pdata->channel_count; i++, channel++) {
748 ring = channel->tx_ring;
749 if (!ring)
750 break;
751
752 for (j = 0; j < ring->rdesc_count; j++) {
753 rdata = XGBE_GET_DESC_DATA(ring, j);
754 desc_if->unmap_rdata(pdata, rdata);
755 }
756 }
757
758 DBGPR("<--xgbe_free_tx_data\n");
759 }
760
xgbe_free_rx_data(struct xgbe_prv_data * pdata)761 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
762 {
763 struct xgbe_desc_if *desc_if = &pdata->desc_if;
764 struct xgbe_channel *channel;
765 struct xgbe_ring *ring;
766 struct xgbe_ring_data *rdata;
767 unsigned int i, j;
768
769 DBGPR("-->xgbe_free_rx_data\n");
770
771 channel = pdata->channel;
772 for (i = 0; i < pdata->channel_count; i++, channel++) {
773 ring = channel->rx_ring;
774 if (!ring)
775 break;
776
777 for (j = 0; j < ring->rdesc_count; j++) {
778 rdata = XGBE_GET_DESC_DATA(ring, j);
779 desc_if->unmap_rdata(pdata, rdata);
780 }
781 }
782
783 DBGPR("<--xgbe_free_rx_data\n");
784 }
785
xgbe_phy_init(struct xgbe_prv_data * pdata)786 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
787 {
788 pdata->phy_link = -1;
789 pdata->phy_speed = SPEED_UNKNOWN;
790
791 return pdata->phy_if.phy_reset(pdata);
792 }
793
xgbe_powerdown(struct net_device * netdev,unsigned int caller)794 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
795 {
796 struct xgbe_prv_data *pdata = netdev_priv(netdev);
797 struct xgbe_hw_if *hw_if = &pdata->hw_if;
798 unsigned long flags;
799
800 DBGPR("-->xgbe_powerdown\n");
801
802 if (!netif_running(netdev) ||
803 (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
804 netdev_alert(netdev, "Device is already powered down\n");
805 DBGPR("<--xgbe_powerdown\n");
806 return -EINVAL;
807 }
808
809 spin_lock_irqsave(&pdata->lock, flags);
810
811 if (caller == XGMAC_DRIVER_CONTEXT)
812 netif_device_detach(netdev);
813
814 netif_tx_stop_all_queues(netdev);
815
816 xgbe_stop_timers(pdata);
817 flush_workqueue(pdata->dev_workqueue);
818
819 hw_if->powerdown_tx(pdata);
820 hw_if->powerdown_rx(pdata);
821
822 xgbe_napi_disable(pdata, 0);
823
824 pdata->power_down = 1;
825
826 spin_unlock_irqrestore(&pdata->lock, flags);
827
828 DBGPR("<--xgbe_powerdown\n");
829
830 return 0;
831 }
832
xgbe_powerup(struct net_device * netdev,unsigned int caller)833 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
834 {
835 struct xgbe_prv_data *pdata = netdev_priv(netdev);
836 struct xgbe_hw_if *hw_if = &pdata->hw_if;
837 unsigned long flags;
838
839 DBGPR("-->xgbe_powerup\n");
840
841 if (!netif_running(netdev) ||
842 (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
843 netdev_alert(netdev, "Device is already powered up\n");
844 DBGPR("<--xgbe_powerup\n");
845 return -EINVAL;
846 }
847
848 spin_lock_irqsave(&pdata->lock, flags);
849
850 pdata->power_down = 0;
851
852 xgbe_napi_enable(pdata, 0);
853
854 hw_if->powerup_tx(pdata);
855 hw_if->powerup_rx(pdata);
856
857 if (caller == XGMAC_DRIVER_CONTEXT)
858 netif_device_attach(netdev);
859
860 netif_tx_start_all_queues(netdev);
861
862 xgbe_start_timers(pdata);
863
864 spin_unlock_irqrestore(&pdata->lock, flags);
865
866 DBGPR("<--xgbe_powerup\n");
867
868 return 0;
869 }
870
xgbe_start(struct xgbe_prv_data * pdata)871 static int xgbe_start(struct xgbe_prv_data *pdata)
872 {
873 struct xgbe_hw_if *hw_if = &pdata->hw_if;
874 struct xgbe_phy_if *phy_if = &pdata->phy_if;
875 struct net_device *netdev = pdata->netdev;
876 int ret;
877
878 DBGPR("-->xgbe_start\n");
879
880 ret = hw_if->init(pdata);
881 if (ret)
882 return ret;
883
884 ret = phy_if->phy_start(pdata);
885 if (ret)
886 goto err_phy;
887
888 xgbe_napi_enable(pdata, 1);
889
890 ret = xgbe_request_irqs(pdata);
891 if (ret)
892 goto err_napi;
893
894 hw_if->enable_tx(pdata);
895 hw_if->enable_rx(pdata);
896
897 netif_tx_start_all_queues(netdev);
898
899 xgbe_start_timers(pdata);
900 queue_work(pdata->dev_workqueue, &pdata->service_work);
901
902 DBGPR("<--xgbe_start\n");
903
904 return 0;
905
906 err_napi:
907 xgbe_napi_disable(pdata, 1);
908
909 phy_if->phy_stop(pdata);
910
911 err_phy:
912 hw_if->exit(pdata);
913
914 return ret;
915 }
916
xgbe_stop(struct xgbe_prv_data * pdata)917 static void xgbe_stop(struct xgbe_prv_data *pdata)
918 {
919 struct xgbe_hw_if *hw_if = &pdata->hw_if;
920 struct xgbe_phy_if *phy_if = &pdata->phy_if;
921 struct xgbe_channel *channel;
922 struct net_device *netdev = pdata->netdev;
923 struct netdev_queue *txq;
924 unsigned int i;
925
926 DBGPR("-->xgbe_stop\n");
927
928 netif_tx_stop_all_queues(netdev);
929
930 xgbe_stop_timers(pdata);
931 flush_workqueue(pdata->dev_workqueue);
932
933 hw_if->disable_tx(pdata);
934 hw_if->disable_rx(pdata);
935
936 xgbe_free_irqs(pdata);
937
938 xgbe_napi_disable(pdata, 1);
939
940 phy_if->phy_stop(pdata);
941
942 hw_if->exit(pdata);
943
944 channel = pdata->channel;
945 for (i = 0; i < pdata->channel_count; i++, channel++) {
946 if (!channel->tx_ring)
947 continue;
948
949 txq = netdev_get_tx_queue(netdev, channel->queue_index);
950 netdev_tx_reset_queue(txq);
951 }
952
953 DBGPR("<--xgbe_stop\n");
954 }
955
xgbe_restart_dev(struct xgbe_prv_data * pdata)956 static void xgbe_restart_dev(struct xgbe_prv_data *pdata)
957 {
958 DBGPR("-->xgbe_restart_dev\n");
959
960 /* If not running, "restart" will happen on open */
961 if (!netif_running(pdata->netdev))
962 return;
963
964 xgbe_stop(pdata);
965
966 xgbe_free_tx_data(pdata);
967 xgbe_free_rx_data(pdata);
968
969 xgbe_start(pdata);
970
971 DBGPR("<--xgbe_restart_dev\n");
972 }
973
xgbe_restart(struct work_struct * work)974 static void xgbe_restart(struct work_struct *work)
975 {
976 struct xgbe_prv_data *pdata = container_of(work,
977 struct xgbe_prv_data,
978 restart_work);
979
980 rtnl_lock();
981
982 xgbe_restart_dev(pdata);
983
984 rtnl_unlock();
985 }
986
xgbe_tx_tstamp(struct work_struct * work)987 static void xgbe_tx_tstamp(struct work_struct *work)
988 {
989 struct xgbe_prv_data *pdata = container_of(work,
990 struct xgbe_prv_data,
991 tx_tstamp_work);
992 struct skb_shared_hwtstamps hwtstamps;
993 u64 nsec;
994 unsigned long flags;
995
996 if (pdata->tx_tstamp) {
997 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
998 pdata->tx_tstamp);
999
1000 memset(&hwtstamps, 0, sizeof(hwtstamps));
1001 hwtstamps.hwtstamp = ns_to_ktime(nsec);
1002 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
1003 }
1004
1005 dev_kfree_skb_any(pdata->tx_tstamp_skb);
1006
1007 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1008 pdata->tx_tstamp_skb = NULL;
1009 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1010 }
1011
xgbe_get_hwtstamp_settings(struct xgbe_prv_data * pdata,struct ifreq * ifreq)1012 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1013 struct ifreq *ifreq)
1014 {
1015 if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1016 sizeof(pdata->tstamp_config)))
1017 return -EFAULT;
1018
1019 return 0;
1020 }
1021
xgbe_set_hwtstamp_settings(struct xgbe_prv_data * pdata,struct ifreq * ifreq)1022 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1023 struct ifreq *ifreq)
1024 {
1025 struct hwtstamp_config config;
1026 unsigned int mac_tscr;
1027
1028 if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1029 return -EFAULT;
1030
1031 if (config.flags)
1032 return -EINVAL;
1033
1034 mac_tscr = 0;
1035
1036 switch (config.tx_type) {
1037 case HWTSTAMP_TX_OFF:
1038 break;
1039
1040 case HWTSTAMP_TX_ON:
1041 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1042 break;
1043
1044 default:
1045 return -ERANGE;
1046 }
1047
1048 switch (config.rx_filter) {
1049 case HWTSTAMP_FILTER_NONE:
1050 break;
1051
1052 case HWTSTAMP_FILTER_ALL:
1053 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1054 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1055 break;
1056
1057 /* PTP v2, UDP, any kind of event packet */
1058 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1059 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1060 /* PTP v1, UDP, any kind of event packet */
1061 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1062 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1063 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1064 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1065 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1066 break;
1067
1068 /* PTP v2, UDP, Sync packet */
1069 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1070 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1071 /* PTP v1, UDP, Sync packet */
1072 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1073 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1074 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1075 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1076 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1077 break;
1078
1079 /* PTP v2, UDP, Delay_req packet */
1080 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1081 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1082 /* PTP v1, UDP, Delay_req packet */
1083 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1084 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1085 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1086 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1087 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1088 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1089 break;
1090
1091 /* 802.AS1, Ethernet, any kind of event packet */
1092 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1093 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1094 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1095 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1096 break;
1097
1098 /* 802.AS1, Ethernet, Sync packet */
1099 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1100 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1101 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1102 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1103 break;
1104
1105 /* 802.AS1, Ethernet, Delay_req packet */
1106 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1107 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1108 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1109 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1110 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1111 break;
1112
1113 /* PTP v2/802.AS1, any layer, any kind of event packet */
1114 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1115 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1116 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1117 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1118 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1119 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1120 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1121 break;
1122
1123 /* PTP v2/802.AS1, any layer, Sync packet */
1124 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1125 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1126 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1127 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1128 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1129 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1130 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1131 break;
1132
1133 /* PTP v2/802.AS1, any layer, Delay_req packet */
1134 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1135 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1136 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1137 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1138 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1139 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1140 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1141 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1142 break;
1143
1144 default:
1145 return -ERANGE;
1146 }
1147
1148 pdata->hw_if.config_tstamp(pdata, mac_tscr);
1149
1150 memcpy(&pdata->tstamp_config, &config, sizeof(config));
1151
1152 return 0;
1153 }
1154
xgbe_prep_tx_tstamp(struct xgbe_prv_data * pdata,struct sk_buff * skb,struct xgbe_packet_data * packet)1155 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1156 struct sk_buff *skb,
1157 struct xgbe_packet_data *packet)
1158 {
1159 unsigned long flags;
1160
1161 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1162 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1163 if (pdata->tx_tstamp_skb) {
1164 /* Another timestamp in progress, ignore this one */
1165 XGMAC_SET_BITS(packet->attributes,
1166 TX_PACKET_ATTRIBUTES, PTP, 0);
1167 } else {
1168 pdata->tx_tstamp_skb = skb_get(skb);
1169 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1170 }
1171 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1172 }
1173
1174 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1175 skb_tx_timestamp(skb);
1176 }
1177
xgbe_prep_vlan(struct sk_buff * skb,struct xgbe_packet_data * packet)1178 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1179 {
1180 if (skb_vlan_tag_present(skb))
1181 packet->vlan_ctag = skb_vlan_tag_get(skb);
1182 }
1183
xgbe_prep_tso(struct sk_buff * skb,struct xgbe_packet_data * packet)1184 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1185 {
1186 int ret;
1187
1188 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1189 TSO_ENABLE))
1190 return 0;
1191
1192 ret = skb_cow_head(skb, 0);
1193 if (ret)
1194 return ret;
1195
1196 packet->header_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1197 packet->tcp_header_len = tcp_hdrlen(skb);
1198 packet->tcp_payload_len = skb->len - packet->header_len;
1199 packet->mss = skb_shinfo(skb)->gso_size;
1200 DBGPR(" packet->header_len=%u\n", packet->header_len);
1201 DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1202 packet->tcp_header_len, packet->tcp_payload_len);
1203 DBGPR(" packet->mss=%u\n", packet->mss);
1204
1205 /* Update the number of packets that will ultimately be transmitted
1206 * along with the extra bytes for each extra packet
1207 */
1208 packet->tx_packets = skb_shinfo(skb)->gso_segs;
1209 packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1210
1211 return 0;
1212 }
1213
xgbe_is_tso(struct sk_buff * skb)1214 static int xgbe_is_tso(struct sk_buff *skb)
1215 {
1216 if (skb->ip_summed != CHECKSUM_PARTIAL)
1217 return 0;
1218
1219 if (!skb_is_gso(skb))
1220 return 0;
1221
1222 DBGPR(" TSO packet to be processed\n");
1223
1224 return 1;
1225 }
1226
xgbe_packet_info(struct xgbe_prv_data * pdata,struct xgbe_ring * ring,struct sk_buff * skb,struct xgbe_packet_data * packet)1227 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1228 struct xgbe_ring *ring, struct sk_buff *skb,
1229 struct xgbe_packet_data *packet)
1230 {
1231 struct skb_frag_struct *frag;
1232 unsigned int context_desc;
1233 unsigned int len;
1234 unsigned int i;
1235
1236 packet->skb = skb;
1237
1238 context_desc = 0;
1239 packet->rdesc_count = 0;
1240
1241 packet->tx_packets = 1;
1242 packet->tx_bytes = skb->len;
1243
1244 if (xgbe_is_tso(skb)) {
1245 /* TSO requires an extra descriptor if mss is different */
1246 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1247 context_desc = 1;
1248 packet->rdesc_count++;
1249 }
1250
1251 /* TSO requires an extra descriptor for TSO header */
1252 packet->rdesc_count++;
1253
1254 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1255 TSO_ENABLE, 1);
1256 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1257 CSUM_ENABLE, 1);
1258 } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1259 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1260 CSUM_ENABLE, 1);
1261
1262 if (skb_vlan_tag_present(skb)) {
1263 /* VLAN requires an extra descriptor if tag is different */
1264 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
1265 /* We can share with the TSO context descriptor */
1266 if (!context_desc) {
1267 context_desc = 1;
1268 packet->rdesc_count++;
1269 }
1270
1271 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1272 VLAN_CTAG, 1);
1273 }
1274
1275 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1276 (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1277 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1278 PTP, 1);
1279
1280 for (len = skb_headlen(skb); len;) {
1281 packet->rdesc_count++;
1282 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1283 }
1284
1285 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1286 frag = &skb_shinfo(skb)->frags[i];
1287 for (len = skb_frag_size(frag); len; ) {
1288 packet->rdesc_count++;
1289 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1290 }
1291 }
1292 }
1293
xgbe_open(struct net_device * netdev)1294 static int xgbe_open(struct net_device *netdev)
1295 {
1296 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1297 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1298 int ret;
1299
1300 DBGPR("-->xgbe_open\n");
1301
1302 /* Initialize the phy */
1303 ret = xgbe_phy_init(pdata);
1304 if (ret)
1305 return ret;
1306
1307 /* Enable the clocks */
1308 ret = clk_prepare_enable(pdata->sysclk);
1309 if (ret) {
1310 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1311 return ret;
1312 }
1313
1314 ret = clk_prepare_enable(pdata->ptpclk);
1315 if (ret) {
1316 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1317 goto err_sysclk;
1318 }
1319
1320 /* Calculate the Rx buffer size before allocating rings */
1321 ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1322 if (ret < 0)
1323 goto err_ptpclk;
1324 pdata->rx_buf_size = ret;
1325
1326 /* Allocate the channel and ring structures */
1327 ret = xgbe_alloc_channels(pdata);
1328 if (ret)
1329 goto err_ptpclk;
1330
1331 /* Allocate the ring descriptors and buffers */
1332 ret = desc_if->alloc_ring_resources(pdata);
1333 if (ret)
1334 goto err_channels;
1335
1336 INIT_WORK(&pdata->service_work, xgbe_service);
1337 INIT_WORK(&pdata->restart_work, xgbe_restart);
1338 INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1339 xgbe_init_timers(pdata);
1340
1341 ret = xgbe_start(pdata);
1342 if (ret)
1343 goto err_rings;
1344
1345 clear_bit(XGBE_DOWN, &pdata->dev_state);
1346
1347 DBGPR("<--xgbe_open\n");
1348
1349 return 0;
1350
1351 err_rings:
1352 desc_if->free_ring_resources(pdata);
1353
1354 err_channels:
1355 xgbe_free_channels(pdata);
1356
1357 err_ptpclk:
1358 clk_disable_unprepare(pdata->ptpclk);
1359
1360 err_sysclk:
1361 clk_disable_unprepare(pdata->sysclk);
1362
1363 return ret;
1364 }
1365
xgbe_close(struct net_device * netdev)1366 static int xgbe_close(struct net_device *netdev)
1367 {
1368 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1369 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1370
1371 DBGPR("-->xgbe_close\n");
1372
1373 /* Stop the device */
1374 xgbe_stop(pdata);
1375
1376 /* Free the ring descriptors and buffers */
1377 desc_if->free_ring_resources(pdata);
1378
1379 /* Free the channel and ring structures */
1380 xgbe_free_channels(pdata);
1381
1382 /* Disable the clocks */
1383 clk_disable_unprepare(pdata->ptpclk);
1384 clk_disable_unprepare(pdata->sysclk);
1385
1386 set_bit(XGBE_DOWN, &pdata->dev_state);
1387
1388 DBGPR("<--xgbe_close\n");
1389
1390 return 0;
1391 }
1392
xgbe_xmit(struct sk_buff * skb,struct net_device * netdev)1393 static netdev_tx_t xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
1394 {
1395 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1396 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1397 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1398 struct xgbe_channel *channel;
1399 struct xgbe_ring *ring;
1400 struct xgbe_packet_data *packet;
1401 struct netdev_queue *txq;
1402 netdev_tx_t ret;
1403
1404 DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1405
1406 channel = pdata->channel + skb->queue_mapping;
1407 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1408 ring = channel->tx_ring;
1409 packet = &ring->packet_data;
1410
1411 ret = NETDEV_TX_OK;
1412
1413 if (skb->len == 0) {
1414 netif_err(pdata, tx_err, netdev,
1415 "empty skb received from stack\n");
1416 dev_kfree_skb_any(skb);
1417 goto tx_netdev_return;
1418 }
1419
1420 /* Calculate preliminary packet info */
1421 memset(packet, 0, sizeof(*packet));
1422 xgbe_packet_info(pdata, ring, skb, packet);
1423
1424 /* Check that there are enough descriptors available */
1425 ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
1426 if (ret)
1427 goto tx_netdev_return;
1428
1429 ret = xgbe_prep_tso(skb, packet);
1430 if (ret) {
1431 netif_err(pdata, tx_err, netdev,
1432 "error processing TSO packet\n");
1433 dev_kfree_skb_any(skb);
1434 goto tx_netdev_return;
1435 }
1436 xgbe_prep_vlan(skb, packet);
1437
1438 if (!desc_if->map_tx_skb(channel, skb)) {
1439 dev_kfree_skb_any(skb);
1440 goto tx_netdev_return;
1441 }
1442
1443 xgbe_prep_tx_tstamp(pdata, skb, packet);
1444
1445 /* Report on the actual number of bytes (to be) sent */
1446 netdev_tx_sent_queue(txq, packet->tx_bytes);
1447
1448 /* Configure required descriptor fields for transmission */
1449 hw_if->dev_xmit(channel);
1450
1451 if (netif_msg_pktdata(pdata))
1452 xgbe_print_pkt(netdev, skb, true);
1453
1454 /* Stop the queue in advance if there may not be enough descriptors */
1455 xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
1456
1457 ret = NETDEV_TX_OK;
1458
1459 tx_netdev_return:
1460 return ret;
1461 }
1462
xgbe_set_rx_mode(struct net_device * netdev)1463 static void xgbe_set_rx_mode(struct net_device *netdev)
1464 {
1465 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1466 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1467
1468 DBGPR("-->xgbe_set_rx_mode\n");
1469
1470 hw_if->config_rx_mode(pdata);
1471
1472 DBGPR("<--xgbe_set_rx_mode\n");
1473 }
1474
xgbe_set_mac_address(struct net_device * netdev,void * addr)1475 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
1476 {
1477 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1478 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1479 struct sockaddr *saddr = addr;
1480
1481 DBGPR("-->xgbe_set_mac_address\n");
1482
1483 if (!is_valid_ether_addr(saddr->sa_data))
1484 return -EADDRNOTAVAIL;
1485
1486 memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len);
1487
1488 hw_if->set_mac_address(pdata, netdev->dev_addr);
1489
1490 DBGPR("<--xgbe_set_mac_address\n");
1491
1492 return 0;
1493 }
1494
xgbe_ioctl(struct net_device * netdev,struct ifreq * ifreq,int cmd)1495 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
1496 {
1497 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1498 int ret;
1499
1500 switch (cmd) {
1501 case SIOCGHWTSTAMP:
1502 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
1503 break;
1504
1505 case SIOCSHWTSTAMP:
1506 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
1507 break;
1508
1509 default:
1510 ret = -EOPNOTSUPP;
1511 }
1512
1513 return ret;
1514 }
1515
xgbe_change_mtu(struct net_device * netdev,int mtu)1516 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
1517 {
1518 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1519 int ret;
1520
1521 DBGPR("-->xgbe_change_mtu\n");
1522
1523 ret = xgbe_calc_rx_buf_size(netdev, mtu);
1524 if (ret < 0)
1525 return ret;
1526
1527 pdata->rx_buf_size = ret;
1528 netdev->mtu = mtu;
1529
1530 xgbe_restart_dev(pdata);
1531
1532 DBGPR("<--xgbe_change_mtu\n");
1533
1534 return 0;
1535 }
1536
xgbe_tx_timeout(struct net_device * netdev)1537 static void xgbe_tx_timeout(struct net_device *netdev)
1538 {
1539 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1540
1541 netdev_warn(netdev, "tx timeout, device restarting\n");
1542 schedule_work(&pdata->restart_work);
1543 }
1544
xgbe_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * s)1545 static struct rtnl_link_stats64 *xgbe_get_stats64(struct net_device *netdev,
1546 struct rtnl_link_stats64 *s)
1547 {
1548 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1549 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
1550
1551 DBGPR("-->%s\n", __func__);
1552
1553 pdata->hw_if.read_mmc_stats(pdata);
1554
1555 s->rx_packets = pstats->rxframecount_gb;
1556 s->rx_bytes = pstats->rxoctetcount_gb;
1557 s->rx_errors = pstats->rxframecount_gb -
1558 pstats->rxbroadcastframes_g -
1559 pstats->rxmulticastframes_g -
1560 pstats->rxunicastframes_g;
1561 s->multicast = pstats->rxmulticastframes_g;
1562 s->rx_length_errors = pstats->rxlengtherror;
1563 s->rx_crc_errors = pstats->rxcrcerror;
1564 s->rx_fifo_errors = pstats->rxfifooverflow;
1565
1566 s->tx_packets = pstats->txframecount_gb;
1567 s->tx_bytes = pstats->txoctetcount_gb;
1568 s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
1569 s->tx_dropped = netdev->stats.tx_dropped;
1570
1571 DBGPR("<--%s\n", __func__);
1572
1573 return s;
1574 }
1575
xgbe_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)1576 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
1577 u16 vid)
1578 {
1579 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1580 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1581
1582 DBGPR("-->%s\n", __func__);
1583
1584 set_bit(vid, pdata->active_vlans);
1585 hw_if->update_vlan_hash_table(pdata);
1586
1587 DBGPR("<--%s\n", __func__);
1588
1589 return 0;
1590 }
1591
xgbe_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)1592 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
1593 u16 vid)
1594 {
1595 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1596 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1597
1598 DBGPR("-->%s\n", __func__);
1599
1600 clear_bit(vid, pdata->active_vlans);
1601 hw_if->update_vlan_hash_table(pdata);
1602
1603 DBGPR("<--%s\n", __func__);
1604
1605 return 0;
1606 }
1607
1608 #ifdef CONFIG_NET_POLL_CONTROLLER
xgbe_poll_controller(struct net_device * netdev)1609 static void xgbe_poll_controller(struct net_device *netdev)
1610 {
1611 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1612 struct xgbe_channel *channel;
1613 unsigned int i;
1614
1615 DBGPR("-->xgbe_poll_controller\n");
1616
1617 if (pdata->per_channel_irq) {
1618 channel = pdata->channel;
1619 for (i = 0; i < pdata->channel_count; i++, channel++)
1620 xgbe_dma_isr(channel->dma_irq, channel);
1621 } else {
1622 disable_irq(pdata->dev_irq);
1623 xgbe_isr(pdata->dev_irq, pdata);
1624 enable_irq(pdata->dev_irq);
1625 }
1626
1627 DBGPR("<--xgbe_poll_controller\n");
1628 }
1629 #endif /* End CONFIG_NET_POLL_CONTROLLER */
1630
xgbe_setup_tc(struct net_device * netdev,u8 tc)1631 static int xgbe_setup_tc(struct net_device *netdev, u8 tc)
1632 {
1633 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1634 unsigned int offset, queue;
1635 u8 i;
1636
1637 if (tc && (tc != pdata->hw_feat.tc_cnt))
1638 return -EINVAL;
1639
1640 if (tc) {
1641 netdev_set_num_tc(netdev, tc);
1642 for (i = 0, queue = 0, offset = 0; i < tc; i++) {
1643 while ((queue < pdata->tx_q_count) &&
1644 (pdata->q2tc_map[queue] == i))
1645 queue++;
1646
1647 netif_dbg(pdata, drv, netdev, "TC%u using TXq%u-%u\n",
1648 i, offset, queue - 1);
1649 netdev_set_tc_queue(netdev, i, queue - offset, offset);
1650 offset = queue;
1651 }
1652 } else {
1653 netdev_reset_tc(netdev);
1654 }
1655
1656 return 0;
1657 }
1658
xgbe_set_features(struct net_device * netdev,netdev_features_t features)1659 static int xgbe_set_features(struct net_device *netdev,
1660 netdev_features_t features)
1661 {
1662 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1663 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1664 netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
1665 int ret = 0;
1666
1667 rxhash = pdata->netdev_features & NETIF_F_RXHASH;
1668 rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
1669 rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
1670 rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
1671
1672 if ((features & NETIF_F_RXHASH) && !rxhash)
1673 ret = hw_if->enable_rss(pdata);
1674 else if (!(features & NETIF_F_RXHASH) && rxhash)
1675 ret = hw_if->disable_rss(pdata);
1676 if (ret)
1677 return ret;
1678
1679 if ((features & NETIF_F_RXCSUM) && !rxcsum)
1680 hw_if->enable_rx_csum(pdata);
1681 else if (!(features & NETIF_F_RXCSUM) && rxcsum)
1682 hw_if->disable_rx_csum(pdata);
1683
1684 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
1685 hw_if->enable_rx_vlan_stripping(pdata);
1686 else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
1687 hw_if->disable_rx_vlan_stripping(pdata);
1688
1689 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
1690 hw_if->enable_rx_vlan_filtering(pdata);
1691 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
1692 hw_if->disable_rx_vlan_filtering(pdata);
1693
1694 pdata->netdev_features = features;
1695
1696 DBGPR("<--xgbe_set_features\n");
1697
1698 return 0;
1699 }
1700
1701 static const struct net_device_ops xgbe_netdev_ops = {
1702 .ndo_open = xgbe_open,
1703 .ndo_stop = xgbe_close,
1704 .ndo_start_xmit = xgbe_xmit,
1705 .ndo_set_rx_mode = xgbe_set_rx_mode,
1706 .ndo_set_mac_address = xgbe_set_mac_address,
1707 .ndo_validate_addr = eth_validate_addr,
1708 .ndo_do_ioctl = xgbe_ioctl,
1709 .ndo_change_mtu = xgbe_change_mtu,
1710 .ndo_tx_timeout = xgbe_tx_timeout,
1711 .ndo_get_stats64 = xgbe_get_stats64,
1712 .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid,
1713 .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid,
1714 #ifdef CONFIG_NET_POLL_CONTROLLER
1715 .ndo_poll_controller = xgbe_poll_controller,
1716 #endif
1717 .ndo_setup_tc = xgbe_setup_tc,
1718 .ndo_set_features = xgbe_set_features,
1719 };
1720
xgbe_get_netdev_ops(void)1721 struct net_device_ops *xgbe_get_netdev_ops(void)
1722 {
1723 return (struct net_device_ops *)&xgbe_netdev_ops;
1724 }
1725
xgbe_rx_refresh(struct xgbe_channel * channel)1726 static void xgbe_rx_refresh(struct xgbe_channel *channel)
1727 {
1728 struct xgbe_prv_data *pdata = channel->pdata;
1729 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1730 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1731 struct xgbe_ring *ring = channel->rx_ring;
1732 struct xgbe_ring_data *rdata;
1733
1734 while (ring->dirty != ring->cur) {
1735 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
1736
1737 /* Reset rdata values */
1738 desc_if->unmap_rdata(pdata, rdata);
1739
1740 if (desc_if->map_rx_buffer(pdata, ring, rdata))
1741 break;
1742
1743 hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
1744
1745 ring->dirty++;
1746 }
1747
1748 /* Make sure everything is written before the register write */
1749 wmb();
1750
1751 /* Update the Rx Tail Pointer Register with address of
1752 * the last cleaned entry */
1753 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
1754 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1755 lower_32_bits(rdata->rdesc_dma));
1756 }
1757
xgbe_create_skb(struct xgbe_prv_data * pdata,struct napi_struct * napi,struct xgbe_ring_data * rdata,unsigned int len)1758 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
1759 struct napi_struct *napi,
1760 struct xgbe_ring_data *rdata,
1761 unsigned int len)
1762 {
1763 struct sk_buff *skb;
1764 u8 *packet;
1765
1766 skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
1767 if (!skb)
1768 return NULL;
1769
1770 /* Pull in the header buffer which may contain just the header
1771 * or the header plus data
1772 */
1773 dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
1774 rdata->rx.hdr.dma_off,
1775 rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
1776
1777 packet = page_address(rdata->rx.hdr.pa.pages) +
1778 rdata->rx.hdr.pa.pages_offset;
1779 skb_copy_to_linear_data(skb, packet, len);
1780 skb_put(skb, len);
1781
1782 return skb;
1783 }
1784
xgbe_rx_buf1_len(struct xgbe_ring_data * rdata,struct xgbe_packet_data * packet)1785 static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata,
1786 struct xgbe_packet_data *packet)
1787 {
1788 /* Always zero if not the first descriptor */
1789 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST))
1790 return 0;
1791
1792 /* First descriptor with split header, return header length */
1793 if (rdata->rx.hdr_len)
1794 return rdata->rx.hdr_len;
1795
1796 /* First descriptor but not the last descriptor and no split header,
1797 * so the full buffer was used
1798 */
1799 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
1800 return rdata->rx.hdr.dma_len;
1801
1802 /* First descriptor and last descriptor and no split header, so
1803 * calculate how much of the buffer was used
1804 */
1805 return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len);
1806 }
1807
xgbe_rx_buf2_len(struct xgbe_ring_data * rdata,struct xgbe_packet_data * packet,unsigned int len)1808 static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata,
1809 struct xgbe_packet_data *packet,
1810 unsigned int len)
1811 {
1812 /* Always the full buffer if not the last descriptor */
1813 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
1814 return rdata->rx.buf.dma_len;
1815
1816 /* Last descriptor so calculate how much of the buffer was used
1817 * for the last bit of data
1818 */
1819 return rdata->rx.len - len;
1820 }
1821
xgbe_tx_poll(struct xgbe_channel * channel)1822 static int xgbe_tx_poll(struct xgbe_channel *channel)
1823 {
1824 struct xgbe_prv_data *pdata = channel->pdata;
1825 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1826 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1827 struct xgbe_ring *ring = channel->tx_ring;
1828 struct xgbe_ring_data *rdata;
1829 struct xgbe_ring_desc *rdesc;
1830 struct net_device *netdev = pdata->netdev;
1831 struct netdev_queue *txq;
1832 int processed = 0;
1833 unsigned int tx_packets = 0, tx_bytes = 0;
1834 unsigned int cur;
1835
1836 DBGPR("-->xgbe_tx_poll\n");
1837
1838 /* Nothing to do if there isn't a Tx ring for this channel */
1839 if (!ring)
1840 return 0;
1841
1842 cur = ring->cur;
1843
1844 /* Be sure we get ring->cur before accessing descriptor data */
1845 smp_rmb();
1846
1847 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1848
1849 while ((processed < XGBE_TX_DESC_MAX_PROC) &&
1850 (ring->dirty != cur)) {
1851 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
1852 rdesc = rdata->rdesc;
1853
1854 if (!hw_if->tx_complete(rdesc))
1855 break;
1856
1857 /* Make sure descriptor fields are read after reading the OWN
1858 * bit */
1859 dma_rmb();
1860
1861 if (netif_msg_tx_done(pdata))
1862 xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
1863
1864 if (hw_if->is_last_desc(rdesc)) {
1865 tx_packets += rdata->tx.packets;
1866 tx_bytes += rdata->tx.bytes;
1867 }
1868
1869 /* Free the SKB and reset the descriptor for re-use */
1870 desc_if->unmap_rdata(pdata, rdata);
1871 hw_if->tx_desc_reset(rdata);
1872
1873 processed++;
1874 ring->dirty++;
1875 }
1876
1877 if (!processed)
1878 return 0;
1879
1880 netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
1881
1882 if ((ring->tx.queue_stopped == 1) &&
1883 (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
1884 ring->tx.queue_stopped = 0;
1885 netif_tx_wake_queue(txq);
1886 }
1887
1888 DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
1889
1890 return processed;
1891 }
1892
xgbe_rx_poll(struct xgbe_channel * channel,int budget)1893 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
1894 {
1895 struct xgbe_prv_data *pdata = channel->pdata;
1896 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1897 struct xgbe_ring *ring = channel->rx_ring;
1898 struct xgbe_ring_data *rdata;
1899 struct xgbe_packet_data *packet;
1900 struct net_device *netdev = pdata->netdev;
1901 struct napi_struct *napi;
1902 struct sk_buff *skb;
1903 struct skb_shared_hwtstamps *hwtstamps;
1904 unsigned int last, error, context_next, context;
1905 unsigned int len, buf1_len, buf2_len, max_len;
1906 unsigned int received = 0;
1907 int packet_count = 0;
1908
1909 DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
1910
1911 /* Nothing to do if there isn't a Rx ring for this channel */
1912 if (!ring)
1913 return 0;
1914
1915 last = 0;
1916 context_next = 0;
1917
1918 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
1919
1920 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1921 packet = &ring->packet_data;
1922 while (packet_count < budget) {
1923 DBGPR(" cur = %d\n", ring->cur);
1924
1925 /* First time in loop see if we need to restore state */
1926 if (!received && rdata->state_saved) {
1927 skb = rdata->state.skb;
1928 error = rdata->state.error;
1929 len = rdata->state.len;
1930 } else {
1931 memset(packet, 0, sizeof(*packet));
1932 skb = NULL;
1933 error = 0;
1934 len = 0;
1935 }
1936
1937 read_again:
1938 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1939
1940 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
1941 xgbe_rx_refresh(channel);
1942
1943 if (hw_if->dev_read(channel))
1944 break;
1945
1946 received++;
1947 ring->cur++;
1948
1949 last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1950 LAST);
1951 context_next = XGMAC_GET_BITS(packet->attributes,
1952 RX_PACKET_ATTRIBUTES,
1953 CONTEXT_NEXT);
1954 context = XGMAC_GET_BITS(packet->attributes,
1955 RX_PACKET_ATTRIBUTES,
1956 CONTEXT);
1957
1958 /* Earlier error, just drain the remaining data */
1959 if ((!last || context_next) && error)
1960 goto read_again;
1961
1962 if (error || packet->errors) {
1963 if (packet->errors)
1964 netif_err(pdata, rx_err, netdev,
1965 "error in received packet\n");
1966 dev_kfree_skb(skb);
1967 goto next_packet;
1968 }
1969
1970 if (!context) {
1971 /* Get the data length in the descriptor buffers */
1972 buf1_len = xgbe_rx_buf1_len(rdata, packet);
1973 len += buf1_len;
1974 buf2_len = xgbe_rx_buf2_len(rdata, packet, len);
1975 len += buf2_len;
1976
1977 if (!skb) {
1978 skb = xgbe_create_skb(pdata, napi, rdata,
1979 buf1_len);
1980 if (!skb) {
1981 error = 1;
1982 goto skip_data;
1983 }
1984 }
1985
1986 if (buf2_len) {
1987 dma_sync_single_range_for_cpu(pdata->dev,
1988 rdata->rx.buf.dma_base,
1989 rdata->rx.buf.dma_off,
1990 rdata->rx.buf.dma_len,
1991 DMA_FROM_DEVICE);
1992
1993 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1994 rdata->rx.buf.pa.pages,
1995 rdata->rx.buf.pa.pages_offset,
1996 buf2_len,
1997 rdata->rx.buf.dma_len);
1998 rdata->rx.buf.pa.pages = NULL;
1999 }
2000 }
2001
2002 skip_data:
2003 if (!last || context_next)
2004 goto read_again;
2005
2006 if (!skb)
2007 goto next_packet;
2008
2009 /* Be sure we don't exceed the configured MTU */
2010 max_len = netdev->mtu + ETH_HLEN;
2011 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2012 (skb->protocol == htons(ETH_P_8021Q)))
2013 max_len += VLAN_HLEN;
2014
2015 if (skb->len > max_len) {
2016 netif_err(pdata, rx_err, netdev,
2017 "packet length exceeds configured MTU\n");
2018 dev_kfree_skb(skb);
2019 goto next_packet;
2020 }
2021
2022 if (netif_msg_pktdata(pdata))
2023 xgbe_print_pkt(netdev, skb, false);
2024
2025 skb_checksum_none_assert(skb);
2026 if (XGMAC_GET_BITS(packet->attributes,
2027 RX_PACKET_ATTRIBUTES, CSUM_DONE))
2028 skb->ip_summed = CHECKSUM_UNNECESSARY;
2029
2030 if (XGMAC_GET_BITS(packet->attributes,
2031 RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2032 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2033 packet->vlan_ctag);
2034
2035 if (XGMAC_GET_BITS(packet->attributes,
2036 RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2037 u64 nsec;
2038
2039 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2040 packet->rx_tstamp);
2041 hwtstamps = skb_hwtstamps(skb);
2042 hwtstamps->hwtstamp = ns_to_ktime(nsec);
2043 }
2044
2045 if (XGMAC_GET_BITS(packet->attributes,
2046 RX_PACKET_ATTRIBUTES, RSS_HASH))
2047 skb_set_hash(skb, packet->rss_hash,
2048 packet->rss_hash_type);
2049
2050 skb->dev = netdev;
2051 skb->protocol = eth_type_trans(skb, netdev);
2052 skb_record_rx_queue(skb, channel->queue_index);
2053 skb_mark_napi_id(skb, napi);
2054
2055 napi_gro_receive(napi, skb);
2056
2057 next_packet:
2058 packet_count++;
2059 }
2060
2061 /* Check if we need to save state before leaving */
2062 if (received && (!last || context_next)) {
2063 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2064 rdata->state_saved = 1;
2065 rdata->state.skb = skb;
2066 rdata->state.len = len;
2067 rdata->state.error = error;
2068 }
2069
2070 DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2071
2072 return packet_count;
2073 }
2074
xgbe_one_poll(struct napi_struct * napi,int budget)2075 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2076 {
2077 struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2078 napi);
2079 int processed = 0;
2080
2081 DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2082
2083 /* Cleanup Tx ring first */
2084 xgbe_tx_poll(channel);
2085
2086 /* Process Rx ring next */
2087 processed = xgbe_rx_poll(channel, budget);
2088
2089 /* If we processed everything, we are done */
2090 if (processed < budget) {
2091 /* Turn off polling */
2092 napi_complete(napi);
2093
2094 /* Enable Tx and Rx interrupts */
2095 enable_irq(channel->dma_irq);
2096 }
2097
2098 DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2099
2100 return processed;
2101 }
2102
xgbe_all_poll(struct napi_struct * napi,int budget)2103 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2104 {
2105 struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2106 napi);
2107 struct xgbe_channel *channel;
2108 int ring_budget;
2109 int processed, last_processed;
2110 unsigned int i;
2111
2112 DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2113
2114 processed = 0;
2115 ring_budget = budget / pdata->rx_ring_count;
2116 do {
2117 last_processed = processed;
2118
2119 channel = pdata->channel;
2120 for (i = 0; i < pdata->channel_count; i++, channel++) {
2121 /* Cleanup Tx ring first */
2122 xgbe_tx_poll(channel);
2123
2124 /* Process Rx ring next */
2125 if (ring_budget > (budget - processed))
2126 ring_budget = budget - processed;
2127 processed += xgbe_rx_poll(channel, ring_budget);
2128 }
2129 } while ((processed < budget) && (processed != last_processed));
2130
2131 /* If we processed everything, we are done */
2132 if (processed < budget) {
2133 /* Turn off polling */
2134 napi_complete(napi);
2135
2136 /* Enable Tx and Rx interrupts */
2137 xgbe_enable_rx_tx_ints(pdata);
2138 }
2139
2140 DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2141
2142 return processed;
2143 }
2144
xgbe_dump_tx_desc(struct xgbe_prv_data * pdata,struct xgbe_ring * ring,unsigned int idx,unsigned int count,unsigned int flag)2145 void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2146 unsigned int idx, unsigned int count, unsigned int flag)
2147 {
2148 struct xgbe_ring_data *rdata;
2149 struct xgbe_ring_desc *rdesc;
2150
2151 while (count--) {
2152 rdata = XGBE_GET_DESC_DATA(ring, idx);
2153 rdesc = rdata->rdesc;
2154 netdev_dbg(pdata->netdev,
2155 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2156 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2157 le32_to_cpu(rdesc->desc0),
2158 le32_to_cpu(rdesc->desc1),
2159 le32_to_cpu(rdesc->desc2),
2160 le32_to_cpu(rdesc->desc3));
2161 idx++;
2162 }
2163 }
2164
xgbe_dump_rx_desc(struct xgbe_prv_data * pdata,struct xgbe_ring * ring,unsigned int idx)2165 void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2166 unsigned int idx)
2167 {
2168 struct xgbe_ring_data *rdata;
2169 struct xgbe_ring_desc *rdesc;
2170
2171 rdata = XGBE_GET_DESC_DATA(ring, idx);
2172 rdesc = rdata->rdesc;
2173 netdev_dbg(pdata->netdev,
2174 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2175 idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2176 le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2177 }
2178
xgbe_print_pkt(struct net_device * netdev,struct sk_buff * skb,bool tx_rx)2179 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2180 {
2181 struct ethhdr *eth = (struct ethhdr *)skb->data;
2182 unsigned char *buf = skb->data;
2183 unsigned char buffer[128];
2184 unsigned int i, j;
2185
2186 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2187
2188 netdev_dbg(netdev, "%s packet of %d bytes\n",
2189 (tx_rx ? "TX" : "RX"), skb->len);
2190
2191 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2192 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
2193 netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
2194
2195 for (i = 0, j = 0; i < skb->len;) {
2196 j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx",
2197 buf[i++]);
2198
2199 if ((i % 32) == 0) {
2200 netdev_dbg(netdev, " %#06x: %s\n", i - 32, buffer);
2201 j = 0;
2202 } else if ((i % 16) == 0) {
2203 buffer[j++] = ' ';
2204 buffer[j++] = ' ';
2205 } else if ((i % 4) == 0) {
2206 buffer[j++] = ' ';
2207 }
2208 }
2209 if (i % 32)
2210 netdev_dbg(netdev, " %#06x: %s\n", i - (i % 32), buffer);
2211
2212 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
2213 }
2214