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1 /*
2  * include/asm-xtensa/coprocessor.h
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 2003 - 2007 Tensilica Inc.
9  */
10 
11 
12 #ifndef _XTENSA_COPROCESSOR_H
13 #define _XTENSA_COPROCESSOR_H
14 
15 #include <linux/stringify.h>
16 #include <variant/core.h>
17 #include <variant/tie.h>
18 #include <asm/types.h>
19 
20 #ifdef __ASSEMBLY__
21 # include <variant/tie-asm.h>
22 
23 .macro	xchal_sa_start  a b
24 	.set .Lxchal_pofs_, 0
25 	.set .Lxchal_ofs_, 0
26 .endm
27 
28 .macro	xchal_sa_align  ptr minofs maxofs ofsalign totalign
29 	.set	.Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ + \totalign - 1
30 	.set	.Lxchal_ofs_, (.Lxchal_ofs_ & -\totalign) - .Lxchal_pofs_
31 .endm
32 
33 #define _SELECT	(  XTHAL_SAS_TIE | XTHAL_SAS_OPT \
34 		 | XTHAL_SAS_CC \
35 		 | XTHAL_SAS_CALR | XTHAL_SAS_CALE )
36 
37 .macro save_xtregs_opt ptr clb at1 at2 at3 at4 offset
38 	.if XTREGS_OPT_SIZE > 0
39 		addi	\clb, \ptr, \offset
40 		xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
41 	.endif
42 .endm
43 
44 .macro load_xtregs_opt ptr clb at1 at2 at3 at4 offset
45 	.if XTREGS_OPT_SIZE > 0
46 		addi	\clb, \ptr, \offset
47 		xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
48 	.endif
49 .endm
50 #undef _SELECT
51 
52 #define _SELECT	(  XTHAL_SAS_TIE | XTHAL_SAS_OPT \
53 		 | XTHAL_SAS_NOCC \
54 		 | XTHAL_SAS_CALR | XTHAL_SAS_CALE | XTHAL_SAS_GLOB )
55 
56 .macro save_xtregs_user ptr clb at1 at2 at3 at4 offset
57 	.if XTREGS_USER_SIZE > 0
58 		addi	\clb, \ptr, \offset
59 		xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
60 	.endif
61 .endm
62 
63 .macro load_xtregs_user ptr clb at1 at2 at3 at4 offset
64 	.if XTREGS_USER_SIZE > 0
65 		addi	\clb, \ptr, \offset
66 		xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
67 	.endif
68 .endm
69 #undef _SELECT
70 
71 
72 
73 #endif	/* __ASSEMBLY__ */
74 
75 /*
76  * XTENSA_HAVE_COPROCESSOR(x) returns 1 if coprocessor x is configured.
77  *
78  * XTENSA_HAVE_IO_PORT(x) returns 1 if io-port x is configured.
79  *
80  */
81 
82 #define XTENSA_HAVE_COPROCESSOR(x)					\
83 	((XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK) & (1 << (x)))
84 #define XTENSA_HAVE_COPROCESSORS					\
85 	(XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK)
86 #define XTENSA_HAVE_IO_PORT(x)						\
87 	(XCHAL_CP_PORT_MASK & (1 << (x)))
88 #define XTENSA_HAVE_IO_PORTS						\
89 	XCHAL_CP_PORT_MASK
90 
91 #ifndef __ASSEMBLY__
92 
93 
94 #if XCHAL_HAVE_CP
95 
96 #define RSR_CPENABLE(x)	do {						  \
97 	__asm__ __volatile__("rsr %0, cpenable" : "=a" (x));		  \
98 	} while(0);
99 #define WSR_CPENABLE(x)	do {						  \
100 	__asm__ __volatile__("wsr %0, cpenable; rsync" :: "a" (x));	  \
101 	} while(0);
102 
103 #endif /* XCHAL_HAVE_CP */
104 
105 
106 /*
107  * Additional registers.
108  * We define three types of additional registers:
109  *  ext: extra registers that are used by the compiler
110  *  cpn: optional registers that can be used by a user application
111  *  cpX: coprocessor registers that can only be used if the corresponding
112  *       CPENABLE bit is set.
113  */
114 
115 #define XCHAL_SA_REG(list,cc,abi,type,y,name,z,align,size,...)	\
116 	__REG ## list (cc, abi, type, name, size, align)
117 
118 #define __REG0(cc,abi,t,name,s,a)	__REG0_ ## cc (abi,name)
119 #define __REG1(cc,abi,t,name,s,a)	__REG1_ ## cc (name)
120 #define __REG2(cc,abi,type,...)		__REG2_ ## type (__VA_ARGS__)
121 
122 #define __REG0_0(abi,name)
123 #define __REG0_1(abi,name)		__REG0_1 ## abi (name)
124 #define __REG0_10(name)	__u32 name;
125 #define __REG0_11(name)	__u32 name;
126 #define __REG0_12(name)
127 
128 #define __REG1_0(name)	__u32 name;
129 #define __REG1_1(name)
130 
131 #define __REG2_0(n,s,a)	__u32 name;
132 #define __REG2_1(n,s,a)	unsigned char n[s] __attribute__ ((aligned(a)));
133 #define __REG2_2(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));
134 
135 typedef struct { XCHAL_NCP_SA_LIST(0) } xtregs_opt_t
136 	__attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
137 typedef struct { XCHAL_NCP_SA_LIST(1) } xtregs_user_t
138 	__attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
139 
140 #if XTENSA_HAVE_COPROCESSORS
141 
142 typedef struct { XCHAL_CP0_SA_LIST(2) } xtregs_cp0_t
143 	__attribute__ ((aligned (XCHAL_CP0_SA_ALIGN)));
144 typedef struct { XCHAL_CP1_SA_LIST(2) } xtregs_cp1_t
145 	__attribute__ ((aligned (XCHAL_CP1_SA_ALIGN)));
146 typedef struct { XCHAL_CP2_SA_LIST(2) } xtregs_cp2_t
147 	__attribute__ ((aligned (XCHAL_CP2_SA_ALIGN)));
148 typedef struct { XCHAL_CP3_SA_LIST(2) } xtregs_cp3_t
149 	__attribute__ ((aligned (XCHAL_CP3_SA_ALIGN)));
150 typedef struct { XCHAL_CP4_SA_LIST(2) } xtregs_cp4_t
151 	__attribute__ ((aligned (XCHAL_CP4_SA_ALIGN)));
152 typedef struct { XCHAL_CP5_SA_LIST(2) } xtregs_cp5_t
153 	__attribute__ ((aligned (XCHAL_CP5_SA_ALIGN)));
154 typedef struct { XCHAL_CP6_SA_LIST(2) } xtregs_cp6_t
155 	__attribute__ ((aligned (XCHAL_CP6_SA_ALIGN)));
156 typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t
157 	__attribute__ ((aligned (XCHAL_CP7_SA_ALIGN)));
158 
159 extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX];
160 extern void coprocessor_save(void*, int);
161 extern void coprocessor_load(void*, int);
162 extern void coprocessor_flush(struct thread_info*, int);
163 extern void coprocessor_restore(struct thread_info*, int);
164 
165 extern void coprocessor_release_all(struct thread_info*);
166 extern void coprocessor_flush_all(struct thread_info*);
167 
coprocessor_clear_cpenable(void)168 static inline void coprocessor_clear_cpenable(void)
169 {
170 	unsigned long i = 0;
171 	WSR_CPENABLE(i);
172 }
173 
174 #endif	/* XTENSA_HAVE_COPROCESSORS */
175 
176 #endif	/* !__ASSEMBLY__ */
177 #endif	/* _XTENSA_COPROCESSOR_H */
178