1 /*
2 * s390 specific pci instructions
3 *
4 * Copyright IBM Corp. 2013
5 */
6
7 #include <linux/export.h>
8 #include <linux/errno.h>
9 #include <linux/delay.h>
10 #include <asm/facility.h>
11 #include <asm/pci_insn.h>
12 #include <asm/pci_debug.h>
13 #include <asm/processor.h>
14
15 #define ZPCI_INSN_BUSY_DELAY 1 /* 1 microsecond */
16
zpci_err_insn(u8 cc,u8 status,u64 req,u64 offset)17 static inline void zpci_err_insn(u8 cc, u8 status, u64 req, u64 offset)
18 {
19 struct {
20 u64 req;
21 u64 offset;
22 u8 cc;
23 u8 status;
24 } __packed data = {req, offset, cc, status};
25
26 zpci_err_hex(&data, sizeof(data));
27 }
28
29 /* Modify PCI Function Controls */
__mpcifc(u64 req,struct zpci_fib * fib,u8 * status)30 static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
31 {
32 u8 cc;
33
34 asm volatile (
35 " .insn rxy,0xe300000000d0,%[req],%[fib]\n"
36 " ipm %[cc]\n"
37 " srl %[cc],28\n"
38 : [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
39 : : "cc");
40 *status = req >> 24 & 0xff;
41 return cc;
42 }
43
zpci_mod_fc(u64 req,struct zpci_fib * fib)44 int zpci_mod_fc(u64 req, struct zpci_fib *fib)
45 {
46 u8 cc, status;
47
48 do {
49 cc = __mpcifc(req, fib, &status);
50 if (cc == 2)
51 msleep(ZPCI_INSN_BUSY_DELAY);
52 } while (cc == 2);
53
54 if (cc)
55 zpci_err_insn(cc, status, req, 0);
56
57 return (cc) ? -EIO : 0;
58 }
59
60 /* Refresh PCI Translations */
__rpcit(u64 fn,u64 addr,u64 range,u8 * status)61 static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
62 {
63 register u64 __addr asm("2") = addr;
64 register u64 __range asm("3") = range;
65 u8 cc;
66
67 asm volatile (
68 " .insn rre,0xb9d30000,%[fn],%[addr]\n"
69 " ipm %[cc]\n"
70 " srl %[cc],28\n"
71 : [cc] "=d" (cc), [fn] "+d" (fn)
72 : [addr] "d" (__addr), "d" (__range)
73 : "cc");
74 *status = fn >> 24 & 0xff;
75 return cc;
76 }
77
zpci_refresh_trans(u64 fn,u64 addr,u64 range)78 int zpci_refresh_trans(u64 fn, u64 addr, u64 range)
79 {
80 u8 cc, status;
81
82 do {
83 cc = __rpcit(fn, addr, range, &status);
84 if (cc == 2)
85 udelay(ZPCI_INSN_BUSY_DELAY);
86 } while (cc == 2);
87
88 if (cc)
89 zpci_err_insn(cc, status, addr, range);
90
91 return (cc) ? -EIO : 0;
92 }
93
94 /* Set Interruption Controls */
zpci_set_irq_ctrl(u16 ctl,char * unused,u8 isc)95 int zpci_set_irq_ctrl(u16 ctl, char *unused, u8 isc)
96 {
97 if (!test_facility(72))
98 return -EIO;
99 asm volatile (
100 " .insn rsy,0xeb00000000d1,%[ctl],%[isc],%[u]\n"
101 : : [ctl] "d" (ctl), [isc] "d" (isc << 27), [u] "Q" (*unused));
102 return 0;
103 }
104
105 /* PCI Load */
__pcilg(u64 * data,u64 req,u64 offset,u8 * status)106 static inline int __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
107 {
108 register u64 __req asm("2") = req;
109 register u64 __offset asm("3") = offset;
110 int cc = -ENXIO;
111 u64 __data;
112
113 asm volatile (
114 " .insn rre,0xb9d20000,%[data],%[req]\n"
115 "0: ipm %[cc]\n"
116 " srl %[cc],28\n"
117 "1:\n"
118 EX_TABLE(0b, 1b)
119 : [cc] "+d" (cc), [data] "=d" (__data), [req] "+d" (__req)
120 : "d" (__offset)
121 : "cc");
122 *status = __req >> 24 & 0xff;
123 if (!cc)
124 *data = __data;
125
126 return cc;
127 }
128
zpci_load(u64 * data,u64 req,u64 offset)129 int zpci_load(u64 *data, u64 req, u64 offset)
130 {
131 u8 status;
132 int cc;
133
134 do {
135 cc = __pcilg(data, req, offset, &status);
136 if (cc == 2)
137 udelay(ZPCI_INSN_BUSY_DELAY);
138 } while (cc == 2);
139
140 if (cc)
141 zpci_err_insn(cc, status, req, offset);
142
143 return (cc > 0) ? -EIO : cc;
144 }
145 EXPORT_SYMBOL_GPL(zpci_load);
146
147 /* PCI Store */
__pcistg(u64 data,u64 req,u64 offset,u8 * status)148 static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status)
149 {
150 register u64 __req asm("2") = req;
151 register u64 __offset asm("3") = offset;
152 int cc = -ENXIO;
153
154 asm volatile (
155 " .insn rre,0xb9d00000,%[data],%[req]\n"
156 "0: ipm %[cc]\n"
157 " srl %[cc],28\n"
158 "1:\n"
159 EX_TABLE(0b, 1b)
160 : [cc] "+d" (cc), [req] "+d" (__req)
161 : "d" (__offset), [data] "d" (data)
162 : "cc");
163 *status = __req >> 24 & 0xff;
164 return cc;
165 }
166
zpci_store(u64 data,u64 req,u64 offset)167 int zpci_store(u64 data, u64 req, u64 offset)
168 {
169 u8 status;
170 int cc;
171
172 do {
173 cc = __pcistg(data, req, offset, &status);
174 if (cc == 2)
175 udelay(ZPCI_INSN_BUSY_DELAY);
176 } while (cc == 2);
177
178 if (cc)
179 zpci_err_insn(cc, status, req, offset);
180
181 return (cc > 0) ? -EIO : cc;
182 }
183 EXPORT_SYMBOL_GPL(zpci_store);
184
185 /* PCI Store Block */
__pcistb(const u64 * data,u64 req,u64 offset,u8 * status)186 static inline int __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
187 {
188 int cc = -ENXIO;
189
190 asm volatile (
191 " .insn rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
192 "0: ipm %[cc]\n"
193 " srl %[cc],28\n"
194 "1:\n"
195 EX_TABLE(0b, 1b)
196 : [cc] "+d" (cc), [req] "+d" (req)
197 : [offset] "d" (offset), [data] "Q" (*data)
198 : "cc");
199 *status = req >> 24 & 0xff;
200 return cc;
201 }
202
zpci_store_block(const u64 * data,u64 req,u64 offset)203 int zpci_store_block(const u64 *data, u64 req, u64 offset)
204 {
205 u8 status;
206 int cc;
207
208 do {
209 cc = __pcistb(data, req, offset, &status);
210 if (cc == 2)
211 udelay(ZPCI_INSN_BUSY_DELAY);
212 } while (cc == 2);
213
214 if (cc)
215 zpci_err_insn(cc, status, req, offset);
216
217 return (cc > 0) ? -EIO : cc;
218 }
219 EXPORT_SYMBOL_GPL(zpci_store_block);
220