1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/amdgpu_drm.h>
28 #include "amdgpu.h"
29 #include "amdgpu_i2c.h"
30 #include "atom.h"
31 #include "amdgpu_connectors.h"
32 #include <asm/div64.h>
33
34 #include <linux/pm_runtime.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37
amdgpu_flip_wait_fence(struct amdgpu_device * adev,struct fence ** f)38 static void amdgpu_flip_wait_fence(struct amdgpu_device *adev,
39 struct fence **f)
40 {
41 struct amdgpu_fence *fence;
42 long r;
43
44 if (*f == NULL)
45 return;
46
47 fence = to_amdgpu_fence(*f);
48 if (fence) {
49 r = fence_wait(&fence->base, false);
50 if (r == -EDEADLK)
51 r = amdgpu_gpu_reset(adev);
52 } else
53 r = fence_wait(*f, false);
54
55 if (r)
56 DRM_ERROR("failed to wait on page flip fence (%ld)!\n", r);
57
58 /* We continue with the page flip even if we failed to wait on
59 * the fence, otherwise the DRM core and userspace will be
60 * confused about which BO the CRTC is scanning out
61 */
62 fence_put(*f);
63 *f = NULL;
64 }
65
amdgpu_flip_work_func(struct work_struct * __work)66 static void amdgpu_flip_work_func(struct work_struct *__work)
67 {
68 struct amdgpu_flip_work *work =
69 container_of(__work, struct amdgpu_flip_work, flip_work);
70 struct amdgpu_device *adev = work->adev;
71 struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id];
72
73 struct drm_crtc *crtc = &amdgpuCrtc->base;
74 unsigned long flags;
75 unsigned i, repcnt = 4;
76 int vpos, hpos, stat, min_udelay = 0;
77 struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id];
78
79 amdgpu_flip_wait_fence(adev, &work->excl);
80 for (i = 0; i < work->shared_count; ++i)
81 amdgpu_flip_wait_fence(adev, &work->shared[i]);
82
83 /* We borrow the event spin lock for protecting flip_status */
84 spin_lock_irqsave(&crtc->dev->event_lock, flags);
85
86 /* If this happens to execute within the "virtually extended" vblank
87 * interval before the start of the real vblank interval then it needs
88 * to delay programming the mmio flip until the real vblank is entered.
89 * This prevents completing a flip too early due to the way we fudge
90 * our vblank counter and vblank timestamps in order to work around the
91 * problem that the hw fires vblank interrupts before actual start of
92 * vblank (when line buffer refilling is done for a frame). It
93 * complements the fudging logic in amdgpu_get_crtc_scanoutpos() for
94 * timestamping and amdgpu_get_vblank_counter_kms() for vblank counts.
95 *
96 * In practice this won't execute very often unless on very fast
97 * machines because the time window for this to happen is very small.
98 */
99 while (amdgpuCrtc->enabled && --repcnt) {
100 /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank
101 * start in hpos, and to the "fudged earlier" vblank start in
102 * vpos.
103 */
104 stat = amdgpu_get_crtc_scanoutpos(adev->ddev, work->crtc_id,
105 GET_DISTANCE_TO_VBLANKSTART,
106 &vpos, &hpos, NULL, NULL,
107 &crtc->hwmode);
108
109 if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
110 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) ||
111 !(vpos >= 0 && hpos <= 0))
112 break;
113
114 /* Sleep at least until estimated real start of hw vblank */
115 min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5);
116 if (min_udelay > vblank->framedur_ns / 2000) {
117 /* Don't wait ridiculously long - something is wrong */
118 repcnt = 0;
119 break;
120 }
121 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
122 usleep_range(min_udelay, 2 * min_udelay);
123 spin_lock_irqsave(&crtc->dev->event_lock, flags);
124 };
125
126 if (!repcnt)
127 DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, "
128 "framedur %d, linedur %d, stat %d, vpos %d, "
129 "hpos %d\n", work->crtc_id, min_udelay,
130 vblank->framedur_ns / 1000,
131 vblank->linedur_ns / 1000, stat, vpos, hpos);
132
133 /* do the flip (mmio) */
134 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base);
135 /* set the flip status */
136 amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
137
138 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
139 }
140
141 /*
142 * Handle unpin events outside the interrupt handler proper.
143 */
amdgpu_unpin_work_func(struct work_struct * __work)144 static void amdgpu_unpin_work_func(struct work_struct *__work)
145 {
146 struct amdgpu_flip_work *work =
147 container_of(__work, struct amdgpu_flip_work, unpin_work);
148 int r;
149
150 /* unpin of the old buffer */
151 r = amdgpu_bo_reserve(work->old_rbo, false);
152 if (likely(r == 0)) {
153 r = amdgpu_bo_unpin(work->old_rbo);
154 if (unlikely(r != 0)) {
155 DRM_ERROR("failed to unpin buffer after flip\n");
156 }
157 amdgpu_bo_unreserve(work->old_rbo);
158 } else
159 DRM_ERROR("failed to reserve buffer after flip\n");
160
161 amdgpu_bo_unref(&work->old_rbo);
162 kfree(work->shared);
163 kfree(work);
164 }
165
amdgpu_crtc_page_flip(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event,uint32_t page_flip_flags)166 int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
167 struct drm_framebuffer *fb,
168 struct drm_pending_vblank_event *event,
169 uint32_t page_flip_flags)
170 {
171 struct drm_device *dev = crtc->dev;
172 struct amdgpu_device *adev = dev->dev_private;
173 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
174 struct amdgpu_framebuffer *old_amdgpu_fb;
175 struct amdgpu_framebuffer *new_amdgpu_fb;
176 struct drm_gem_object *obj;
177 struct amdgpu_flip_work *work;
178 struct amdgpu_bo *new_rbo;
179 unsigned long flags;
180 u64 tiling_flags;
181 u64 base;
182 int i, r;
183
184 work = kzalloc(sizeof *work, GFP_KERNEL);
185 if (work == NULL)
186 return -ENOMEM;
187
188 INIT_WORK(&work->flip_work, amdgpu_flip_work_func);
189 INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func);
190
191 work->event = event;
192 work->adev = adev;
193 work->crtc_id = amdgpu_crtc->crtc_id;
194
195 /* schedule unpin of the old buffer */
196 old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
197 obj = old_amdgpu_fb->obj;
198
199 /* take a reference to the old object */
200 work->old_rbo = gem_to_amdgpu_bo(obj);
201 amdgpu_bo_ref(work->old_rbo);
202
203 new_amdgpu_fb = to_amdgpu_framebuffer(fb);
204 obj = new_amdgpu_fb->obj;
205 new_rbo = gem_to_amdgpu_bo(obj);
206
207 /* pin the new buffer */
208 r = amdgpu_bo_reserve(new_rbo, false);
209 if (unlikely(r != 0)) {
210 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
211 goto cleanup;
212 }
213
214 r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base);
215 if (unlikely(r != 0)) {
216 amdgpu_bo_unreserve(new_rbo);
217 r = -EINVAL;
218 DRM_ERROR("failed to pin new rbo buffer before flip\n");
219 goto cleanup;
220 }
221
222 r = reservation_object_get_fences_rcu(new_rbo->tbo.resv, &work->excl,
223 &work->shared_count,
224 &work->shared);
225 if (unlikely(r != 0)) {
226 amdgpu_bo_unreserve(new_rbo);
227 DRM_ERROR("failed to get fences for buffer\n");
228 goto cleanup;
229 }
230
231 amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags);
232 amdgpu_bo_unreserve(new_rbo);
233
234 work->base = base;
235
236 r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id);
237 if (r) {
238 DRM_ERROR("failed to get vblank before flip\n");
239 goto pflip_cleanup;
240 }
241
242 /* we borrow the event spin lock for protecting flip_wrok */
243 spin_lock_irqsave(&crtc->dev->event_lock, flags);
244 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
245 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
246 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
247 r = -EBUSY;
248 goto vblank_cleanup;
249 }
250
251 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
252 amdgpu_crtc->pflip_works = work;
253
254 /* update crtc fb */
255 crtc->primary->fb = fb;
256 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
257 queue_work(amdgpu_crtc->pflip_queue, &work->flip_work);
258 return 0;
259
260 vblank_cleanup:
261 drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id);
262
263 pflip_cleanup:
264 if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) {
265 DRM_ERROR("failed to reserve new rbo in error path\n");
266 goto cleanup;
267 }
268 if (unlikely(amdgpu_bo_unpin(new_rbo) != 0)) {
269 DRM_ERROR("failed to unpin new rbo in error path\n");
270 }
271 amdgpu_bo_unreserve(new_rbo);
272
273 cleanup:
274 amdgpu_bo_unref(&work->old_rbo);
275 fence_put(work->excl);
276 for (i = 0; i < work->shared_count; ++i)
277 fence_put(work->shared[i]);
278 kfree(work->shared);
279 kfree(work);
280
281 return r;
282 }
283
amdgpu_crtc_set_config(struct drm_mode_set * set)284 int amdgpu_crtc_set_config(struct drm_mode_set *set)
285 {
286 struct drm_device *dev;
287 struct amdgpu_device *adev;
288 struct drm_crtc *crtc;
289 bool active = false;
290 int ret;
291
292 if (!set || !set->crtc)
293 return -EINVAL;
294
295 dev = set->crtc->dev;
296
297 ret = pm_runtime_get_sync(dev->dev);
298 if (ret < 0)
299 goto out;
300
301 ret = drm_crtc_helper_set_config(set);
302
303 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
304 if (crtc->enabled)
305 active = true;
306
307 pm_runtime_mark_last_busy(dev->dev);
308
309 adev = dev->dev_private;
310 /* if we have active crtcs and we don't have a power ref,
311 take the current one */
312 if (active && !adev->have_disp_power_ref) {
313 adev->have_disp_power_ref = true;
314 return ret;
315 }
316 /* if we have no active crtcs, then drop the power ref
317 we got before */
318 if (!active && adev->have_disp_power_ref) {
319 pm_runtime_put_autosuspend(dev->dev);
320 adev->have_disp_power_ref = false;
321 }
322
323 out:
324 /* drop the power reference we got coming in here */
325 pm_runtime_put_autosuspend(dev->dev);
326 return ret;
327 }
328
329 static const char *encoder_names[38] = {
330 "NONE",
331 "INTERNAL_LVDS",
332 "INTERNAL_TMDS1",
333 "INTERNAL_TMDS2",
334 "INTERNAL_DAC1",
335 "INTERNAL_DAC2",
336 "INTERNAL_SDVOA",
337 "INTERNAL_SDVOB",
338 "SI170B",
339 "CH7303",
340 "CH7301",
341 "INTERNAL_DVO1",
342 "EXTERNAL_SDVOA",
343 "EXTERNAL_SDVOB",
344 "TITFP513",
345 "INTERNAL_LVTM1",
346 "VT1623",
347 "HDMI_SI1930",
348 "HDMI_INTERNAL",
349 "INTERNAL_KLDSCP_TMDS1",
350 "INTERNAL_KLDSCP_DVO1",
351 "INTERNAL_KLDSCP_DAC1",
352 "INTERNAL_KLDSCP_DAC2",
353 "SI178",
354 "MVPU_FPGA",
355 "INTERNAL_DDI",
356 "VT1625",
357 "HDMI_SI1932",
358 "DP_AN9801",
359 "DP_DP501",
360 "INTERNAL_UNIPHY",
361 "INTERNAL_KLDSCP_LVTMA",
362 "INTERNAL_UNIPHY1",
363 "INTERNAL_UNIPHY2",
364 "NUTMEG",
365 "TRAVIS",
366 "INTERNAL_VCE",
367 "INTERNAL_UNIPHY3",
368 };
369
370 static const char *hpd_names[6] = {
371 "HPD1",
372 "HPD2",
373 "HPD3",
374 "HPD4",
375 "HPD5",
376 "HPD6",
377 };
378
amdgpu_print_display_setup(struct drm_device * dev)379 void amdgpu_print_display_setup(struct drm_device *dev)
380 {
381 struct drm_connector *connector;
382 struct amdgpu_connector *amdgpu_connector;
383 struct drm_encoder *encoder;
384 struct amdgpu_encoder *amdgpu_encoder;
385 uint32_t devices;
386 int i = 0;
387
388 DRM_INFO("AMDGPU Display Connectors\n");
389 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
390 amdgpu_connector = to_amdgpu_connector(connector);
391 DRM_INFO("Connector %d:\n", i);
392 DRM_INFO(" %s\n", connector->name);
393 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
394 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
395 if (amdgpu_connector->ddc_bus) {
396 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
397 amdgpu_connector->ddc_bus->rec.mask_clk_reg,
398 amdgpu_connector->ddc_bus->rec.mask_data_reg,
399 amdgpu_connector->ddc_bus->rec.a_clk_reg,
400 amdgpu_connector->ddc_bus->rec.a_data_reg,
401 amdgpu_connector->ddc_bus->rec.en_clk_reg,
402 amdgpu_connector->ddc_bus->rec.en_data_reg,
403 amdgpu_connector->ddc_bus->rec.y_clk_reg,
404 amdgpu_connector->ddc_bus->rec.y_data_reg);
405 if (amdgpu_connector->router.ddc_valid)
406 DRM_INFO(" DDC Router 0x%x/0x%x\n",
407 amdgpu_connector->router.ddc_mux_control_pin,
408 amdgpu_connector->router.ddc_mux_state);
409 if (amdgpu_connector->router.cd_valid)
410 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
411 amdgpu_connector->router.cd_mux_control_pin,
412 amdgpu_connector->router.cd_mux_state);
413 } else {
414 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
415 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
416 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
417 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
418 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
419 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
420 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
421 }
422 DRM_INFO(" Encoders:\n");
423 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
424 amdgpu_encoder = to_amdgpu_encoder(encoder);
425 devices = amdgpu_encoder->devices & amdgpu_connector->devices;
426 if (devices) {
427 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
428 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
429 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
430 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
431 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
432 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
433 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
434 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
435 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
436 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
437 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
438 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
439 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
440 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
441 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
442 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
443 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
444 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
445 if (devices & ATOM_DEVICE_TV1_SUPPORT)
446 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
447 if (devices & ATOM_DEVICE_CV_SUPPORT)
448 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
449 }
450 }
451 i++;
452 }
453 }
454
455 /**
456 * amdgpu_ddc_probe
457 *
458 */
amdgpu_ddc_probe(struct amdgpu_connector * amdgpu_connector,bool use_aux)459 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector,
460 bool use_aux)
461 {
462 u8 out = 0x0;
463 u8 buf[8];
464 int ret;
465 struct i2c_msg msgs[] = {
466 {
467 .addr = DDC_ADDR,
468 .flags = 0,
469 .len = 1,
470 .buf = &out,
471 },
472 {
473 .addr = DDC_ADDR,
474 .flags = I2C_M_RD,
475 .len = 8,
476 .buf = buf,
477 }
478 };
479
480 /* on hw with routers, select right port */
481 if (amdgpu_connector->router.ddc_valid)
482 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
483
484 if (use_aux) {
485 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
486 } else {
487 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
488 }
489
490 if (ret != 2)
491 /* Couldn't find an accessible DDC on this connector */
492 return false;
493 /* Probe also for valid EDID header
494 * EDID header starts with:
495 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
496 * Only the first 6 bytes must be valid as
497 * drm_edid_block_valid() can fix the last 2 bytes */
498 if (drm_edid_header_is_valid(buf) < 6) {
499 /* Couldn't find an accessible EDID on this
500 * connector */
501 return false;
502 }
503 return true;
504 }
505
amdgpu_user_framebuffer_destroy(struct drm_framebuffer * fb)506 static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb)
507 {
508 struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
509
510 if (amdgpu_fb->obj) {
511 drm_gem_object_unreference_unlocked(amdgpu_fb->obj);
512 }
513 drm_framebuffer_cleanup(fb);
514 kfree(amdgpu_fb);
515 }
516
amdgpu_user_framebuffer_create_handle(struct drm_framebuffer * fb,struct drm_file * file_priv,unsigned int * handle)517 static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb,
518 struct drm_file *file_priv,
519 unsigned int *handle)
520 {
521 struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
522
523 return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle);
524 }
525
526 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
527 .destroy = amdgpu_user_framebuffer_destroy,
528 .create_handle = amdgpu_user_framebuffer_create_handle,
529 };
530
531 int
amdgpu_framebuffer_init(struct drm_device * dev,struct amdgpu_framebuffer * rfb,struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)532 amdgpu_framebuffer_init(struct drm_device *dev,
533 struct amdgpu_framebuffer *rfb,
534 struct drm_mode_fb_cmd2 *mode_cmd,
535 struct drm_gem_object *obj)
536 {
537 int ret;
538 rfb->obj = obj;
539 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
540 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
541 if (ret) {
542 rfb->obj = NULL;
543 return ret;
544 }
545 return 0;
546 }
547
548 static struct drm_framebuffer *
amdgpu_user_framebuffer_create(struct drm_device * dev,struct drm_file * file_priv,struct drm_mode_fb_cmd2 * mode_cmd)549 amdgpu_user_framebuffer_create(struct drm_device *dev,
550 struct drm_file *file_priv,
551 struct drm_mode_fb_cmd2 *mode_cmd)
552 {
553 struct drm_gem_object *obj;
554 struct amdgpu_framebuffer *amdgpu_fb;
555 int ret;
556
557 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
558 if (obj == NULL) {
559 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
560 "can't create framebuffer\n", mode_cmd->handles[0]);
561 return ERR_PTR(-ENOENT);
562 }
563
564 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
565 if (obj->import_attach) {
566 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
567 return ERR_PTR(-EINVAL);
568 }
569
570 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
571 if (amdgpu_fb == NULL) {
572 drm_gem_object_unreference_unlocked(obj);
573 return ERR_PTR(-ENOMEM);
574 }
575
576 ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj);
577 if (ret) {
578 kfree(amdgpu_fb);
579 drm_gem_object_unreference_unlocked(obj);
580 return ERR_PTR(ret);
581 }
582
583 return &amdgpu_fb->base;
584 }
585
amdgpu_output_poll_changed(struct drm_device * dev)586 static void amdgpu_output_poll_changed(struct drm_device *dev)
587 {
588 struct amdgpu_device *adev = dev->dev_private;
589 amdgpu_fb_output_poll_changed(adev);
590 }
591
592 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
593 .fb_create = amdgpu_user_framebuffer_create,
594 .output_poll_changed = amdgpu_output_poll_changed
595 };
596
597 static struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
598 { { UNDERSCAN_OFF, "off" },
599 { UNDERSCAN_ON, "on" },
600 { UNDERSCAN_AUTO, "auto" },
601 };
602
603 static struct drm_prop_enum_list amdgpu_audio_enum_list[] =
604 { { AMDGPU_AUDIO_DISABLE, "off" },
605 { AMDGPU_AUDIO_ENABLE, "on" },
606 { AMDGPU_AUDIO_AUTO, "auto" },
607 };
608
609 /* XXX support different dither options? spatial, temporal, both, etc. */
610 static struct drm_prop_enum_list amdgpu_dither_enum_list[] =
611 { { AMDGPU_FMT_DITHER_DISABLE, "off" },
612 { AMDGPU_FMT_DITHER_ENABLE, "on" },
613 };
614
amdgpu_modeset_create_props(struct amdgpu_device * adev)615 int amdgpu_modeset_create_props(struct amdgpu_device *adev)
616 {
617 int sz;
618
619 if (adev->is_atom_bios) {
620 adev->mode_info.coherent_mode_property =
621 drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1);
622 if (!adev->mode_info.coherent_mode_property)
623 return -ENOMEM;
624 }
625
626 adev->mode_info.load_detect_property =
627 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1);
628 if (!adev->mode_info.load_detect_property)
629 return -ENOMEM;
630
631 drm_mode_create_scaling_mode_property(adev->ddev);
632
633 sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
634 adev->mode_info.underscan_property =
635 drm_property_create_enum(adev->ddev, 0,
636 "underscan",
637 amdgpu_underscan_enum_list, sz);
638
639 adev->mode_info.underscan_hborder_property =
640 drm_property_create_range(adev->ddev, 0,
641 "underscan hborder", 0, 128);
642 if (!adev->mode_info.underscan_hborder_property)
643 return -ENOMEM;
644
645 adev->mode_info.underscan_vborder_property =
646 drm_property_create_range(adev->ddev, 0,
647 "underscan vborder", 0, 128);
648 if (!adev->mode_info.underscan_vborder_property)
649 return -ENOMEM;
650
651 sz = ARRAY_SIZE(amdgpu_audio_enum_list);
652 adev->mode_info.audio_property =
653 drm_property_create_enum(adev->ddev, 0,
654 "audio",
655 amdgpu_audio_enum_list, sz);
656
657 sz = ARRAY_SIZE(amdgpu_dither_enum_list);
658 adev->mode_info.dither_property =
659 drm_property_create_enum(adev->ddev, 0,
660 "dither",
661 amdgpu_dither_enum_list, sz);
662
663 return 0;
664 }
665
amdgpu_update_display_priority(struct amdgpu_device * adev)666 void amdgpu_update_display_priority(struct amdgpu_device *adev)
667 {
668 /* adjustment options for the display watermarks */
669 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
670 adev->mode_info.disp_priority = 0;
671 else
672 adev->mode_info.disp_priority = amdgpu_disp_priority;
673
674 }
675
is_hdtv_mode(const struct drm_display_mode * mode)676 static bool is_hdtv_mode(const struct drm_display_mode *mode)
677 {
678 /* try and guess if this is a tv or a monitor */
679 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
680 (mode->vdisplay == 576) || /* 576p */
681 (mode->vdisplay == 720) || /* 720p */
682 (mode->vdisplay == 1080)) /* 1080p */
683 return true;
684 else
685 return false;
686 }
687
amdgpu_crtc_scaling_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)688 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
689 const struct drm_display_mode *mode,
690 struct drm_display_mode *adjusted_mode)
691 {
692 struct drm_device *dev = crtc->dev;
693 struct drm_encoder *encoder;
694 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
695 struct amdgpu_encoder *amdgpu_encoder;
696 struct drm_connector *connector;
697 struct amdgpu_connector *amdgpu_connector;
698 u32 src_v = 1, dst_v = 1;
699 u32 src_h = 1, dst_h = 1;
700
701 amdgpu_crtc->h_border = 0;
702 amdgpu_crtc->v_border = 0;
703
704 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
705 if (encoder->crtc != crtc)
706 continue;
707 amdgpu_encoder = to_amdgpu_encoder(encoder);
708 connector = amdgpu_get_connector_for_encoder(encoder);
709 amdgpu_connector = to_amdgpu_connector(connector);
710
711 /* set scaling */
712 if (amdgpu_encoder->rmx_type == RMX_OFF)
713 amdgpu_crtc->rmx_type = RMX_OFF;
714 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
715 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
716 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
717 else
718 amdgpu_crtc->rmx_type = RMX_OFF;
719 /* copy native mode */
720 memcpy(&amdgpu_crtc->native_mode,
721 &amdgpu_encoder->native_mode,
722 sizeof(struct drm_display_mode));
723 src_v = crtc->mode.vdisplay;
724 dst_v = amdgpu_crtc->native_mode.vdisplay;
725 src_h = crtc->mode.hdisplay;
726 dst_h = amdgpu_crtc->native_mode.hdisplay;
727
728 /* fix up for overscan on hdmi */
729 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
730 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
731 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
732 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
733 is_hdtv_mode(mode)))) {
734 if (amdgpu_encoder->underscan_hborder != 0)
735 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
736 else
737 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
738 if (amdgpu_encoder->underscan_vborder != 0)
739 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
740 else
741 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
742 amdgpu_crtc->rmx_type = RMX_FULL;
743 src_v = crtc->mode.vdisplay;
744 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
745 src_h = crtc->mode.hdisplay;
746 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
747 }
748 }
749 if (amdgpu_crtc->rmx_type != RMX_OFF) {
750 fixed20_12 a, b;
751 a.full = dfixed_const(src_v);
752 b.full = dfixed_const(dst_v);
753 amdgpu_crtc->vsc.full = dfixed_div(a, b);
754 a.full = dfixed_const(src_h);
755 b.full = dfixed_const(dst_h);
756 amdgpu_crtc->hsc.full = dfixed_div(a, b);
757 } else {
758 amdgpu_crtc->vsc.full = dfixed_const(1);
759 amdgpu_crtc->hsc.full = dfixed_const(1);
760 }
761 return true;
762 }
763
764 /*
765 * Retrieve current video scanout position of crtc on a given gpu, and
766 * an optional accurate timestamp of when query happened.
767 *
768 * \param dev Device to query.
769 * \param pipe Crtc to query.
770 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
771 * For driver internal use only also supports these flags:
772 *
773 * USE_REAL_VBLANKSTART to use the real start of vblank instead
774 * of a fudged earlier start of vblank.
775 *
776 * GET_DISTANCE_TO_VBLANKSTART to return distance to the
777 * fudged earlier start of vblank in *vpos and the distance
778 * to true start of vblank in *hpos.
779 *
780 * \param *vpos Location where vertical scanout position should be stored.
781 * \param *hpos Location where horizontal scanout position should go.
782 * \param *stime Target location for timestamp taken immediately before
783 * scanout position query. Can be NULL to skip timestamp.
784 * \param *etime Target location for timestamp taken immediately after
785 * scanout position query. Can be NULL to skip timestamp.
786 *
787 * Returns vpos as a positive number while in active scanout area.
788 * Returns vpos as a negative number inside vblank, counting the number
789 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
790 * until start of active scanout / end of vblank."
791 *
792 * \return Flags, or'ed together as follows:
793 *
794 * DRM_SCANOUTPOS_VALID = Query successful.
795 * DRM_SCANOUTPOS_INVBL = Inside vblank.
796 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
797 * this flag means that returned position may be offset by a constant but
798 * unknown small number of scanlines wrt. real scanout position.
799 *
800 */
amdgpu_get_crtc_scanoutpos(struct drm_device * dev,unsigned int pipe,unsigned int flags,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)801 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
802 unsigned int flags, int *vpos, int *hpos,
803 ktime_t *stime, ktime_t *etime,
804 const struct drm_display_mode *mode)
805 {
806 u32 vbl = 0, position = 0;
807 int vbl_start, vbl_end, vtotal, ret = 0;
808 bool in_vbl = true;
809
810 struct amdgpu_device *adev = dev->dev_private;
811
812 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
813
814 /* Get optional system timestamp before query. */
815 if (stime)
816 *stime = ktime_get();
817
818 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
819 ret |= DRM_SCANOUTPOS_VALID;
820
821 /* Get optional system timestamp after query. */
822 if (etime)
823 *etime = ktime_get();
824
825 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
826
827 /* Decode into vertical and horizontal scanout position. */
828 *vpos = position & 0x1fff;
829 *hpos = (position >> 16) & 0x1fff;
830
831 /* Valid vblank area boundaries from gpu retrieved? */
832 if (vbl > 0) {
833 /* Yes: Decode. */
834 ret |= DRM_SCANOUTPOS_ACCURATE;
835 vbl_start = vbl & 0x1fff;
836 vbl_end = (vbl >> 16) & 0x1fff;
837 }
838 else {
839 /* No: Fake something reasonable which gives at least ok results. */
840 vbl_start = mode->crtc_vdisplay;
841 vbl_end = 0;
842 }
843
844 /* Called from driver internal vblank counter query code? */
845 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
846 /* Caller wants distance from real vbl_start in *hpos */
847 *hpos = *vpos - vbl_start;
848 }
849
850 /* Fudge vblank to start a few scanlines earlier to handle the
851 * problem that vblank irqs fire a few scanlines before start
852 * of vblank. Some driver internal callers need the true vblank
853 * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
854 *
855 * The cause of the "early" vblank irq is that the irq is triggered
856 * by the line buffer logic when the line buffer read position enters
857 * the vblank, whereas our crtc scanout position naturally lags the
858 * line buffer read position.
859 */
860 if (!(flags & USE_REAL_VBLANKSTART))
861 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
862
863 /* Test scanout position against vblank region. */
864 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
865 in_vbl = false;
866
867 /* In vblank? */
868 if (in_vbl)
869 ret |= DRM_SCANOUTPOS_IN_VBLANK;
870
871 /* Called from driver internal vblank counter query code? */
872 if (flags & GET_DISTANCE_TO_VBLANKSTART) {
873 /* Caller wants distance from fudged earlier vbl_start */
874 *vpos -= vbl_start;
875 return ret;
876 }
877
878 /* Check if inside vblank area and apply corrective offsets:
879 * vpos will then be >=0 in video scanout area, but negative
880 * within vblank area, counting down the number of lines until
881 * start of scanout.
882 */
883
884 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
885 if (in_vbl && (*vpos >= vbl_start)) {
886 vtotal = mode->crtc_vtotal;
887 *vpos = *vpos - vtotal;
888 }
889
890 /* Correct for shifted end of vbl at vbl_end. */
891 *vpos = *vpos - vbl_end;
892
893 return ret;
894 }
895
amdgpu_crtc_idx_to_irq_type(struct amdgpu_device * adev,int crtc)896 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
897 {
898 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
899 return AMDGPU_CRTC_IRQ_NONE;
900
901 switch (crtc) {
902 case 0:
903 return AMDGPU_CRTC_IRQ_VBLANK1;
904 case 1:
905 return AMDGPU_CRTC_IRQ_VBLANK2;
906 case 2:
907 return AMDGPU_CRTC_IRQ_VBLANK3;
908 case 3:
909 return AMDGPU_CRTC_IRQ_VBLANK4;
910 case 4:
911 return AMDGPU_CRTC_IRQ_VBLANK5;
912 case 5:
913 return AMDGPU_CRTC_IRQ_VBLANK6;
914 default:
915 return AMDGPU_CRTC_IRQ_NONE;
916 }
917 }
918