1 #ifndef _MAPPI2_PLD_H 2 #define _MAPPI2_PLD_H 3 4 /* 5 * include/asm-m32r/mappi2/mappi2_pld.h 6 * 7 * Definitions for Extended IO Logic on MAPPI2 board. 8 * based on m32700ut_pld.h 9 * 10 * This file is subject to the terms and conditions of the GNU General 11 * Public License. See the file "COPYING" in the main directory of 12 * this archive for more details. 13 */ 14 15 #ifndef __ASSEMBLY__ 16 /* FIXME: 17 * Some C functions use non-cache address, so can't define non-cache address. 18 */ 19 #define PLD_BASE (0x10c00000 /* + NONCACHE_OFFSET */) 20 #define __reg8 (volatile unsigned char *) 21 #define __reg16 (volatile unsigned short *) 22 #define __reg32 (volatile unsigned int *) 23 #else 24 #define PLD_BASE (0x10c00000 + NONCACHE_OFFSET) 25 #define __reg8 26 #define __reg16 27 #define __reg32 28 #endif /* __ASSEMBLY__ */ 29 30 /* CFC */ 31 #define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000) 32 #define PLD_CFSTS __reg16(PLD_BASE + 0x0002) 33 #define PLD_CFIMASK __reg16(PLD_BASE + 0x0004) 34 #define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006) 35 #define PLD_CFCR0 __reg16(PLD_BASE + 0x000a) 36 #define PLD_CFCR1 __reg16(PLD_BASE + 0x000c) 37 38 /* MMC */ 39 #define PLD_MMCCR __reg16(PLD_BASE + 0x4000) 40 #define PLD_MMCMOD __reg16(PLD_BASE + 0x4002) 41 #define PLD_MMCSTS __reg16(PLD_BASE + 0x4006) 42 #define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a) 43 #define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c) 44 #define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e) 45 #define PLD_MMCDET __reg16(PLD_BASE + 0x4010) 46 #define PLD_MMCWP __reg16(PLD_BASE + 0x4012) 47 #define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000) 48 #define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000) 49 #define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000) 50 #define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006) 51 52 /* Power Control of MMC and CF */ 53 #define PLD_CPCR __reg16(PLD_BASE + 0x14000) 54 55 56 /*==== ICU ====*/ 57 #define M32R_IRQ_PC104 (5) /* INT4(PC/104) */ 58 #define M32R_IRQ_I2C (28) /* I2C-BUS */ 59 #if 1 60 #define PLD_IRQ_CFIREQ (40) /* CFC Card Interrupt */ 61 #define PLD_IRQ_CFC_INSERT (41) /* CFC Card Insert */ 62 #define PLD_IRQ_CFC_EJECT (42) /* CFC Card Eject */ 63 #define PLD_IRQ_MMCCARD (43) /* MMC Card Insert */ 64 #define PLD_IRQ_MMCIRQ (44) /* MMC Transfer Done */ 65 #else 66 #define PLD_IRQ_CFIREQ (34) /* CFC Card Interrupt */ 67 #define PLD_IRQ_CFC_INSERT (35) /* CFC Card Insert */ 68 #define PLD_IRQ_CFC_EJECT (36) /* CFC Card Eject */ 69 #define PLD_IRQ_MMCCARD (37) /* MMC Card Insert */ 70 #define PLD_IRQ_MMCIRQ (38) /* MMC Transfer Done */ 71 #endif 72 73 74 #if 0 75 /* LED Control 76 * 77 * 1: DIP swich side 78 * 2: Reset switch side 79 */ 80 #define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002) 81 #define PLD_IOLED_1_ON 0x001 82 #define PLD_IOLED_1_OFF 0x000 83 #define PLD_IOLED_2_ON 0x002 84 #define PLD_IOLED_2_OFF 0x000 85 86 /* DIP Switch 87 * 0: Write-protect of Flash Memory (0:protected, 1:non-protected) 88 * 1: - 89 * 2: - 90 * 3: - 91 */ 92 #define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004) 93 #define PLD_IOSWSTS_IOSW2 0x0200 94 #define PLD_IOSWSTS_IOSW1 0x0100 95 #define PLD_IOSWSTS_IOWP0 0x0001 96 97 #endif 98 99 /* CRC */ 100 #define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000) 101 #define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002) 102 #define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004) 103 #define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006) 104 #define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008) 105 #define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a) 106 107 108 #if 0 109 /* RTC */ 110 #define PLD_RTCCR __reg16(PLD_BASE + 0x1c000) 111 #define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002) 112 #define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004) 113 #define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006) 114 #define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008) 115 116 /* SIO0 */ 117 #define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000) 118 #define PLD_ESIO0CR_TXEN 0x0001 119 #define PLD_ESIO0CR_RXEN 0x0002 120 #define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002) 121 #define PLD_ESIO0MOD0_CTSS 0x0040 122 #define PLD_ESIO0MOD0_RTSS 0x0080 123 #define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004) 124 #define PLD_ESIO0MOD1_LMFS 0x0010 125 #define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006) 126 #define PLD_ESIO0STS_TEMP 0x0001 127 #define PLD_ESIO0STS_TXCP 0x0002 128 #define PLD_ESIO0STS_RXCP 0x0004 129 #define PLD_ESIO0STS_TXSC 0x0100 130 #define PLD_ESIO0STS_RXSC 0x0200 131 #define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP) 132 #define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008) 133 #define PLD_ESIO0INTCR_TXIEN 0x0002 134 #define PLD_ESIO0INTCR_RXCEN 0x0004 135 #define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a) 136 #define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c) 137 #define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e) 138 139 /* SIM Card */ 140 #define PLD_SCCR __reg16(PLD_BASE + 0x38000) 141 #define PLD_SCMOD __reg16(PLD_BASE + 0x38004) 142 #define PLD_SCSTS __reg16(PLD_BASE + 0x38006) 143 #define PLD_SCINTCR __reg16(PLD_BASE + 0x38008) 144 #define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a) 145 #define PLD_SCTXB __reg16(PLD_BASE + 0x3800c) 146 #define PLD_SCRXB __reg16(PLD_BASE + 0x3800e) 147 148 #endif 149 150 #endif /* _MAPPI2_PLD.H */ 151