1/* 2 * Broadcom BCM470X / BCM5301X ARM platform code. 3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, 4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs 5 * 6 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include "skeleton.dtsi" 16 17/ { 18 interrupt-parent = <&gic>; 19 20 chipcommonA { 21 compatible = "simple-bus"; 22 ranges = <0x00000000 0x18000000 0x00001000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 26 uart0: serial@0300 { 27 compatible = "ns16550"; 28 reg = <0x0300 0x100>; 29 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 30 clock-frequency = <100000000>; 31 status = "disabled"; 32 }; 33 34 uart1: serial@0400 { 35 compatible = "ns16550"; 36 reg = <0x0400 0x100>; 37 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 38 clock-frequency = <100000000>; 39 status = "disabled"; 40 }; 41 }; 42 43 mpcore { 44 compatible = "simple-bus"; 45 ranges = <0x00000000 0x19020000 0x00003000>; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 49 scu@0000 { 50 compatible = "arm,cortex-a9-scu"; 51 reg = <0x0000 0x100>; 52 }; 53 54 timer@0200 { 55 compatible = "arm,cortex-a9-global-timer"; 56 reg = <0x0200 0x100>; 57 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 58 clocks = <&clk_periph>; 59 }; 60 61 local-timer@0600 { 62 compatible = "arm,cortex-a9-twd-timer"; 63 reg = <0x0600 0x100>; 64 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>; 65 clocks = <&clk_periph>; 66 }; 67 68 gic: interrupt-controller@1000 { 69 compatible = "arm,cortex-a9-gic"; 70 #interrupt-cells = <3>; 71 #address-cells = <0>; 72 interrupt-controller; 73 reg = <0x1000 0x1000>, 74 <0x0100 0x100>; 75 }; 76 77 L2: cache-controller@2000 { 78 compatible = "arm,pl310-cache"; 79 reg = <0x2000 0x1000>; 80 cache-unified; 81 arm,shared-override; 82 prefetch-data = <1>; 83 prefetch-instr = <1>; 84 cache-level = <2>; 85 }; 86 }; 87 88 pmu { 89 compatible = "arm,cortex-a9-pmu"; 90 interrupts = 91 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 93 }; 94 95 clocks { 96 #address-cells = <1>; 97 #size-cells = <0>; 98 99 /* As long as we do not have a real clock driver us this 100 * fixed clock */ 101 clk_periph: periph { 102 compatible = "fixed-clock"; 103 #clock-cells = <0>; 104 clock-frequency = <400000000>; 105 }; 106 }; 107 108 axi@18000000 { 109 compatible = "brcm,bus-axi"; 110 reg = <0x18000000 0x1000>; 111 ranges = <0x00000000 0x18000000 0x00100000>; 112 #address-cells = <1>; 113 #size-cells = <1>; 114 115 #interrupt-cells = <1>; 116 interrupt-map-mask = <0x000fffff 0xffff>; 117 interrupt-map = 118 /* ChipCommon */ 119 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 120 121 /* PCIe Controller 0 */ 122 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 123 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 124 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 125 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 126 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 127 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 128 129 /* PCIe Controller 1 */ 130 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 131 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 132 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 133 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 134 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 135 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 136 137 /* PCIe Controller 2 */ 138 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 139 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 140 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 141 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 142 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 143 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 144 145 /* USB 2.0 Controller */ 146 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 147 148 /* USB 3.0 Controller */ 149 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 150 151 /* Ethernet Controller 0 */ 152 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 153 154 /* Ethernet Controller 1 */ 155 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 156 157 /* Ethernet Controller 2 */ 158 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 159 160 /* Ethernet Controller 3 */ 161 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 162 163 /* NAND Controller */ 164 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 165 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 166 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 167 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 168 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 169 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 170 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 171 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 172 173 chipcommon: chipcommon@0 { 174 reg = <0x00000000 0x1000>; 175 176 gpio-controller; 177 #gpio-cells = <2>; 178 interrupt-controller; 179 #interrupt-cells = <2>; 180 }; 181 }; 182 183 nand: nand@18028000 { 184 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; 185 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; 186 reg-names = "nand", "iproc-idm", "iproc-ext"; 187 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 188 189 #address-cells = <1>; 190 #size-cells = <0>; 191 192 brcm,nand-has-wp; 193 }; 194}; 195