1 /*
2 * Renesas Technology Corp. R0P7785LC0011RL Support.
3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda
5 * Copyright (C) 2009 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/sm501.h>
14 #include <linux/sm501-regs.h>
15 #include <linux/fb.h>
16 #include <linux/mtd/physmap.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/i2c.h>
20 #include <linux/i2c-pca-platform.h>
21 #include <linux/i2c-algo-pca.h>
22 #include <linux/usb/r8a66597.h>
23 #include <linux/sh_intc.h>
24 #include <linux/irq.h>
25 #include <linux/io.h>
26 #include <linux/clk.h>
27 #include <linux/errno.h>
28 #include <mach/sh7785lcr.h>
29 #include <cpu/sh7785.h>
30 #include <asm/heartbeat.h>
31 #include <asm/clock.h>
32 #include <asm/bl_bit.h>
33
34 /*
35 * NOTE: This board has 2 physical memory maps.
36 * Please look at include/asm-sh/sh7785lcr.h or hardware manual.
37 */
38 static struct resource heartbeat_resource = {
39 .start = PLD_LEDCR,
40 .end = PLD_LEDCR,
41 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
42 };
43
44 static struct platform_device heartbeat_device = {
45 .name = "heartbeat",
46 .id = -1,
47 .num_resources = 1,
48 .resource = &heartbeat_resource,
49 };
50
51 static struct mtd_partition nor_flash_partitions[] = {
52 {
53 .name = "loader",
54 .offset = 0x00000000,
55 .size = 512 * 1024,
56 },
57 {
58 .name = "bootenv",
59 .offset = MTDPART_OFS_APPEND,
60 .size = 512 * 1024,
61 },
62 {
63 .name = "kernel",
64 .offset = MTDPART_OFS_APPEND,
65 .size = 4 * 1024 * 1024,
66 },
67 {
68 .name = "data",
69 .offset = MTDPART_OFS_APPEND,
70 .size = MTDPART_SIZ_FULL,
71 },
72 };
73
74 static struct physmap_flash_data nor_flash_data = {
75 .width = 4,
76 .parts = nor_flash_partitions,
77 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
78 };
79
80 static struct resource nor_flash_resources[] = {
81 [0] = {
82 .start = NOR_FLASH_ADDR,
83 .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
84 .flags = IORESOURCE_MEM,
85 }
86 };
87
88 static struct platform_device nor_flash_device = {
89 .name = "physmap-flash",
90 .dev = {
91 .platform_data = &nor_flash_data,
92 },
93 .num_resources = ARRAY_SIZE(nor_flash_resources),
94 .resource = nor_flash_resources,
95 };
96
97 static struct r8a66597_platdata r8a66597_data = {
98 .xtal = R8A66597_PLATDATA_XTAL_12MHZ,
99 .vif = 1,
100 };
101
102 static struct resource r8a66597_usb_host_resources[] = {
103 [0] = {
104 .start = R8A66597_ADDR,
105 .end = R8A66597_ADDR + R8A66597_SIZE - 1,
106 .flags = IORESOURCE_MEM,
107 },
108 [1] = {
109 .start = evt2irq(0x240),
110 .end = evt2irq(0x240),
111 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
112 },
113 };
114
115 static struct platform_device r8a66597_usb_host_device = {
116 .name = "r8a66597_hcd",
117 .id = -1,
118 .dev = {
119 .dma_mask = NULL,
120 .coherent_dma_mask = 0xffffffff,
121 .platform_data = &r8a66597_data,
122 },
123 .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
124 .resource = r8a66597_usb_host_resources,
125 };
126
127 static struct resource sm501_resources[] = {
128 [0] = {
129 .start = SM107_MEM_ADDR,
130 .end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1,
131 .flags = IORESOURCE_MEM,
132 },
133 [1] = {
134 .start = SM107_REG_ADDR,
135 .end = SM107_REG_ADDR + SM107_REG_SIZE - 1,
136 .flags = IORESOURCE_MEM,
137 },
138 [2] = {
139 .start = evt2irq(0x340),
140 .flags = IORESOURCE_IRQ,
141 },
142 };
143
144 static struct fb_videomode sm501_default_mode_crt = {
145 .pixclock = 35714, /* 28MHz */
146 .xres = 640,
147 .yres = 480,
148 .left_margin = 105,
149 .right_margin = 16,
150 .upper_margin = 33,
151 .lower_margin = 10,
152 .hsync_len = 39,
153 .vsync_len = 2,
154 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
155 };
156
157 static struct fb_videomode sm501_default_mode_pnl = {
158 .pixclock = 40000, /* 25MHz */
159 .xres = 640,
160 .yres = 480,
161 .left_margin = 2,
162 .right_margin = 16,
163 .upper_margin = 33,
164 .lower_margin = 10,
165 .hsync_len = 39,
166 .vsync_len = 2,
167 .sync = 0,
168 };
169
170 static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = {
171 .def_bpp = 16,
172 .def_mode = &sm501_default_mode_pnl,
173 .flags = SM501FB_FLAG_USE_INIT_MODE |
174 SM501FB_FLAG_USE_HWCURSOR |
175 SM501FB_FLAG_USE_HWACCEL |
176 SM501FB_FLAG_DISABLE_AT_EXIT |
177 SM501FB_FLAG_PANEL_NO_VBIASEN,
178 };
179
180 static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = {
181 .def_bpp = 16,
182 .def_mode = &sm501_default_mode_crt,
183 .flags = SM501FB_FLAG_USE_INIT_MODE |
184 SM501FB_FLAG_USE_HWCURSOR |
185 SM501FB_FLAG_USE_HWACCEL |
186 SM501FB_FLAG_DISABLE_AT_EXIT,
187 };
188
189 static struct sm501_platdata_fb sm501_fb_pdata = {
190 .fb_route = SM501_FB_OWN,
191 .fb_crt = &sm501_pdata_fbsub_crt,
192 .fb_pnl = &sm501_pdata_fbsub_pnl,
193 };
194
195 static struct sm501_initdata sm501_initdata = {
196 .gpio_high = {
197 .set = 0x00001fe0,
198 .mask = 0x0,
199 },
200 .devices = 0,
201 .mclk = 84 * 1000000,
202 .m1xclk = 112 * 1000000,
203 };
204
205 static struct sm501_platdata sm501_platform_data = {
206 .init = &sm501_initdata,
207 .fb = &sm501_fb_pdata,
208 };
209
210 static struct platform_device sm501_device = {
211 .name = "sm501",
212 .id = -1,
213 .dev = {
214 .platform_data = &sm501_platform_data,
215 },
216 .num_resources = ARRAY_SIZE(sm501_resources),
217 .resource = sm501_resources,
218 };
219
220 static struct resource i2c_proto_resources[] = {
221 [0] = {
222 .start = PCA9564_PROTO_32BIT_ADDR,
223 .end = PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1,
224 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
225 },
226 [1] = {
227 .start = evt2irq(0x380),
228 .end = evt2irq(0x380),
229 .flags = IORESOURCE_IRQ,
230 },
231 };
232
233 static struct resource i2c_resources[] = {
234 [0] = {
235 .start = PCA9564_ADDR,
236 .end = PCA9564_ADDR + PCA9564_SIZE - 1,
237 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
238 },
239 [1] = {
240 .start = evt2irq(0x380),
241 .end = evt2irq(0x380),
242 .flags = IORESOURCE_IRQ,
243 },
244 };
245
246 static struct i2c_pca9564_pf_platform_data i2c_platform_data = {
247 .gpio = 0,
248 .i2c_clock_speed = I2C_PCA_CON_330kHz,
249 .timeout = HZ,
250 };
251
252 static struct platform_device i2c_device = {
253 .name = "i2c-pca-platform",
254 .id = -1,
255 .dev = {
256 .platform_data = &i2c_platform_data,
257 },
258 .num_resources = ARRAY_SIZE(i2c_resources),
259 .resource = i2c_resources,
260 };
261
262 static struct platform_device *sh7785lcr_devices[] __initdata = {
263 &heartbeat_device,
264 &nor_flash_device,
265 &r8a66597_usb_host_device,
266 &sm501_device,
267 &i2c_device,
268 };
269
270 static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = {
271 {
272 I2C_BOARD_INFO("r2025sd", 0x32),
273 },
274 };
275
sh7785lcr_devices_setup(void)276 static int __init sh7785lcr_devices_setup(void)
277 {
278 i2c_register_board_info(0, sh7785lcr_i2c_devices,
279 ARRAY_SIZE(sh7785lcr_i2c_devices));
280
281 if (mach_is_sh7785lcr_pt()) {
282 i2c_device.resource = i2c_proto_resources;
283 i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources);
284 }
285
286 return platform_add_devices(sh7785lcr_devices,
287 ARRAY_SIZE(sh7785lcr_devices));
288 }
289 device_initcall(sh7785lcr_devices_setup);
290
291 /* Initialize IRQ setting */
init_sh7785lcr_IRQ(void)292 void __init init_sh7785lcr_IRQ(void)
293 {
294 plat_irq_setup_pins(IRQ_MODE_IRQ7654);
295 plat_irq_setup_pins(IRQ_MODE_IRQ3210);
296 }
297
sh7785lcr_clk_init(void)298 static int sh7785lcr_clk_init(void)
299 {
300 struct clk *clk;
301 int ret;
302
303 clk = clk_get(NULL, "extal");
304 if (IS_ERR(clk))
305 return PTR_ERR(clk);
306 ret = clk_set_rate(clk, 33333333);
307 clk_put(clk);
308
309 return ret;
310 }
311
sh7785lcr_power_off(void)312 static void sh7785lcr_power_off(void)
313 {
314 unsigned char *p;
315
316 p = ioremap(PLD_POFCR, PLD_POFCR + 1);
317 if (!p) {
318 printk(KERN_ERR "%s: ioremap error.\n", __func__);
319 return;
320 }
321 *p = 0x01;
322 iounmap(p);
323 set_bl_bit();
324 while (1)
325 cpu_relax();
326 }
327
328 /* Initialize the board */
sh7785lcr_setup(char ** cmdline_p)329 static void __init sh7785lcr_setup(char **cmdline_p)
330 {
331 void __iomem *sm501_reg;
332
333 printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n");
334
335 pm_power_off = sh7785lcr_power_off;
336
337 /* sm501 DRAM configuration */
338 sm501_reg = ioremap_nocache(SM107_REG_ADDR, SM501_DRAM_CONTROL);
339 if (!sm501_reg) {
340 printk(KERN_ERR "%s: ioremap error.\n", __func__);
341 return;
342 }
343
344 writel(0x000307c2, sm501_reg + SM501_DRAM_CONTROL);
345 iounmap(sm501_reg);
346 }
347
348 /* Return the board specific boot mode pin configuration */
sh7785lcr_mode_pins(void)349 static int sh7785lcr_mode_pins(void)
350 {
351 int value = 0;
352
353 /* These are the factory default settings of S1 and S2.
354 * If you change these dip switches then you will need to
355 * adjust the values below as well.
356 */
357 value |= MODE_PIN4; /* Clock Mode 16 */
358 value |= MODE_PIN5; /* 32-bit Area0 bus width */
359 value |= MODE_PIN6; /* 32-bit Area0 bus width */
360 value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */
361 value |= MODE_PIN8; /* Little Endian */
362 value |= MODE_PIN9; /* Master Mode */
363 value |= MODE_PIN14; /* No PLL step-up */
364
365 return value;
366 }
367
368 /*
369 * The Machine Vector
370 */
371 static struct sh_machine_vector mv_sh7785lcr __initmv = {
372 .mv_name = "SH7785LCR",
373 .mv_setup = sh7785lcr_setup,
374 .mv_clk_init = sh7785lcr_clk_init,
375 .mv_init_irq = init_sh7785lcr_IRQ,
376 .mv_mode_pins = sh7785lcr_mode_pins,
377 };
378
379