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1 /******************************************************************************
2  *
3  * This file is provided under a dual BSD/GPLv2 license.  When using or
4  * redistributing this file, you may do so under either license.
5  *
6  * GPL LICENSE SUMMARY
7  *
8  * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10  * Copyright(c) 2015        Intel Deutschland GmbH
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of version 2 of the GNU General Public License as
14  * published by the Free Software Foundation.
15  *
16  * This program is distributed in the hope that it will be useful, but
17  * WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19  * General Public License for more details.
20  *
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23  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24  * USA
25  *
26  * The full GNU General Public License is included in this distribution
27  * in the file called COPYING.
28  *
29  * Contact Information:
30  *  Intel Linux Wireless <ilw@linux.intel.com>
31  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32  *
33  * BSD LICENSE
34  *
35  * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
36  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
37  * Copyright(c) 2015        Intel Deutschland GmbH
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54  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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65  *
66  *****************************************************************************/
67 
68 #ifndef __fw_api_rx_h__
69 #define __fw_api_rx_h__
70 
71 #define IWL_RX_INFO_PHY_CNT 8
72 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1
73 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
74 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
75 #define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
76 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0
77 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8
78 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16
79 
80 /**
81  * struct iwl_rx_phy_info - phy info
82  * (REPLY_RX_PHY_CMD = 0xc0)
83  * @non_cfg_phy_cnt: non configurable DSP phy data byte count
84  * @cfg_phy_cnt: configurable DSP phy data byte count
85  * @stat_id: configurable DSP phy data set ID
86  * @reserved1:
87  * @system_timestamp: GP2  at on air rise
88  * @timestamp: TSF at on air rise
89  * @beacon_time_stamp: beacon at on-air rise
90  * @phy_flags: general phy flags: band, modulation, ...
91  * @channel: channel number
92  * @non_cfg_phy_buf: for various implementations of non_cfg_phy
93  * @rate_n_flags: RATE_MCS_*
94  * @byte_count: frame's byte-count
95  * @frame_time: frame's time on the air, based on byte count and frame rate
96  *	calculation
97  * @mac_active_msk: what MACs were active when the frame was received
98  *
99  * Before each Rx, the device sends this data. It contains PHY information
100  * about the reception of the packet.
101  */
102 struct iwl_rx_phy_info {
103 	u8 non_cfg_phy_cnt;
104 	u8 cfg_phy_cnt;
105 	u8 stat_id;
106 	u8 reserved1;
107 	__le32 system_timestamp;
108 	__le64 timestamp;
109 	__le32 beacon_time_stamp;
110 	__le16 phy_flags;
111 	__le16 channel;
112 	__le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT];
113 	__le32 rate_n_flags;
114 	__le32 byte_count;
115 	__le16 mac_active_msk;
116 	__le16 frame_time;
117 } __packed;
118 
119 /*
120  * TCP offload Rx assist info
121  *
122  * bits 0:3 - reserved
123  * bits 4:7 - MIC CRC length
124  * bits 8:12 - MAC header length
125  * bit 13 - Padding indication
126  * bit 14 - A-AMSDU indication
127  * bit 15 - Offload enabled
128  */
129 enum iwl_csum_rx_assist_info {
130 	CSUM_RXA_RESERVED_MASK	= 0x000f,
131 	CSUM_RXA_MICSIZE_MASK	= 0x00f0,
132 	CSUM_RXA_HEADERLEN_MASK	= 0x1f00,
133 	CSUM_RXA_PADD		= BIT(13),
134 	CSUM_RXA_AMSDU		= BIT(14),
135 	CSUM_RXA_ENA		= BIT(15)
136 };
137 
138 /**
139  * struct iwl_rx_mpdu_res_start - phy info
140  * @assist: see CSUM_RX_ASSIST_ above
141  */
142 struct iwl_rx_mpdu_res_start {
143 	__le16 byte_count;
144 	__le16 assist;
145 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */
146 
147 /**
148  * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags
149  * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
150  * @RX_RES_PHY_FLAGS_MOD_CCK:
151  * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
152  * @RX_RES_PHY_FLAGS_NARROW_BAND:
153  * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
154  * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
155  * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
156  * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
157  * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
158  */
159 enum iwl_rx_phy_flags {
160 	RX_RES_PHY_FLAGS_BAND_24	= BIT(0),
161 	RX_RES_PHY_FLAGS_MOD_CCK	= BIT(1),
162 	RX_RES_PHY_FLAGS_SHORT_PREAMBLE	= BIT(2),
163 	RX_RES_PHY_FLAGS_NARROW_BAND	= BIT(3),
164 	RX_RES_PHY_FLAGS_ANTENNA	= (0x7 << 4),
165 	RX_RES_PHY_FLAGS_ANTENNA_POS	= 4,
166 	RX_RES_PHY_FLAGS_AGG		= BIT(7),
167 	RX_RES_PHY_FLAGS_OFDM_HT	= BIT(8),
168 	RX_RES_PHY_FLAGS_OFDM_GF	= BIT(9),
169 	RX_RES_PHY_FLAGS_OFDM_VHT	= BIT(10),
170 };
171 
172 /**
173  * enum iwl_mvm_rx_status - written by fw for each Rx packet
174  * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
175  * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
176  * @RX_MPDU_RES_STATUS_SRC_STA_FOUND:
177  * @RX_MPDU_RES_STATUS_KEY_VALID:
178  * @RX_MPDU_RES_STATUS_KEY_PARAM_OK:
179  * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
180  * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
181  *	in the driver.
182  * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
183  * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR:  valid for alg = CCM_CMAC or
184  *	alg = CCM only. Checks replay attack for 11w frames. Relevant only if
185  *	%RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
186  * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
187  * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
188  * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
189  * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
190  * @RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
191  * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
192  * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
193  * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
194  * @RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
195  * @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
196  * @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
197  * @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
198  * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw
199  * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors
200  * @RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
201  * @RX_MPDU_RES_STATUS_STA_ID_MSK:
202  * @RX_MPDU_RES_STATUS_RRF_KILL:
203  * @RX_MPDU_RES_STATUS_FILTERING_MSK:
204  * @RX_MPDU_RES_STATUS2_FILTERING_MSK:
205  */
206 enum iwl_mvm_rx_status {
207 	RX_MPDU_RES_STATUS_CRC_OK			= BIT(0),
208 	RX_MPDU_RES_STATUS_OVERRUN_OK			= BIT(1),
209 	RX_MPDU_RES_STATUS_SRC_STA_FOUND		= BIT(2),
210 	RX_MPDU_RES_STATUS_KEY_VALID			= BIT(3),
211 	RX_MPDU_RES_STATUS_KEY_PARAM_OK			= BIT(4),
212 	RX_MPDU_RES_STATUS_ICV_OK			= BIT(5),
213 	RX_MPDU_RES_STATUS_MIC_OK			= BIT(6),
214 	RX_MPDU_RES_STATUS_TTAK_OK			= BIT(7),
215 	RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR		= BIT(7),
216 	RX_MPDU_RES_STATUS_SEC_NO_ENC			= (0 << 8),
217 	RX_MPDU_RES_STATUS_SEC_WEP_ENC			= (1 << 8),
218 	RX_MPDU_RES_STATUS_SEC_CCM_ENC			= (2 << 8),
219 	RX_MPDU_RES_STATUS_SEC_TKIP_ENC			= (3 << 8),
220 	RX_MPDU_RES_STATUS_SEC_EXT_ENC			= (4 << 8),
221 	RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC		= (6 << 8),
222 	RX_MPDU_RES_STATUS_SEC_ENC_ERR			= (7 << 8),
223 	RX_MPDU_RES_STATUS_SEC_ENC_MSK			= (7 << 8),
224 	RX_MPDU_RES_STATUS_DEC_DONE			= BIT(11),
225 	RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP	= BIT(12),
226 	RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP		= BIT(13),
227 	RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT		= BIT(14),
228 	RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME		= BIT(15),
229 	RX_MPDU_RES_STATUS_CSUM_DONE			= BIT(16),
230 	RX_MPDU_RES_STATUS_CSUM_OK			= BIT(17),
231 	RX_MPDU_RES_STATUS_HASH_INDEX_MSK		= (0x3F0000),
232 	RX_MPDU_RES_STATUS_STA_ID_MSK			= (0x1f000000),
233 	RX_MPDU_RES_STATUS_RRF_KILL			= BIT(29),
234 	RX_MPDU_RES_STATUS_FILTERING_MSK		= (0xc00000),
235 	RX_MPDU_RES_STATUS2_FILTERING_MSK		= (0xc0000000),
236 };
237 
238 #endif /* __fw_api_rx_h__ */
239