1/* head-mmu-fr451.S: FR451 mmu-linux specific bits of initialisation 2 * 3 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. 4 * Written by David Howells (dhowells@redhat.com) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12#include <linux/init.h> 13#include <linux/threads.h> 14#include <linux/linkage.h> 15#include <asm/ptrace.h> 16#include <asm/page.h> 17#include <asm/mem-layout.h> 18#include <asm/spr-regs.h> 19#include <asm/mb86943a.h> 20#include "head.inc" 21 22 23#define __400_DBR0 0xfe000e00 24#define __400_DBR1 0xfe000e08 25#define __400_DBR2 0xfe000e10 26#define __400_DBR3 0xfe000e18 27#define __400_DAM0 0xfe000f00 28#define __400_DAM1 0xfe000f08 29#define __400_DAM2 0xfe000f10 30#define __400_DAM3 0xfe000f18 31#define __400_LGCR 0xfe000010 32#define __400_LCR 0xfe000100 33#define __400_LSBR 0xfe000c00 34 35 __INIT 36 .balign 4 37 38############################################################################### 39# 40# describe the position and layout of the SDRAM controller registers 41# 42# ENTRY: EXIT: 43# GR5 - cacheline size 44# GR11 - displacement of 2nd SDRAM addr reg from GR14 45# GR12 - displacement of 3rd SDRAM addr reg from GR14 46# GR13 - displacement of 4th SDRAM addr reg from GR14 47# GR14 - address of 1st SDRAM addr reg 48# GR15 - amount to shift address by to match SDRAM addr reg 49# GR26 &__head_reference [saved] 50# GR30 LED address [saved] 51# CC0 - T if DBR0 is present 52# CC1 - T if DBR1 is present 53# CC2 - T if DBR2 is present 54# CC3 - T if DBR3 is present 55# 56############################################################################### 57 .globl __head_fr451_describe_sdram 58__head_fr451_describe_sdram: 59 sethi.p %hi(__400_DBR0),gr14 60 setlo %lo(__400_DBR0),gr14 61 setlos.p #__400_DBR1-__400_DBR0,gr11 62 setlos #__400_DBR2-__400_DBR0,gr12 63 setlos.p #__400_DBR3-__400_DBR0,gr13 64 setlos #32,gr5 ; cacheline size 65 setlos.p #0,gr15 ; amount to shift addr reg by 66 setlos #0x00ff,gr4 67 movgs gr4,cccr ; extant DARS/DAMK regs 68 bralr 69 70############################################################################### 71# 72# rearrange the bus controller registers 73# 74# ENTRY: EXIT: 75# GR26 &__head_reference [saved] 76# GR30 LED address revised LED address 77# 78############################################################################### 79 .globl __head_fr451_set_busctl 80__head_fr451_set_busctl: 81 sethi.p %hi(__400_LGCR),gr4 82 setlo %lo(__400_LGCR),gr4 83 sethi.p %hi(__400_LSBR),gr10 84 setlo %lo(__400_LSBR),gr10 85 sethi.p %hi(__400_LCR),gr11 86 setlo %lo(__400_LCR),gr11 87 88 # set the bus controller 89 ldi @(gr4,#0),gr5 90 ori gr5,#0xff,gr5 ; make sure all chip-selects are enabled 91 sti gr5,@(gr4,#0) 92 93 sethi.p %hi(__region_CS1),gr4 94 setlo %lo(__region_CS1),gr4 95 sethi.p %hi(__region_CS1_M),gr5 96 setlo %lo(__region_CS1_M),gr5 97 sethi.p %hi(__region_CS1_C),gr6 98 setlo %lo(__region_CS1_C),gr6 99 sti gr4,@(gr10,#1*0x08) 100 sti gr5,@(gr10,#1*0x08+0x100) 101 sti gr6,@(gr11,#1*0x08) 102 sethi.p %hi(__region_CS2),gr4 103 setlo %lo(__region_CS2),gr4 104 sethi.p %hi(__region_CS2_M),gr5 105 setlo %lo(__region_CS2_M),gr5 106 sethi.p %hi(__region_CS2_C),gr6 107 setlo %lo(__region_CS2_C),gr6 108 sti gr4,@(gr10,#2*0x08) 109 sti gr5,@(gr10,#2*0x08+0x100) 110 sti gr6,@(gr11,#2*0x08) 111 sethi.p %hi(__region_CS3),gr4 112 setlo %lo(__region_CS3),gr4 113 sethi.p %hi(__region_CS3_M),gr5 114 setlo %lo(__region_CS3_M),gr5 115 sethi.p %hi(__region_CS3_C),gr6 116 setlo %lo(__region_CS3_C),gr6 117 sti gr4,@(gr10,#3*0x08) 118 sti gr5,@(gr10,#3*0x08+0x100) 119 sti gr6,@(gr11,#3*0x08) 120 sethi.p %hi(__region_CS4),gr4 121 setlo %lo(__region_CS4),gr4 122 sethi.p %hi(__region_CS4_M),gr5 123 setlo %lo(__region_CS4_M),gr5 124 sethi.p %hi(__region_CS4_C),gr6 125 setlo %lo(__region_CS4_C),gr6 126 sti gr4,@(gr10,#4*0x08) 127 sti gr5,@(gr10,#4*0x08+0x100) 128 sti gr6,@(gr11,#4*0x08) 129 sethi.p %hi(__region_CS5),gr4 130 setlo %lo(__region_CS5),gr4 131 sethi.p %hi(__region_CS5_M),gr5 132 setlo %lo(__region_CS5_M),gr5 133 sethi.p %hi(__region_CS5_C),gr6 134 setlo %lo(__region_CS5_C),gr6 135 sti gr4,@(gr10,#5*0x08) 136 sti gr5,@(gr10,#5*0x08+0x100) 137 sti gr6,@(gr11,#5*0x08) 138 sethi.p %hi(__region_CS6),gr4 139 setlo %lo(__region_CS6),gr4 140 sethi.p %hi(__region_CS6_M),gr5 141 setlo %lo(__region_CS6_M),gr5 142 sethi.p %hi(__region_CS6_C),gr6 143 setlo %lo(__region_CS6_C),gr6 144 sti gr4,@(gr10,#6*0x08) 145 sti gr5,@(gr10,#6*0x08+0x100) 146 sti gr6,@(gr11,#6*0x08) 147 sethi.p %hi(__region_CS7),gr4 148 setlo %lo(__region_CS7),gr4 149 sethi.p %hi(__region_CS7_M),gr5 150 setlo %lo(__region_CS7_M),gr5 151 sethi.p %hi(__region_CS7_C),gr6 152 setlo %lo(__region_CS7_C),gr6 153 sti gr4,@(gr10,#7*0x08) 154 sti gr5,@(gr10,#7*0x08+0x100) 155 sti gr6,@(gr11,#7*0x08) 156 membar 157 bar 158 159 # adjust LED bank address 160#ifdef CONFIG_MB93091_VDK 161 sethi.p %hi(__region_CS2 + 0x01200004),gr30 162 setlo %lo(__region_CS2 + 0x01200004),gr30 163#endif 164 bralr 165 166############################################################################### 167# 168# determine the total SDRAM size 169# 170# ENTRY: EXIT: 171# GR25 - SDRAM size 172# GR26 &__head_reference [saved] 173# GR30 LED address [saved] 174# 175############################################################################### 176 .globl __head_fr451_survey_sdram 177__head_fr451_survey_sdram: 178 sethi.p %hi(__400_DAM0),gr11 179 setlo %lo(__400_DAM0),gr11 180 sethi.p %hi(__400_DBR0),gr12 181 setlo %lo(__400_DBR0),gr12 182 183 sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value 184 setlo %lo(0xfe000000),gr17 185 setlos #0,gr25 186 187 ldi @(gr12,#0x00),gr4 ; DAR0 188 subcc gr4,gr17,gr0,icc0 189 beq icc0,#0,__head_no_DCS0 190 ldi @(gr11,#0x00),gr6 ; DAM0: bits 31:20 match addr 31:20 191 add gr25,gr6,gr25 192 addi gr25,#1,gr25 193__head_no_DCS0: 194 195 ldi @(gr12,#0x08),gr4 ; DAR1 196 subcc gr4,gr17,gr0,icc0 197 beq icc0,#0,__head_no_DCS1 198 ldi @(gr11,#0x08),gr6 ; DAM1: bits 31:20 match addr 31:20 199 add gr25,gr6,gr25 200 addi gr25,#1,gr25 201__head_no_DCS1: 202 203 ldi @(gr12,#0x10),gr4 ; DAR2 204 subcc gr4,gr17,gr0,icc0 205 beq icc0,#0,__head_no_DCS2 206 ldi @(gr11,#0x10),gr6 ; DAM2: bits 31:20 match addr 31:20 207 add gr25,gr6,gr25 208 addi gr25,#1,gr25 209__head_no_DCS2: 210 211 ldi @(gr12,#0x18),gr4 ; DAR3 212 subcc gr4,gr17,gr0,icc0 213 beq icc0,#0,__head_no_DCS3 214 ldi @(gr11,#0x18),gr6 ; DAM3: bits 31:20 match addr 31:20 215 add gr25,gr6,gr25 216 addi gr25,#1,gr25 217__head_no_DCS3: 218 bralr 219 220############################################################################### 221# 222# set the protection map with the I/DAMPR registers 223# 224# ENTRY: EXIT: 225# GR25 SDRAM size [saved] 226# GR26 &__head_reference [saved] 227# GR30 LED address [saved] 228# 229# 230# Using this map: 231# REGISTERS ADDRESS RANGE VIEW 232# =============== ====================== =============================== 233# IAMPR0/DAMPR0 0xC0000000-0xCFFFFFFF Cached kernel RAM Window 234# DAMPR11 0xE0000000-0xFFFFFFFF Uncached I/O 235# 236############################################################################### 237 .globl __head_fr451_set_protection 238__head_fr451_set_protection: 239 movsg lr,gr27 240 241 # set the I/O region protection registers for FR451 in MMU mode 242#define PGPROT_IO xAMPRx_L|xAMPRx_M|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V 243 244 sethi.p %hi(__region_IO),gr5 245 setlo %lo(__region_IO),gr5 246 setlos #PGPROT_IO|xAMPRx_SS_512Mb,gr4 247 or gr4,gr5,gr4 248 movgs gr5,damlr11 ; General I/O tile 249 movgs gr4,dampr11 250 251 # need to open a window onto at least part of the RAM for the kernel's use 252 sethi.p %hi(__sdram_base),gr8 253 setlo %lo(__sdram_base),gr8 ; physical address 254 sethi.p %hi(__page_offset),gr9 255 setlo %lo(__page_offset),gr9 ; virtual address 256 257 setlos #xAMPRx_L|xAMPRx_M|xAMPRx_SS_256Mb|xAMPRx_S_KERNEL|xAMPRx_V,gr11 258 or gr8,gr11,gr8 259 260 movgs gr9,iamlr0 ; mapped from real address 0 261 movgs gr8,iampr0 ; cached kernel memory at 0xC0000000 262 movgs gr9,damlr0 263 movgs gr8,dampr0 264 265 # set a temporary mapping for the kernel running at address 0 until we've turned on the MMU 266 sethi.p %hi(__sdram_base),gr9 267 setlo %lo(__sdram_base),gr9 ; virtual address 268 269 and.p gr4,gr11,gr4 270 and gr5,gr11,gr5 271 or.p gr4,gr11,gr4 272 or gr5,gr11,gr5 273 274 movgs gr9,iamlr1 ; mapped from real address 0 275 movgs gr8,iampr1 ; cached kernel memory at 0x00000000 276 movgs gr9,damlr1 277 movgs gr8,dampr1 278 279 # we use DAMR2-10 for kmap_atomic(), cache flush and TLB management 280 # since the DAMLR regs are not going to change, we can set them now 281 # also set up IAMLR2 to the same as DAMLR5 282 sethi.p %hi(KMAP_ATOMIC_PRIMARY_FRAME),gr4 283 setlo %lo(KMAP_ATOMIC_PRIMARY_FRAME),gr4 284 sethi.p %hi(PAGE_SIZE),gr5 285 setlo %lo(PAGE_SIZE),gr5 286 287 movgs gr4,damlr2 288 movgs gr4,iamlr2 289 add gr4,gr5,gr4 290 movgs gr4,damlr3 291 add gr4,gr5,gr4 292 movgs gr4,damlr4 293 add gr4,gr5,gr4 294 movgs gr4,damlr5 295 add gr4,gr5,gr4 296 movgs gr4,damlr6 297 add gr4,gr5,gr4 298 movgs gr4,damlr7 299 add gr4,gr5,gr4 300 movgs gr4,damlr8 301 add gr4,gr5,gr4 302 movgs gr4,damlr9 303 add gr4,gr5,gr4 304 movgs gr4,damlr10 305 306 movgs gr0,dampr2 307 movgs gr0,dampr4 308 movgs gr0,dampr5 309 movgs gr0,dampr6 310 movgs gr0,dampr7 311 movgs gr0,dampr8 312 movgs gr0,dampr9 313 movgs gr0,dampr10 314 315 movgs gr0,iamlr3 316 movgs gr0,iamlr4 317 movgs gr0,iamlr5 318 movgs gr0,iamlr6 319 movgs gr0,iamlr7 320 321 movgs gr0,iampr2 322 movgs gr0,iampr3 323 movgs gr0,iampr4 324 movgs gr0,iampr5 325 movgs gr0,iampr6 326 movgs gr0,iampr7 327 328 # start in TLB context 0 with the swapper's page tables 329 movgs gr0,cxnr 330 331 sethi.p %hi(swapper_pg_dir),gr4 332 setlo %lo(swapper_pg_dir),gr4 333 sethi.p %hi(__page_offset),gr5 334 setlo %lo(__page_offset),gr5 335 sub gr4,gr5,gr4 336 movgs gr4,ttbr 337 setlos #xAMPRx_L|xAMPRx_M|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr5 338 or gr4,gr5,gr4 339 movgs gr4,dampr3 340 341 # the FR451 also has an extra trap base register 342 movsg tbr,gr4 343 movgs gr4,btbr 344 345 LEDS 0x3300 346 jmpl @(gr27,gr0) 347 348############################################################################### 349# 350# finish setting up the protection registers 351# 352############################################################################### 353 .globl __head_fr451_finalise_protection 354__head_fr451_finalise_protection: 355 # turn on the timers as appropriate 356 movgs gr0,timerh 357 movgs gr0,timerl 358 movgs gr0,timerd 359 movsg hsr0,gr4 360 sethi.p %hi(HSR0_ETMI),gr5 361 setlo %lo(HSR0_ETMI),gr5 362 or gr4,gr5,gr4 363 movgs gr4,hsr0 364 365 # clear the TLB entry cache 366 movgs gr0,iamlr1 367 movgs gr0,iampr1 368 movgs gr0,damlr1 369 movgs gr0,dampr1 370 371 # clear the PGE cache 372 sethi.p %hi(__flush_tlb_all),gr4 373 setlo %lo(__flush_tlb_all),gr4 374 jmpl @(gr4,gr0) 375