1/include/ "skeleton.dtsi" 2#include <dt-bindings/input/input.h> 3#include <dt-bindings/gpio/gpio.h> 4 5#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 6 7/ { 8 compatible = "marvell,kirkwood"; 9 interrupt-parent = <&intc>; 10 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu@0 { 16 device_type = "cpu"; 17 compatible = "marvell,feroceon"; 18 reg = <0>; 19 clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; 20 clock-names = "cpu_clk", "ddrclk", "powersave"; 21 }; 22 }; 23 24 aliases { 25 gpio0 = &gpio0; 26 gpio1 = &gpio1; 27 i2c0 = &i2c0; 28 }; 29 30 mbus { 31 compatible = "marvell,kirkwood-mbus", "simple-bus"; 32 #address-cells = <2>; 33 #size-cells = <1>; 34 /* If a board file needs to change this ranges it must replace it completely */ 35 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */ 36 MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */ 37 MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */ 38 >; 39 controller = <&mbusc>; 40 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ 41 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ 42 43 nand: nand@012f { 44 #address-cells = <1>; 45 #size-cells = <1>; 46 cle = <0>; 47 ale = <1>; 48 bank-width = <1>; 49 compatible = "marvell,orion-nand"; 50 reg = <MBUS_ID(0x01, 0x2f) 0 0x400>; 51 chip-delay = <25>; 52 /* set partition map and/or chip-delay in board dts */ 53 clocks = <&gate_clk 7>; 54 pinctrl-0 = <&pmx_nand>; 55 pinctrl-names = "default"; 56 status = "disabled"; 57 }; 58 59 crypto_sram: sa-sram@0301 { 60 compatible = "mmio-sram"; 61 reg = <MBUS_ID(0x03, 0x01) 0x0 0x800>; 62 clocks = <&gate_clk 17>; 63 #address-cells = <1>; 64 #size-cells = <1>; 65 }; 66 }; 67 68 ocp@f1000000 { 69 compatible = "simple-bus"; 70 ranges = <0x00000000 0xf1000000 0x0100000>; 71 #address-cells = <1>; 72 #size-cells = <1>; 73 74 pinctrl: pin-controller@10000 { 75 /* set compatible property in SoC file */ 76 reg = <0x10000 0x20>; 77 78 pmx_ge1: pmx-ge1 { 79 marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", 80 "mpp24", "mpp25", "mpp26", "mpp27", 81 "mpp30", "mpp31", "mpp32", "mpp33"; 82 marvell,function = "ge1"; 83 }; 84 85 pmx_nand: pmx-nand { 86 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", 87 "mpp4", "mpp5", "mpp18", "mpp19"; 88 marvell,function = "nand"; 89 }; 90 91 /* 92 * Default SPI0 pinctrl setting with CSn on mpp0, 93 * overwrite marvell,pins on board level if required. 94 */ 95 pmx_spi: pmx-spi { 96 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; 97 marvell,function = "spi"; 98 }; 99 100 pmx_twsi0: pmx-twsi0 { 101 marvell,pins = "mpp8", "mpp9"; 102 marvell,function = "twsi0"; 103 }; 104 105 /* 106 * Default UART pinctrl setting without RTS/CTS, 107 * overwrite marvell,pins on board level if required. 108 */ 109 pmx_uart0: pmx-uart0 { 110 marvell,pins = "mpp10", "mpp11"; 111 marvell,function = "uart0"; 112 }; 113 114 pmx_uart1: pmx-uart1 { 115 marvell,pins = "mpp13", "mpp14"; 116 marvell,function = "uart1"; 117 }; 118 }; 119 120 core_clk: core-clocks@10030 { 121 compatible = "marvell,kirkwood-core-clock"; 122 reg = <0x10030 0x4>; 123 #clock-cells = <1>; 124 }; 125 126 spi0: spi@10600 { 127 compatible = "marvell,orion-spi"; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 cell-index = <0>; 131 interrupts = <23>; 132 reg = <0x10600 0x28>; 133 clocks = <&gate_clk 7>; 134 pinctrl-0 = <&pmx_spi>; 135 pinctrl-names = "default"; 136 status = "disabled"; 137 }; 138 139 gpio0: gpio@10100 { 140 compatible = "marvell,orion-gpio"; 141 #gpio-cells = <2>; 142 gpio-controller; 143 reg = <0x10100 0x40>; 144 ngpios = <32>; 145 interrupt-controller; 146 #interrupt-cells = <2>; 147 interrupts = <35>, <36>, <37>, <38>; 148 clocks = <&gate_clk 7>; 149 }; 150 151 gpio1: gpio@10140 { 152 compatible = "marvell,orion-gpio"; 153 #gpio-cells = <2>; 154 gpio-controller; 155 reg = <0x10140 0x40>; 156 ngpios = <18>; 157 interrupt-controller; 158 #interrupt-cells = <2>; 159 interrupts = <39>, <40>, <41>; 160 clocks = <&gate_clk 7>; 161 }; 162 163 i2c0: i2c@11000 { 164 compatible = "marvell,mv64xxx-i2c"; 165 reg = <0x11000 0x20>; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 interrupts = <29>; 169 clock-frequency = <100000>; 170 clocks = <&gate_clk 7>; 171 pinctrl-0 = <&pmx_twsi0>; 172 pinctrl-names = "default"; 173 status = "disabled"; 174 }; 175 176 uart0: serial@12000 { 177 compatible = "ns16550a"; 178 reg = <0x12000 0x100>; 179 reg-shift = <2>; 180 interrupts = <33>; 181 clocks = <&gate_clk 7>; 182 pinctrl-0 = <&pmx_uart0>; 183 pinctrl-names = "default"; 184 status = "disabled"; 185 }; 186 187 uart1: serial@12100 { 188 compatible = "ns16550a"; 189 reg = <0x12100 0x100>; 190 reg-shift = <2>; 191 interrupts = <34>; 192 clocks = <&gate_clk 7>; 193 pinctrl-0 = <&pmx_uart1>; 194 pinctrl-names = "default"; 195 status = "disabled"; 196 }; 197 198 mbusc: mbus-controller@20000 { 199 compatible = "marvell,mbus-controller"; 200 reg = <0x20000 0x80>, <0x1500 0x20>; 201 }; 202 203 sysc: system-controller@20000 { 204 compatible = "marvell,orion-system-controller"; 205 reg = <0x20000 0x120>; 206 }; 207 208 bridge_intc: bridge-interrupt-ctrl@20110 { 209 compatible = "marvell,orion-bridge-intc"; 210 interrupt-controller; 211 #interrupt-cells = <1>; 212 reg = <0x20110 0x8>; 213 interrupts = <1>; 214 marvell,#interrupts = <6>; 215 }; 216 217 gate_clk: clock-gating-control@2011c { 218 compatible = "marvell,kirkwood-gating-clock"; 219 reg = <0x2011c 0x4>; 220 clocks = <&core_clk 0>; 221 #clock-cells = <1>; 222 }; 223 224 l2: l2-cache@20128 { 225 compatible = "marvell,kirkwood-cache"; 226 reg = <0x20128 0x4>; 227 }; 228 229 intc: main-interrupt-ctrl@20200 { 230 compatible = "marvell,orion-intc"; 231 interrupt-controller; 232 #interrupt-cells = <1>; 233 reg = <0x20200 0x10>, <0x20210 0x10>; 234 }; 235 236 timer: timer@20300 { 237 compatible = "marvell,orion-timer"; 238 reg = <0x20300 0x20>; 239 interrupt-parent = <&bridge_intc>; 240 interrupts = <1>, <2>; 241 clocks = <&core_clk 0>; 242 }; 243 244 wdt: watchdog-timer@20300 { 245 compatible = "marvell,orion-wdt"; 246 reg = <0x20300 0x28>, <0x20108 0x4>; 247 interrupt-parent = <&bridge_intc>; 248 interrupts = <3>; 249 clocks = <&gate_clk 7>; 250 status = "okay"; 251 }; 252 253 cesa: crypto@30000 { 254 compatible = "marvell,kirkwood-crypto"; 255 reg = <0x30000 0x10000>; 256 reg-names = "regs"; 257 interrupts = <22>; 258 clocks = <&gate_clk 17>; 259 marvell,crypto-srams = <&crypto_sram>; 260 marvell,crypto-sram-size = <0x800>; 261 status = "okay"; 262 }; 263 264 usb0: ehci@50000 { 265 compatible = "marvell,orion-ehci"; 266 reg = <0x50000 0x1000>; 267 interrupts = <19>; 268 clocks = <&gate_clk 3>; 269 status = "okay"; 270 }; 271 272 dma0: xor@60800 { 273 compatible = "marvell,orion-xor"; 274 reg = <0x60800 0x100 275 0x60A00 0x100>; 276 status = "okay"; 277 clocks = <&gate_clk 8>; 278 279 xor00 { 280 interrupts = <5>; 281 dmacap,memcpy; 282 dmacap,xor; 283 }; 284 xor01 { 285 interrupts = <6>; 286 dmacap,memcpy; 287 dmacap,xor; 288 dmacap,memset; 289 }; 290 }; 291 292 dma1: xor@60900 { 293 compatible = "marvell,orion-xor"; 294 reg = <0x60900 0x100 295 0x60B00 0x100>; 296 status = "okay"; 297 clocks = <&gate_clk 16>; 298 299 xor00 { 300 interrupts = <7>; 301 dmacap,memcpy; 302 dmacap,xor; 303 }; 304 xor01 { 305 interrupts = <8>; 306 dmacap,memcpy; 307 dmacap,xor; 308 dmacap,memset; 309 }; 310 }; 311 312 eth0: ethernet-controller@72000 { 313 compatible = "marvell,kirkwood-eth"; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 reg = <0x72000 0x4000>; 317 clocks = <&gate_clk 0>; 318 marvell,tx-checksum-limit = <1600>; 319 status = "disabled"; 320 321 eth0port: ethernet0-port@0 { 322 compatible = "marvell,kirkwood-eth-port"; 323 reg = <0>; 324 interrupts = <11>; 325 /* overwrite MAC address in bootloader */ 326 local-mac-address = [00 00 00 00 00 00]; 327 /* set phy-handle property in board file */ 328 }; 329 }; 330 331 mdio: mdio-bus@72004 { 332 compatible = "marvell,orion-mdio"; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 reg = <0x72004 0x84>; 336 interrupts = <46>; 337 clocks = <&gate_clk 0>; 338 status = "disabled"; 339 340 /* add phy nodes in board file */ 341 }; 342 343 eth1: ethernet-controller@76000 { 344 compatible = "marvell,kirkwood-eth"; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 reg = <0x76000 0x4000>; 348 clocks = <&gate_clk 19>; 349 marvell,tx-checksum-limit = <1600>; 350 pinctrl-0 = <&pmx_ge1>; 351 pinctrl-names = "default"; 352 status = "disabled"; 353 354 eth1port: ethernet1-port@0 { 355 compatible = "marvell,kirkwood-eth-port"; 356 reg = <0>; 357 interrupts = <15>; 358 /* overwrite MAC address in bootloader */ 359 local-mac-address = [00 00 00 00 00 00]; 360 /* set phy-handle property in board file */ 361 }; 362 }; 363 364 sata_phy0: sata-phy@82000 { 365 compatible = "marvell,mvebu-sata-phy"; 366 reg = <0x82000 0x0334>; 367 clocks = <&gate_clk 14>; 368 clock-names = "sata"; 369 #phy-cells = <0>; 370 status = "ok"; 371 }; 372 373 sata_phy1: sata-phy@84000 { 374 compatible = "marvell,mvebu-sata-phy"; 375 reg = <0x84000 0x0334>; 376 clocks = <&gate_clk 15>; 377 clock-names = "sata"; 378 #phy-cells = <0>; 379 status = "ok"; 380 }; 381 382 audio0: audio-controller@a0000 { 383 compatible = "marvell,kirkwood-audio"; 384 #sound-dai-cells = <0>; 385 reg = <0xa0000 0x2210>; 386 interrupts = <24>; 387 clocks = <&gate_clk 9>; 388 clock-names = "internal"; 389 status = "disabled"; 390 }; 391 }; 392}; 393