1 /* 2 * arch/arm/mach-w90x900/include/mach/regs-serial.h 3 * 4 * Copyright (c) 2009 Nuvoton technology corporation 5 * All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * Description: 13 * Nuvoton Display, LCM Register list 14 * Author: Wang Qiang (rurality.linux@gmail.com) 2009/12/11 15 * 16 */ 17 18 19 #ifndef __ASM_ARM_W90X900_REGS_LDM_H 20 #define __ASM_ARM_W90X900_REGS_LDM_H 21 22 #include <mach/map.h> 23 24 /* Display Controller Control/Status Register */ 25 #define REG_LCM_DCCS (0x00) 26 27 #define LCM_DCCS_ENG_RST (1 << 0) 28 #define LCM_DCCS_VA_EN (1 << 1) 29 #define LCM_DCCS_OSD_EN (1 << 2) 30 #define LCM_DCCS_DISP_OUT_EN (1 << 3) 31 #define LCM_DCCS_DISP_INT_EN (1 << 4) 32 #define LCM_DCCS_CMD_ON (1 << 5) 33 #define LCM_DCCS_FIELD_INTR (1 << 6) 34 #define LCM_DCCS_SINGLE (1 << 7) 35 36 enum LCM_DCCS_VA_SRC { 37 LCM_DCCS_VA_SRC_YUV422 = (0 << 8), 38 LCM_DCCS_VA_SRC_YCBCR422 = (1 << 8), 39 LCM_DCCS_VA_SRC_RGB888 = (2 << 8), 40 LCM_DCCS_VA_SRC_RGB666 = (3 << 8), 41 LCM_DCCS_VA_SRC_RGB565 = (4 << 8), 42 LCM_DCCS_VA_SRC_RGB444LOW = (5 << 8), 43 LCM_DCCS_VA_SRC_RGB444HIGH = (7 << 8) 44 }; 45 46 47 /* Display Device Control Register */ 48 #define REG_LCM_DEV_CTRL (0x04) 49 50 enum LCM_DEV_CTRL_SWAP_YCbCr { 51 LCM_DEV_CTRL_SWAP_UYVY = (0 << 1), 52 LCM_DEV_CTRL_SWAP_YUYV = (1 << 1), 53 LCM_DEV_CTRL_SWAP_VYUY = (2 << 1), 54 LCM_DEV_CTRL_SWAP_YVYU = (3 << 1) 55 }; 56 57 enum LCM_DEV_CTRL_RGB_SHIFT { 58 LCM_DEV_CTRL_RGB_SHIFT_NOT = (0 << 3), 59 LCM_DEV_CTRL_RGB_SHIFT_ONECYCLE = (1 << 3), 60 LCM_DEV_CTRL_RGB_SHIFT_TWOCYCLE = (2 << 3), 61 LCM_DEV_CTRL_RGB_SHIFT_NOT_DEF = (3 << 3) 62 }; 63 64 enum LCM_DEV_CTRL_DEVICE { 65 LCM_DEV_CTRL_DEVICE_YUV422 = (0 << 5), 66 LCM_DEV_CTRL_DEVICE_YUV444 = (1 << 5), 67 LCM_DEV_CTRL_DEVICE_UNIPAC = (4 << 5), 68 LCM_DEV_CTRL_DEVICE_SEIKO_EPSON = (5 << 5), 69 LCM_DEV_CTRL_DEVICE_HIGH_COLOR = (6 << 5), 70 LCM_DEV_CTRL_DEVICE_MPU = (7 << 5) 71 }; 72 73 #define LCM_DEV_CTRL_LCD_DDA (8) 74 #define LCM_DEV_CTRL_YUV2CCIR (16) 75 76 enum LCM_DEV_CTRL_LCD_SEL { 77 LCM_DEV_CTRL_LCD_SEL_RGB_GBR = (0 << 17), 78 LCM_DEV_CTRL_LCD_SEL_BGR_RBG = (1 << 17), 79 LCM_DEV_CTRL_LCD_SEL_GBR_RGB = (2 << 17), 80 LCM_DEV_CTRL_LCD_SEL_RBG_BGR = (3 << 17) 81 }; 82 83 enum LCM_DEV_CTRL_FAL_D { 84 LCM_DEV_CTRL_FAL_D_FALLING = (0 << 19), 85 LCM_DEV_CTRL_FAL_D_RISING = (1 << 19), 86 }; 87 88 enum LCM_DEV_CTRL_H_POL { 89 LCM_DEV_CTRL_H_POL_LOW = (0 << 20), 90 LCM_DEV_CTRL_H_POL_HIGH = (1 << 20), 91 }; 92 93 enum LCM_DEV_CTRL_V_POL { 94 LCM_DEV_CTRL_V_POL_LOW = (0 << 21), 95 LCM_DEV_CTRL_V_POL_HIGH = (1 << 21), 96 }; 97 98 enum LCM_DEV_CTRL_VR_LACE { 99 LCM_DEV_CTRL_VR_LACE_NINTERLACE = (0 << 22), 100 LCM_DEV_CTRL_VR_LACE_INTERLACE = (1 << 22), 101 }; 102 103 enum LCM_DEV_CTRL_LACE { 104 LCM_DEV_CTRL_LACE_NINTERLACE = (0 << 23), 105 LCM_DEV_CTRL_LACE_INTERLACE = (1 << 23), 106 }; 107 108 enum LCM_DEV_CTRL_RGB_SCALE { 109 LCM_DEV_CTRL_RGB_SCALE_4096 = (0 << 24), 110 LCM_DEV_CTRL_RGB_SCALE_65536 = (1 << 24), 111 LCM_DEV_CTRL_RGB_SCALE_262144 = (2 << 24), 112 LCM_DEV_CTRL_RGB_SCALE_16777216 = (3 << 24), 113 }; 114 115 enum LCM_DEV_CTRL_DBWORD { 116 LCM_DEV_CTRL_DBWORD_HALFWORD = (0 << 26), 117 LCM_DEV_CTRL_DBWORD_FULLWORD = (1 << 26), 118 }; 119 120 enum LCM_DEV_CTRL_MPU68 { 121 LCM_DEV_CTRL_MPU68_80_SERIES = (0 << 27), 122 LCM_DEV_CTRL_MPU68_68_SERIES = (1 << 27), 123 }; 124 125 enum LCM_DEV_CTRL_DE_POL { 126 LCM_DEV_CTRL_DE_POL_HIGH = (0 << 28), 127 LCM_DEV_CTRL_DE_POL_LOW = (1 << 28), 128 }; 129 130 #define LCM_DEV_CTRL_CMD16 (29) 131 #define LCM_DEV_CTRL_CM16t18 (30) 132 #define LCM_DEV_CTRL_CMD_LOW (31) 133 134 /* MPU-Interface LCD Write Command */ 135 #define REG_LCM_MPU_CMD (0x08) 136 137 /* Interrupt Control/Status Register */ 138 #define REG_LCM_INT_CS (0x0c) 139 #define LCM_INT_CS_DISP_F_EN (1 << 0) 140 #define LCM_INT_CS_UNDERRUN_EN (1 << 1) 141 #define LCM_INT_CS_BUS_ERROR_INT (1 << 28) 142 #define LCM_INT_CS_UNDERRUN_INT (1 << 29) 143 #define LCM_INT_CS_DISP_F_STATUS (1 << 30) 144 #define LCM_INT_CS_DISP_F_INT (1 << 31) 145 146 /* CRTC Display Size Control Register */ 147 #define REG_LCM_CRTC_SIZE (0x10) 148 #define LCM_CRTC_SIZE_VTTVAL(x) ((x) << 16) 149 #define LCM_CRTC_SIZE_HTTVAL(x) ((x) << 0) 150 151 /* CRTC Display Enable End */ 152 #define REG_LCM_CRTC_DEND (0x14) 153 #define LCM_CRTC_DEND_VDENDVAL(x) ((x) << 16) 154 #define LCM_CRTC_DEND_HDENDVAL(x) ((x) << 0) 155 156 /* CRTC Internal Horizontal Retrace Control Register */ 157 #define REG_LCM_CRTC_HR (0x18) 158 #define LCM_CRTC_HR_EVAL(x) ((x) << 16) 159 #define LCM_CRTC_HR_SVAL(x) ((x) << 0) 160 161 /* CRTC Horizontal Sync Control Register */ 162 #define REG_LCM_CRTC_HSYNC (0x1C) 163 #define LCM_CRTC_HSYNC_SHIFTVAL(x) ((x) << 30) 164 #define LCM_CRTC_HSYNC_EVAL(x) ((x) << 16) 165 #define LCM_CRTC_HSYNC_SVAL(x) ((x) << 0) 166 167 /* CRTC Internal Vertical Retrace Control Register */ 168 #define REG_LCM_CRTC_VR (0x20) 169 #define LCM_CRTC_VR_EVAL(x) ((x) << 16) 170 #define LCM_CRTC_VR_SVAL(x) ((x) << 0) 171 172 /* Video Stream Frame Buffer-0 Starting Address */ 173 #define REG_LCM_VA_BADDR0 (0x24) 174 175 /* Video Stream Frame Buffer-1 Starting Address */ 176 #define REG_LCM_VA_BADDR1 (0x28) 177 178 /* Video Stream Frame Buffer Control Register */ 179 #define REG_LCM_VA_FBCTRL (0x2C) 180 #define LCM_VA_FBCTRL_IO_REGION_HALF (1 << 28) 181 #define LCM_VA_FBCTRL_FIELD_DUAL (1 << 29) 182 #define LCM_VA_FBCTRL_START_BUF (1 << 30) 183 #define LCM_VA_FBCTRL_DB_EN (1 << 31) 184 185 /* Video Stream Scaling Control Register */ 186 #define REG_LCM_VA_SCALE (0x30) 187 #define LCM_VA_SCALE_XCOPY_INTERPOLATION (0 << 15) 188 #define LCM_VA_SCALE_XCOPY_DUPLICATION (1 << 15) 189 190 /* Image Stream Active Window Coordinates */ 191 #define REG_LCM_VA_WIN (0x38) 192 193 /* Image Stream Stuff Pixel */ 194 #define REG_LCM_VA_STUFF (0x3C) 195 196 /* OSD Window Starting Coordinates */ 197 #define REG_LCM_OSD_WINS (0x40) 198 199 /* OSD Window Ending Coordinates */ 200 #define REG_LCM_OSD_WINE (0x44) 201 202 /* OSD Stream Frame Buffer Starting Address */ 203 #define REG_LCM_OSD_BADDR (0x48) 204 205 /* OSD Stream Frame Buffer Control Register */ 206 #define REG_LCM_OSD_FBCTRL (0x4c) 207 208 /* OSD Overlay Control Register */ 209 #define REG_LCM_OSD_OVERLAY (0x50) 210 211 /* OSD Overlay Color-Key Pattern Register */ 212 #define REG_LCM_OSD_CKEY (0x54) 213 214 /* OSD Overlay Color-Key Mask Register */ 215 #define REG_LCM_OSD_CMASK (0x58) 216 217 /* OSD Window Skip1 Register */ 218 #define REG_LCM_OSD_SKIP1 (0x5C) 219 220 /* OSD Window Skip2 Register */ 221 #define REG_LCM_OSD_SKIP2 (0x60) 222 223 /* OSD horizontal up scaling control register */ 224 #define REG_LCM_OSD_SCALE (0x64) 225 226 /* MPU Vsync control register */ 227 #define REG_LCM_MPU_VSYNC (0x68) 228 229 /* Hardware cursor control Register */ 230 #define REG_LCM_HC_CTRL (0x6C) 231 232 /* Hardware cursot tip point potison on va picture */ 233 #define REG_LCM_HC_POS (0x70) 234 235 /* Hardware Cursor Window Buffer Control Register */ 236 #define REG_LCM_HC_WBCTRL (0x74) 237 238 /* Hardware cursor memory base address register */ 239 #define REG_LCM_HC_BADDR (0x78) 240 241 /* Hardware cursor color ram register mapped to bpp = 0 */ 242 #define REG_LCM_HC_COLOR0 (0x7C) 243 244 /* Hardware cursor color ram register mapped to bpp = 1 */ 245 #define REG_LCM_HC_COLOR1 (0x80) 246 247 /* Hardware cursor color ram register mapped to bpp = 2 */ 248 #define REG_LCM_HC_COLOR2 (0x84) 249 250 /* Hardware cursor color ram register mapped to bpp = 3 */ 251 #define REG_LCM_HC_COLOR3 (0x88) 252 253 #endif /* __ASM_ARM_W90X900_REGS_LDM_H */ 254