1 #ifndef __ASM_SH_HITACHI_SE_H 2 #define __ASM_SH_HITACHI_SE_H 3 4 /* 5 * linux/include/asm-sh/hitachi_se.h 6 * 7 * Copyright (C) 2000 Kazumoto Kojima 8 * 9 * Hitachi SolutionEngine support 10 */ 11 #include <linux/sh_intc.h> 12 13 /* Box specific addresses. */ 14 15 #define PA_ROM 0x00000000 /* EPROM */ 16 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ 17 #define PA_FROM 0x01000000 /* EPROM */ 18 #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ 19 #define PA_EXT1 0x04000000 20 #define PA_EXT1_SIZE 0x04000000 21 #define PA_EXT2 0x08000000 22 #define PA_EXT2_SIZE 0x04000000 23 #define PA_SDRAM 0x0c000000 24 #define PA_SDRAM_SIZE 0x04000000 25 26 #define PA_EXT4 0x12000000 27 #define PA_EXT4_SIZE 0x02000000 28 #define PA_EXT5 0x14000000 29 #define PA_EXT5_SIZE 0x04000000 30 #define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ 31 32 #define PA_83902 0xb0000000 /* DP83902A */ 33 #define PA_83902_IF 0xb0040000 /* DP83902A remote io port */ 34 #define PA_83902_RST 0xb0080000 /* DP83902A reset port */ 35 36 #define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */ 37 #define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */ 38 #define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */ 39 #define PA_LED 0xb0c00000 /* LED */ 40 #if defined(CONFIG_CPU_SUBTYPE_SH7705) 41 #define PA_BCR 0xb0e00000 42 #else 43 #define PA_BCR 0xb1400000 /* FPGA */ 44 #endif 45 46 #define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ 47 #define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ 48 #define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ 49 #define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ 50 #define MRSHPC_OPTION (PA_MRSHPC + 6) 51 #define MRSHPC_CSR (PA_MRSHPC + 8) 52 #define MRSHPC_ISR (PA_MRSHPC + 10) 53 #define MRSHPC_ICR (PA_MRSHPC + 12) 54 #define MRSHPC_CPWCR (PA_MRSHPC + 14) 55 #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) 56 #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) 57 #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) 58 #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) 59 #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) 60 #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) 61 #define MRSHPC_CDCR (PA_MRSHPC + 28) 62 #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) 63 64 #define BCR_ILCRA (PA_BCR + 0) 65 #define BCR_ILCRB (PA_BCR + 2) 66 #define BCR_ILCRC (PA_BCR + 4) 67 #define BCR_ILCRD (PA_BCR + 6) 68 #define BCR_ILCRE (PA_BCR + 8) 69 #define BCR_ILCRF (PA_BCR + 10) 70 #define BCR_ILCRG (PA_BCR + 12) 71 72 #if defined(CONFIG_CPU_SUBTYPE_SH7709) 73 #define INTC_IRR0 0xa4000004UL 74 #define INTC_IRR1 0xa4000006UL 75 #define INTC_IRR2 0xa4000008UL 76 77 #define INTC_ICR0 0xfffffee0UL 78 #define INTC_ICR1 0xa4000010UL 79 #define INTC_ICR2 0xa4000012UL 80 #define INTC_INTER 0xa4000014UL 81 82 #define INTC_IPRC 0xa4000016UL 83 #define INTC_IPRD 0xa4000018UL 84 #define INTC_IPRE 0xa400001aUL 85 86 #define IRQ0_IRQ evt2irq(0x600) 87 #define IRQ1_IRQ evt2irq(0x620) 88 #endif 89 90 #if defined(CONFIG_CPU_SUBTYPE_SH7705) 91 #define IRQ_STNIC evt2irq(0x380) 92 #define IRQ_CFCARD evt2irq(0x3c0) 93 #else 94 #define IRQ_STNIC evt2irq(0x340) 95 #define IRQ_CFCARD evt2irq(0x2e0) 96 #endif 97 98 /* SH Ether support (SH7710/SH7712) */ 99 /* Base address */ 100 #define SH_ETH0_BASE 0xA7000000 101 #define SH_ETH1_BASE 0xA7000400 102 /* PHY ID */ 103 #if defined(CONFIG_CPU_SUBTYPE_SH7710) 104 # define PHY_ID 0x00 105 #elif defined(CONFIG_CPU_SUBTYPE_SH7712) 106 # define PHY_ID 0x01 107 #endif 108 /* Ether IRQ */ 109 #define SH_ETH0_IRQ evt2irq(0xc00) 110 #define SH_ETH1_IRQ evt2irq(0xc20) 111 #define SH_TSU_IRQ evt2irq(0xc40) 112 113 void init_se_IRQ(void); 114 115 #define __IO_PREFIX se 116 #include <asm/io_generic.h> 117 118 #endif /* __ASM_SH_HITACHI_SE_H */ 119