1 /*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #ifndef _MLX4_EN_H_
35 #define _MLX4_EN_H_
36
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #include <linux/net_tstamp.h>
44 #ifdef CONFIG_MLX4_EN_DCB
45 #include <linux/dcbnl.h>
46 #endif
47 #include <linux/cpu_rmap.h>
48 #include <linux/ptp_clock_kernel.h>
49
50 #include <linux/mlx4/device.h>
51 #include <linux/mlx4/qp.h>
52 #include <linux/mlx4/cq.h>
53 #include <linux/mlx4/srq.h>
54 #include <linux/mlx4/doorbell.h>
55 #include <linux/mlx4/cmd.h>
56
57 #include "en_port.h"
58 #include "mlx4_stats.h"
59
60 #define DRV_NAME "mlx4_en"
61 #define DRV_VERSION "2.2-1"
62 #define DRV_RELDATE "Feb 2014"
63
64 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
65
66 /*
67 * Device constants
68 */
69
70
71 #define MLX4_EN_PAGE_SHIFT 12
72 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
73 #define DEF_RX_RINGS 16
74 #define MAX_RX_RINGS 128
75 #define MIN_RX_RINGS 4
76 #define TXBB_SIZE 64
77 #define HEADROOM (2048 / TXBB_SIZE + 1)
78 #define STAMP_STRIDE 64
79 #define STAMP_DWORDS (STAMP_STRIDE / 4)
80 #define STAMP_SHIFT 31
81 #define STAMP_VAL 0x7fffffff
82 #define STATS_DELAY (HZ / 4)
83 #define SERVICE_TASK_DELAY (HZ / 4)
84 #define MAX_NUM_OF_FS_RULES 256
85
86 #define MLX4_EN_FILTER_HASH_SHIFT 4
87 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
88
89 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
90 #define MAX_DESC_SIZE 512
91 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
92
93 /*
94 * OS related constants and tunables
95 */
96
97 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
98 #define MLX4_EN_PRIV_FLAGS_PHV 2
99
100 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
101
102 /* Use the maximum between 16384 and a single page */
103 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
104
105 #define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER
106
107 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU
108 * and 4K allocations) */
109 enum {
110 FRAG_SZ0 = 1536 - NET_IP_ALIGN,
111 FRAG_SZ1 = 4096,
112 FRAG_SZ2 = 4096,
113 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
114 };
115 #define MLX4_EN_MAX_RX_FRAGS 4
116
117 /* Maximum ring sizes */
118 #define MLX4_EN_MAX_TX_SIZE 8192
119 #define MLX4_EN_MAX_RX_SIZE 8192
120
121 /* Minimum ring size for our page-allocation scheme to work */
122 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
123 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
124
125 #define MLX4_EN_SMALL_PKT_SIZE 64
126 #define MLX4_EN_MIN_TX_RING_P_UP 1
127 #define MLX4_EN_MAX_TX_RING_P_UP 32
128 #define MLX4_EN_NUM_UP 8
129 #define MLX4_EN_DEF_TX_RING_SIZE 512
130 #define MLX4_EN_DEF_RX_RING_SIZE 1024
131 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
132 MLX4_EN_NUM_UP)
133
134 #define MLX4_EN_DEFAULT_TX_WORK 256
135
136 /* Target number of packets to coalesce with interrupt moderation */
137 #define MLX4_EN_RX_COAL_TARGET 44
138 #define MLX4_EN_RX_COAL_TIME 0x10
139
140 #define MLX4_EN_TX_COAL_PKTS 16
141 #define MLX4_EN_TX_COAL_TIME 0x10
142
143 #define MLX4_EN_MAX_COAL_PKTS U16_MAX
144 #define MLX4_EN_MAX_COAL_TIME U16_MAX
145
146 #define MLX4_EN_RX_RATE_LOW 400000
147 #define MLX4_EN_RX_COAL_TIME_LOW 0
148 #define MLX4_EN_RX_RATE_HIGH 450000
149 #define MLX4_EN_RX_COAL_TIME_HIGH 128
150 #define MLX4_EN_RX_SIZE_THRESH 1024
151 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
152 #define MLX4_EN_SAMPLE_INTERVAL 0
153 #define MLX4_EN_AVG_PKT_SMALL 256
154
155 #define MLX4_EN_AUTO_CONF 0xffff
156
157 #define MLX4_EN_DEF_RX_PAUSE 1
158 #define MLX4_EN_DEF_TX_PAUSE 1
159
160 /* Interval between successive polls in the Tx routine when polling is used
161 instead of interrupts (in per-core Tx rings) - should be power of 2 */
162 #define MLX4_EN_TX_POLL_MODER 16
163 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
164
165 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
166 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
167 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
168
169 #define MLX4_EN_MIN_MTU 46
170 #define ETH_BCAST 0xffffffffffffULL
171
172 #define MLX4_EN_LOOPBACK_RETRIES 5
173 #define MLX4_EN_LOOPBACK_TIMEOUT 100
174
175 #ifdef MLX4_EN_PERF_STAT
176 /* Number of samples to 'average' */
177 #define AVG_SIZE 128
178 #define AVG_FACTOR 1024
179
180 #define INC_PERF_COUNTER(cnt) (++(cnt))
181 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
182 #define AVG_PERF_COUNTER(cnt, sample) \
183 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
184 #define GET_PERF_COUNTER(cnt) (cnt)
185 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
186
187 #else
188
189 #define INC_PERF_COUNTER(cnt) do {} while (0)
190 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
191 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
192 #define GET_PERF_COUNTER(cnt) (0)
193 #define GET_AVG_PERF_COUNTER(cnt) (0)
194 #endif /* MLX4_EN_PERF_STAT */
195
196 /* Constants for TX flow */
197 enum {
198 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
199 MAX_BF = 256,
200 MIN_PKT_LEN = 17,
201 };
202
203 /*
204 * Configurables
205 */
206
207 enum cq_type {
208 RX = 0,
209 TX = 1,
210 };
211
212
213 /*
214 * Useful macros
215 */
216 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
217 #define XNOR(x, y) (!(x) == !(y))
218
219
220 struct mlx4_en_tx_info {
221 struct sk_buff *skb;
222 dma_addr_t map0_dma;
223 u32 map0_byte_count;
224 u32 nr_txbb;
225 u32 nr_bytes;
226 u8 linear;
227 u8 data_offset;
228 u8 inl;
229 u8 ts_requested;
230 u8 nr_maps;
231 } ____cacheline_aligned_in_smp;
232
233
234 #define MLX4_EN_BIT_DESC_OWN 0x80000000
235 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
236 #define MLX4_EN_MEMTYPE_PAD 0x100
237 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
238
239
240 struct mlx4_en_tx_desc {
241 struct mlx4_wqe_ctrl_seg ctrl;
242 union {
243 struct mlx4_wqe_data_seg data; /* at least one data segment */
244 struct mlx4_wqe_lso_seg lso;
245 struct mlx4_wqe_inline_seg inl;
246 };
247 };
248
249 #define MLX4_EN_USE_SRQ 0x01000000
250
251 #define MLX4_EN_CX3_LOW_ID 0x1000
252 #define MLX4_EN_CX3_HIGH_ID 0x1005
253
254 struct mlx4_en_rx_alloc {
255 struct page *page;
256 dma_addr_t dma;
257 u32 page_offset;
258 u32 page_size;
259 };
260
261 struct mlx4_en_tx_ring {
262 /* cache line used and dirtied in tx completion
263 * (mlx4_en_free_tx_buf())
264 */
265 u32 last_nr_txbb;
266 u32 cons;
267 unsigned long wake_queue;
268
269 /* cache line used and dirtied in mlx4_en_xmit() */
270 u32 prod ____cacheline_aligned_in_smp;
271 unsigned long bytes;
272 unsigned long packets;
273 unsigned long tx_csum;
274 unsigned long tso_packets;
275 unsigned long xmit_more;
276 struct mlx4_bf bf;
277 unsigned long queue_stopped;
278
279 /* Following part should be mostly read */
280 cpumask_t affinity_mask;
281 struct mlx4_qp qp;
282 struct mlx4_hwq_resources wqres;
283 u32 size; /* number of TXBBs */
284 u32 size_mask;
285 u16 stride;
286 u32 full_size;
287 u16 cqn; /* index of port CQ associated with this ring */
288 u32 buf_size;
289 __be32 doorbell_qpn;
290 __be32 mr_key;
291 void *buf;
292 struct mlx4_en_tx_info *tx_info;
293 u8 *bounce_buf;
294 struct mlx4_qp_context context;
295 int qpn;
296 enum mlx4_qp_state qp_state;
297 u8 queue_index;
298 bool bf_enabled;
299 bool bf_alloced;
300 struct netdev_queue *tx_queue;
301 int hwtstamp_tx_type;
302 } ____cacheline_aligned_in_smp;
303
304 struct mlx4_en_rx_desc {
305 /* actual number of entries depends on rx ring stride */
306 struct mlx4_wqe_data_seg data[0];
307 };
308
309 struct mlx4_en_rx_ring {
310 struct mlx4_hwq_resources wqres;
311 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
312 u32 size ; /* number of Rx descs*/
313 u32 actual_size;
314 u32 size_mask;
315 u16 stride;
316 u16 log_stride;
317 u16 cqn; /* index of port CQ associated with this ring */
318 u32 prod;
319 u32 cons;
320 u32 buf_size;
321 u8 fcs_del;
322 void *buf;
323 void *rx_info;
324 unsigned long bytes;
325 unsigned long packets;
326 #ifdef CONFIG_NET_RX_BUSY_POLL
327 unsigned long yields;
328 unsigned long misses;
329 unsigned long cleaned;
330 #endif
331 unsigned long csum_ok;
332 unsigned long csum_none;
333 unsigned long csum_complete;
334 int hwtstamp_rx_filter;
335 cpumask_var_t affinity_mask;
336 };
337
338 struct mlx4_en_cq {
339 struct mlx4_cq mcq;
340 struct mlx4_hwq_resources wqres;
341 int ring;
342 struct net_device *dev;
343 struct napi_struct napi;
344 int size;
345 int buf_size;
346 int vector;
347 enum cq_type is_tx;
348 u16 moder_time;
349 u16 moder_cnt;
350 struct mlx4_cqe *buf;
351 #define MLX4_EN_OPCODE_ERROR 0x1e
352
353 #ifdef CONFIG_NET_RX_BUSY_POLL
354 unsigned int state;
355 #define MLX4_EN_CQ_STATE_IDLE 0
356 #define MLX4_EN_CQ_STATE_NAPI 1 /* NAPI owns this CQ */
357 #define MLX4_EN_CQ_STATE_POLL 2 /* poll owns this CQ */
358 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL)
359 #define MLX4_EN_CQ_STATE_NAPI_YIELD 4 /* NAPI yielded this CQ */
360 #define MLX4_EN_CQ_STATE_POLL_YIELD 8 /* poll yielded this CQ */
361 #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD)
362 #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD)
363 spinlock_t poll_lock; /* protects from LLS/napi conflicts */
364 #endif /* CONFIG_NET_RX_BUSY_POLL */
365 struct irq_desc *irq_desc;
366 };
367
368 struct mlx4_en_port_profile {
369 u32 flags;
370 u32 tx_ring_num;
371 u32 rx_ring_num;
372 u32 tx_ring_size;
373 u32 rx_ring_size;
374 u8 rx_pause;
375 u8 rx_ppp;
376 u8 tx_pause;
377 u8 tx_ppp;
378 int rss_rings;
379 int inline_thold;
380 };
381
382 struct mlx4_en_profile {
383 int udp_rss;
384 u8 rss_mask;
385 u32 active_ports;
386 u32 small_pkt_int;
387 u8 no_reset;
388 u8 num_tx_rings_p_up;
389 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
390 };
391
392 struct mlx4_en_dev {
393 struct mlx4_dev *dev;
394 struct pci_dev *pdev;
395 struct mutex state_lock;
396 struct net_device *pndev[MLX4_MAX_PORTS + 1];
397 struct net_device *upper[MLX4_MAX_PORTS + 1];
398 u32 port_cnt;
399 bool device_up;
400 struct mlx4_en_profile profile;
401 u32 LSO_support;
402 struct workqueue_struct *workqueue;
403 struct device *dma_device;
404 void __iomem *uar_map;
405 struct mlx4_uar priv_uar;
406 struct mlx4_mr mr;
407 u32 priv_pdn;
408 spinlock_t uar_lock;
409 u8 mac_removed[MLX4_MAX_PORTS + 1];
410 rwlock_t clock_lock;
411 u32 nominal_c_mult;
412 struct cyclecounter cycles;
413 struct timecounter clock;
414 unsigned long last_overflow_check;
415 struct ptp_clock *ptp_clock;
416 struct ptp_clock_info ptp_clock_info;
417 struct notifier_block nb;
418 };
419
420
421 struct mlx4_en_rss_map {
422 int base_qpn;
423 struct mlx4_qp qps[MAX_RX_RINGS];
424 enum mlx4_qp_state state[MAX_RX_RINGS];
425 struct mlx4_qp indir_qp;
426 enum mlx4_qp_state indir_state;
427 };
428
429 enum mlx4_en_port_flag {
430 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
431 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
432 };
433
434 struct mlx4_en_port_state {
435 int link_state;
436 int link_speed;
437 int transceiver;
438 u32 flags;
439 };
440
441 enum mlx4_en_mclist_act {
442 MCLIST_NONE,
443 MCLIST_REM,
444 MCLIST_ADD,
445 };
446
447 struct mlx4_en_mc_list {
448 struct list_head list;
449 enum mlx4_en_mclist_act action;
450 u8 addr[ETH_ALEN];
451 u64 reg_id;
452 u64 tunnel_reg_id;
453 };
454
455 struct mlx4_en_frag_info {
456 u16 frag_size;
457 u16 frag_prefix_size;
458 u16 frag_stride;
459 };
460
461 #ifdef CONFIG_MLX4_EN_DCB
462 /* Minimal TC BW - setting to 0 will block traffic */
463 #define MLX4_EN_BW_MIN 1
464 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
465
466 #define MLX4_EN_TC_ETS 7
467
468 #endif
469
470 struct ethtool_flow_id {
471 struct list_head list;
472 struct ethtool_rx_flow_spec flow_spec;
473 u64 id;
474 };
475
476 enum {
477 MLX4_EN_FLAG_PROMISC = (1 << 0),
478 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
479 /* whether we need to enable hardware loopback by putting dmac
480 * in Tx WQE
481 */
482 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
483 /* whether we need to drop packets that hardware loopback-ed */
484 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
485 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4),
486 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5),
487 };
488
489 #define PORT_BEACON_MAX_LIMIT (65535)
490 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
491 #define MLX4_EN_MAC_HASH_IDX 5
492
493 struct mlx4_en_stats_bitmap {
494 DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
495 struct mutex mutex; /* for mutual access to stats bitmap */
496 };
497
498 enum {
499 MLX4_EN_STATE_FLAG_RESTARTING,
500 };
501
502 struct mlx4_en_priv {
503 struct mlx4_en_dev *mdev;
504 struct mlx4_en_port_profile *prof;
505 struct net_device *dev;
506 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
507 struct net_device_stats stats;
508 struct net_device_stats ret_stats;
509 struct mlx4_en_port_state port_state;
510 spinlock_t stats_lock;
511 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
512 /* To allow rules removal while port is going down */
513 struct list_head ethtool_list;
514
515 unsigned long last_moder_packets[MAX_RX_RINGS];
516 unsigned long last_moder_tx_packets;
517 unsigned long last_moder_bytes[MAX_RX_RINGS];
518 unsigned long last_moder_jiffies;
519 int last_moder_time[MAX_RX_RINGS];
520 u16 rx_usecs;
521 u16 rx_frames;
522 u16 tx_usecs;
523 u16 tx_frames;
524 u32 pkt_rate_low;
525 u16 rx_usecs_low;
526 u32 pkt_rate_high;
527 u16 rx_usecs_high;
528 u32 sample_interval;
529 u32 adaptive_rx_coal;
530 u32 msg_enable;
531 u32 loopback_ok;
532 u32 validate_loopback;
533
534 struct mlx4_hwq_resources res;
535 int link_state;
536 int last_link_state;
537 bool port_up;
538 int port;
539 int registered;
540 int allocated;
541 int stride;
542 unsigned char current_mac[ETH_ALEN + 2];
543 int mac_index;
544 unsigned max_mtu;
545 int base_qpn;
546 int cqe_factor;
547 int cqe_size;
548
549 struct mlx4_en_rss_map rss_map;
550 __be32 ctrl_flags;
551 u32 flags;
552 u8 num_tx_rings_p_up;
553 u32 tx_work_limit;
554 u32 tx_ring_num;
555 u32 rx_ring_num;
556 u32 rx_skb_size;
557 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
558 u16 num_frags;
559 u16 log_rx_info;
560
561 struct mlx4_en_tx_ring **tx_ring;
562 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
563 struct mlx4_en_cq **tx_cq;
564 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
565 struct mlx4_qp drop_qp;
566 struct work_struct rx_mode_task;
567 struct work_struct restart_task;
568 struct work_struct linkstate_task;
569 struct delayed_work stats_task;
570 struct delayed_work service_task;
571 #ifdef CONFIG_MLX4_EN_VXLAN
572 struct work_struct vxlan_add_task;
573 struct work_struct vxlan_del_task;
574 #endif
575 struct mlx4_en_perf_stats pstats;
576 struct mlx4_en_pkt_stats pkstats;
577 struct mlx4_en_counter_stats pf_stats;
578 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
579 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
580 struct mlx4_en_flow_stats_rx rx_flowstats;
581 struct mlx4_en_flow_stats_tx tx_flowstats;
582 struct mlx4_en_port_stats port_stats;
583 struct mlx4_en_stats_bitmap stats_bitmap;
584 struct list_head mc_list;
585 struct list_head curr_list;
586 u64 broadcast_id;
587 struct mlx4_en_stat_out_mbox hw_stats;
588 int vids[128];
589 bool wol;
590 struct device *ddev;
591 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
592 struct hwtstamp_config hwtstamp_config;
593 u32 counter_index;
594
595 #ifdef CONFIG_MLX4_EN_DCB
596 struct ieee_ets ets;
597 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
598 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
599 #endif
600 #ifdef CONFIG_RFS_ACCEL
601 spinlock_t filters_lock;
602 int last_filter_id;
603 struct list_head filters;
604 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
605 #endif
606 u64 tunnel_reg_id;
607 __be16 vxlan_port;
608
609 u32 pflags;
610 u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
611 u8 rss_hash_fn;
612 unsigned long state;
613 };
614
615 enum mlx4_en_wol {
616 MLX4_EN_WOL_MAGIC = (1ULL << 61),
617 MLX4_EN_WOL_ENABLED = (1ULL << 62),
618 };
619
620 struct mlx4_mac_entry {
621 struct hlist_node hlist;
622 unsigned char mac[ETH_ALEN + 2];
623 u64 reg_id;
624 struct rcu_head rcu;
625 };
626
mlx4_en_get_cqe(void * buf,int idx,int cqe_sz)627 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
628 {
629 return buf + idx * cqe_sz;
630 }
631
632 #ifdef CONFIG_NET_RX_BUSY_POLL
mlx4_en_cq_init_lock(struct mlx4_en_cq * cq)633 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
634 {
635 spin_lock_init(&cq->poll_lock);
636 cq->state = MLX4_EN_CQ_STATE_IDLE;
637 }
638
639 /* called from the device poll rutine to get ownership of a cq */
mlx4_en_cq_lock_napi(struct mlx4_en_cq * cq)640 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
641 {
642 int rc = true;
643 spin_lock(&cq->poll_lock);
644 if (cq->state & MLX4_CQ_LOCKED) {
645 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI);
646 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD;
647 rc = false;
648 } else
649 /* we don't care if someone yielded */
650 cq->state = MLX4_EN_CQ_STATE_NAPI;
651 spin_unlock(&cq->poll_lock);
652 return rc;
653 }
654
655 /* returns true is someone tried to get the cq while napi had it */
mlx4_en_cq_unlock_napi(struct mlx4_en_cq * cq)656 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
657 {
658 int rc = false;
659 spin_lock(&cq->poll_lock);
660 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL |
661 MLX4_EN_CQ_STATE_NAPI_YIELD));
662
663 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
664 rc = true;
665 cq->state = MLX4_EN_CQ_STATE_IDLE;
666 spin_unlock(&cq->poll_lock);
667 return rc;
668 }
669
670 /* called from mlx4_en_low_latency_poll() */
mlx4_en_cq_lock_poll(struct mlx4_en_cq * cq)671 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
672 {
673 int rc = true;
674 spin_lock_bh(&cq->poll_lock);
675 if ((cq->state & MLX4_CQ_LOCKED)) {
676 struct net_device *dev = cq->dev;
677 struct mlx4_en_priv *priv = netdev_priv(dev);
678 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
679
680 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD;
681 rc = false;
682 rx_ring->yields++;
683 } else
684 /* preserve yield marks */
685 cq->state |= MLX4_EN_CQ_STATE_POLL;
686 spin_unlock_bh(&cq->poll_lock);
687 return rc;
688 }
689
690 /* returns true if someone tried to get the cq while it was locked */
mlx4_en_cq_unlock_poll(struct mlx4_en_cq * cq)691 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
692 {
693 int rc = false;
694 spin_lock_bh(&cq->poll_lock);
695 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI));
696
697 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
698 rc = true;
699 cq->state = MLX4_EN_CQ_STATE_IDLE;
700 spin_unlock_bh(&cq->poll_lock);
701 return rc;
702 }
703
704 /* true if a socket is polling, even if it did not get the lock */
mlx4_en_cq_busy_polling(struct mlx4_en_cq * cq)705 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
706 {
707 WARN_ON(!(cq->state & MLX4_CQ_LOCKED));
708 return cq->state & CQ_USER_PEND;
709 }
710 #else
mlx4_en_cq_init_lock(struct mlx4_en_cq * cq)711 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
712 {
713 }
714
mlx4_en_cq_lock_napi(struct mlx4_en_cq * cq)715 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
716 {
717 return true;
718 }
719
mlx4_en_cq_unlock_napi(struct mlx4_en_cq * cq)720 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
721 {
722 return false;
723 }
724
mlx4_en_cq_lock_poll(struct mlx4_en_cq * cq)725 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
726 {
727 return false;
728 }
729
mlx4_en_cq_unlock_poll(struct mlx4_en_cq * cq)730 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
731 {
732 return false;
733 }
734
mlx4_en_cq_busy_polling(struct mlx4_en_cq * cq)735 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
736 {
737 return false;
738 }
739 #endif /* CONFIG_NET_RX_BUSY_POLL */
740
741 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
742
743 void mlx4_en_update_loopback_state(struct net_device *dev,
744 netdev_features_t features);
745
746 void mlx4_en_destroy_netdev(struct net_device *dev);
747 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
748 struct mlx4_en_port_profile *prof);
749
750 int mlx4_en_start_port(struct net_device *dev);
751 void mlx4_en_stop_port(struct net_device *dev, int detach);
752
753 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
754 struct mlx4_en_stats_bitmap *stats_bitmap,
755 u8 rx_ppp, u8 rx_pause,
756 u8 tx_ppp, u8 tx_pause);
757
758 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
759 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
760
761 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
762 int entries, int ring, enum cq_type mode, int node);
763 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
764 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
765 int cq_idx);
766 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
767 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
768 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
769
770 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
771 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
772 void *accel_priv, select_queue_fallback_t fallback);
773 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
774
775 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
776 struct mlx4_en_tx_ring **pring,
777 u32 size, u16 stride,
778 int node, int queue_index);
779 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
780 struct mlx4_en_tx_ring **pring);
781 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
782 struct mlx4_en_tx_ring *ring,
783 int cq, int user_prio);
784 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
785 struct mlx4_en_tx_ring *ring);
786 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
787 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
788 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
789 struct mlx4_en_rx_ring **pring,
790 u32 size, u16 stride, int node);
791 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
792 struct mlx4_en_rx_ring **pring,
793 u32 size, u16 stride);
794 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
795 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
796 struct mlx4_en_rx_ring *ring);
797 int mlx4_en_process_rx_cq(struct net_device *dev,
798 struct mlx4_en_cq *cq,
799 int budget);
800 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
801 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
802 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
803 int is_tx, int rss, int qpn, int cqn, int user_prio,
804 struct mlx4_qp_context *context);
805 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
806 int mlx4_en_map_buffer(struct mlx4_buf *buf);
807 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
808 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
809 int loopback);
810 void mlx4_en_calc_rx_buf(struct net_device *dev);
811 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
812 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
813 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
814 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
815 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
816 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
817
818 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
819 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
820
821 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
822 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
823
824 #ifdef CONFIG_MLX4_EN_DCB
825 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
826 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
827 #endif
828
829 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
830
831 #ifdef CONFIG_RFS_ACCEL
832 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
833 #endif
834
835 #define MLX4_EN_NUM_SELF_TEST 5
836 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
837 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
838
839 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \
840 ((dev->features & feature) ^ (new_features & feature))
841
842 int mlx4_en_moderation_update(struct mlx4_en_priv *priv);
843 int mlx4_en_reset_config(struct net_device *dev,
844 struct hwtstamp_config ts_config,
845 netdev_features_t new_features);
846 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
847 struct mlx4_en_stats_bitmap *stats_bitmap,
848 u8 rx_ppp, u8 rx_pause,
849 u8 tx_ppp, u8 tx_pause);
850 int mlx4_en_netdev_event(struct notifier_block *this,
851 unsigned long event, void *ptr);
852
853 /*
854 * Functions for time stamping
855 */
856 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
857 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
858 struct skb_shared_hwtstamps *hwts,
859 u64 timestamp);
860 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
861 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
862
863 /* Globals
864 */
865 extern const struct ethtool_ops mlx4_en_ethtool_ops;
866
867
868
869 /*
870 * printk / logging functions
871 */
872
873 __printf(3, 4)
874 void en_print(const char *level, const struct mlx4_en_priv *priv,
875 const char *format, ...);
876
877 #define en_dbg(mlevel, priv, format, ...) \
878 do { \
879 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \
880 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \
881 } while (0)
882 #define en_warn(priv, format, ...) \
883 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
884 #define en_err(priv, format, ...) \
885 en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
886 #define en_info(priv, format, ...) \
887 en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
888
889 #define mlx4_err(mdev, format, ...) \
890 pr_err(DRV_NAME " %s: " format, \
891 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
892 #define mlx4_info(mdev, format, ...) \
893 pr_info(DRV_NAME " %s: " format, \
894 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
895 #define mlx4_warn(mdev, format, ...) \
896 pr_warn(DRV_NAME " %s: " format, \
897 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
898
899 #endif
900