1 /* 2 * net/dsa/mv88e6xxx.h - Marvell 88e6xxx switch chip support 3 * Copyright (c) 2008 Marvell Semiconductor 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 */ 10 11 #ifndef __MV88E6XXX_H 12 #define __MV88E6XXX_H 13 14 #include <linux/if_vlan.h> 15 16 #ifndef UINT64_MAX 17 #define UINT64_MAX (u64)(~((u64)0)) 18 #endif 19 20 #define SMI_CMD 0x00 21 #define SMI_CMD_BUSY BIT(15) 22 #define SMI_CMD_CLAUSE_22 BIT(12) 23 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 24 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) 25 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) 26 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) 27 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) 28 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) 29 #define SMI_DATA 0x01 30 31 #define REG_PORT(p) (0x10 + (p)) 32 #define PORT_STATUS 0x00 33 #define PORT_STATUS_PAUSE_EN BIT(15) 34 #define PORT_STATUS_MY_PAUSE BIT(14) 35 #define PORT_STATUS_HD_FLOW BIT(13) 36 #define PORT_STATUS_PHY_DETECT BIT(12) 37 #define PORT_STATUS_LINK BIT(11) 38 #define PORT_STATUS_DUPLEX BIT(10) 39 #define PORT_STATUS_SPEED_MASK 0x0300 40 #define PORT_STATUS_SPEED_10 0x0000 41 #define PORT_STATUS_SPEED_100 0x0100 42 #define PORT_STATUS_SPEED_1000 0x0200 43 #define PORT_STATUS_EEE BIT(6) /* 6352 */ 44 #define PORT_STATUS_AM_DIS BIT(6) /* 6165 */ 45 #define PORT_STATUS_MGMII BIT(6) /* 6185 */ 46 #define PORT_STATUS_TX_PAUSED BIT(5) 47 #define PORT_STATUS_FLOW_CTRL BIT(4) 48 #define PORT_PCS_CTRL 0x01 49 #define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15) 50 #define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14) 51 #define PORT_PCS_CTRL_FC BIT(7) 52 #define PORT_PCS_CTRL_FORCE_FC BIT(6) 53 #define PORT_PCS_CTRL_LINK_UP BIT(5) 54 #define PORT_PCS_CTRL_FORCE_LINK BIT(4) 55 #define PORT_PCS_CTRL_DUPLEX_FULL BIT(3) 56 #define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2) 57 #define PORT_PCS_CTRL_10 0x00 58 #define PORT_PCS_CTRL_100 0x01 59 #define PORT_PCS_CTRL_1000 0x02 60 #define PORT_PCS_CTRL_UNFORCED 0x03 61 #define PORT_PAUSE_CTRL 0x02 62 #define PORT_SWITCH_ID 0x03 63 #define PORT_SWITCH_ID_PROD_NUM_MASK 0xfff0 64 #define PORT_SWITCH_ID_REV_MASK 0x000f 65 #define PORT_SWITCH_ID_6031 0x0310 66 #define PORT_SWITCH_ID_6035 0x0350 67 #define PORT_SWITCH_ID_6046 0x0480 68 #define PORT_SWITCH_ID_6061 0x0610 69 #define PORT_SWITCH_ID_6065 0x0650 70 #define PORT_SWITCH_ID_6085 0x04a0 71 #define PORT_SWITCH_ID_6092 0x0970 72 #define PORT_SWITCH_ID_6095 0x0950 73 #define PORT_SWITCH_ID_6096 0x0980 74 #define PORT_SWITCH_ID_6097 0x0990 75 #define PORT_SWITCH_ID_6108 0x1070 76 #define PORT_SWITCH_ID_6121 0x1040 77 #define PORT_SWITCH_ID_6122 0x1050 78 #define PORT_SWITCH_ID_6123 0x1210 79 #define PORT_SWITCH_ID_6123_A1 0x1212 80 #define PORT_SWITCH_ID_6123_A2 0x1213 81 #define PORT_SWITCH_ID_6131 0x1060 82 #define PORT_SWITCH_ID_6131_B2 0x1066 83 #define PORT_SWITCH_ID_6152 0x1a40 84 #define PORT_SWITCH_ID_6155 0x1a50 85 #define PORT_SWITCH_ID_6161 0x1610 86 #define PORT_SWITCH_ID_6161_A1 0x1612 87 #define PORT_SWITCH_ID_6161_A2 0x1613 88 #define PORT_SWITCH_ID_6165 0x1650 89 #define PORT_SWITCH_ID_6165_A1 0x1652 90 #define PORT_SWITCH_ID_6165_A2 0x1653 91 #define PORT_SWITCH_ID_6171 0x1710 92 #define PORT_SWITCH_ID_6172 0x1720 93 #define PORT_SWITCH_ID_6175 0x1750 94 #define PORT_SWITCH_ID_6176 0x1760 95 #define PORT_SWITCH_ID_6182 0x1a60 96 #define PORT_SWITCH_ID_6185 0x1a70 97 #define PORT_SWITCH_ID_6240 0x2400 98 #define PORT_SWITCH_ID_6320 0x1150 99 #define PORT_SWITCH_ID_6320_A1 0x1151 100 #define PORT_SWITCH_ID_6320_A2 0x1152 101 #define PORT_SWITCH_ID_6321 0x3100 102 #define PORT_SWITCH_ID_6321_A1 0x3101 103 #define PORT_SWITCH_ID_6321_A2 0x3102 104 #define PORT_SWITCH_ID_6350 0x3710 105 #define PORT_SWITCH_ID_6351 0x3750 106 #define PORT_SWITCH_ID_6352 0x3520 107 #define PORT_SWITCH_ID_6352_A0 0x3521 108 #define PORT_SWITCH_ID_6352_A1 0x3522 109 #define PORT_CONTROL 0x04 110 #define PORT_CONTROL_USE_CORE_TAG BIT(15) 111 #define PORT_CONTROL_DROP_ON_LOCK BIT(14) 112 #define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12) 113 #define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12) 114 #define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12) 115 #define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12) 116 #define PORT_CONTROL_HEADER BIT(11) 117 #define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10) 118 #define PORT_CONTROL_DOUBLE_TAG BIT(9) 119 #define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8) 120 #define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8) 121 #define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8) 122 #define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8) 123 #define PORT_CONTROL_DSA_TAG BIT(8) 124 #define PORT_CONTROL_VLAN_TUNNEL BIT(7) 125 #define PORT_CONTROL_TAG_IF_BOTH BIT(6) 126 #define PORT_CONTROL_USE_IP BIT(5) 127 #define PORT_CONTROL_USE_TAG BIT(4) 128 #define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3) 129 #define PORT_CONTROL_FORWARD_UNKNOWN BIT(2) 130 #define PORT_CONTROL_STATE_MASK 0x03 131 #define PORT_CONTROL_STATE_DISABLED 0x00 132 #define PORT_CONTROL_STATE_BLOCKING 0x01 133 #define PORT_CONTROL_STATE_LEARNING 0x02 134 #define PORT_CONTROL_STATE_FORWARDING 0x03 135 #define PORT_CONTROL_1 0x05 136 #define PORT_BASE_VLAN 0x06 137 #define PORT_DEFAULT_VLAN 0x07 138 #define PORT_DEFAULT_VLAN_MASK 0xfff 139 #define PORT_CONTROL_2 0x08 140 #define PORT_CONTROL_2_IGNORE_FCS BIT(15) 141 #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14) 142 #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13) 143 #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12) 144 #define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12) 145 #define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12) 146 #define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12) 147 #define PORT_CONTROL_2_8021Q_MASK (0x03 << 10) 148 #define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10) 149 #define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10) 150 #define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10) 151 #define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10) 152 #define PORT_CONTROL_2_DISCARD_TAGGED BIT(9) 153 #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8) 154 #define PORT_CONTROL_2_MAP_DA BIT(7) 155 #define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6) 156 #define PORT_CONTROL_2_FORWARD_UNKNOWN BIT(6) 157 #define PORT_CONTROL_2_EGRESS_MONITOR BIT(5) 158 #define PORT_CONTROL_2_INGRESS_MONITOR BIT(4) 159 #define PORT_RATE_CONTROL 0x09 160 #define PORT_RATE_CONTROL_2 0x0a 161 #define PORT_ASSOC_VECTOR 0x0b 162 #define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15) 163 #define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14) 164 #define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13) 165 #define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12) 166 #define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11) 167 #define PORT_ATU_CONTROL 0x0c 168 #define PORT_PRI_OVERRIDE 0x0d 169 #define PORT_ETH_TYPE 0x0f 170 #define PORT_IN_DISCARD_LO 0x10 171 #define PORT_IN_DISCARD_HI 0x11 172 #define PORT_IN_FILTERED 0x12 173 #define PORT_OUT_FILTERED 0x13 174 #define PORT_TAG_REGMAP_0123 0x18 175 #define PORT_TAG_REGMAP_4567 0x19 176 177 #define REG_GLOBAL 0x1b 178 #define GLOBAL_STATUS 0x00 179 #define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */ 180 /* Two bits for 6165, 6185 etc */ 181 #define GLOBAL_STATUS_PPU_MASK (0x3 << 14) 182 #define GLOBAL_STATUS_PPU_DISABLED_RST (0x0 << 14) 183 #define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14) 184 #define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14) 185 #define GLOBAL_STATUS_PPU_POLLING (0x3 << 14) 186 #define GLOBAL_MAC_01 0x01 187 #define GLOBAL_MAC_23 0x02 188 #define GLOBAL_MAC_45 0x03 189 #define GLOBAL_ATU_FID 0x01 /* 6097 6165 6351 6352 */ 190 #define GLOBAL_VTU_FID 0x02 /* 6097 6165 6351 6352 */ 191 #define GLOBAL_VTU_FID_MASK 0xfff 192 #define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */ 193 #define GLOBAL_VTU_SID_MASK 0x3f 194 #define GLOBAL_CONTROL 0x04 195 #define GLOBAL_CONTROL_SW_RESET BIT(15) 196 #define GLOBAL_CONTROL_PPU_ENABLE BIT(14) 197 #define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */ 198 #define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */ 199 #define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */ 200 #define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */ 201 #define GLOBAL_CONTROL_DEVICE_EN BIT(7) 202 #define GLOBAL_CONTROL_STATS_DONE_EN BIT(6) 203 #define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5) 204 #define GLOBAL_CONTROL_VTU_DONE_EN BIT(4) 205 #define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3) 206 #define GLOBAL_CONTROL_ATU_DONE_EN BIT(2) 207 #define GLOBAL_CONTROL_TCAM_EN BIT(1) 208 #define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0) 209 #define GLOBAL_VTU_OP 0x05 210 #define GLOBAL_VTU_OP_BUSY BIT(15) 211 #define GLOBAL_VTU_OP_FLUSH_ALL ((0x01 << 12) | GLOBAL_VTU_OP_BUSY) 212 #define GLOBAL_VTU_OP_VTU_LOAD_PURGE ((0x03 << 12) | GLOBAL_VTU_OP_BUSY) 213 #define GLOBAL_VTU_OP_VTU_GET_NEXT ((0x04 << 12) | GLOBAL_VTU_OP_BUSY) 214 #define GLOBAL_VTU_OP_STU_LOAD_PURGE ((0x05 << 12) | GLOBAL_VTU_OP_BUSY) 215 #define GLOBAL_VTU_OP_STU_GET_NEXT ((0x06 << 12) | GLOBAL_VTU_OP_BUSY) 216 #define GLOBAL_VTU_VID 0x06 217 #define GLOBAL_VTU_VID_MASK 0xfff 218 #define GLOBAL_VTU_VID_VALID BIT(12) 219 #define GLOBAL_VTU_DATA_0_3 0x07 220 #define GLOBAL_VTU_DATA_4_7 0x08 221 #define GLOBAL_VTU_DATA_8_11 0x09 222 #define GLOBAL_VTU_STU_DATA_MASK 0x03 223 #define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x00 224 #define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED 0x01 225 #define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED 0x02 226 #define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x03 227 #define GLOBAL_STU_DATA_PORT_STATE_DISABLED 0x00 228 #define GLOBAL_STU_DATA_PORT_STATE_BLOCKING 0x01 229 #define GLOBAL_STU_DATA_PORT_STATE_LEARNING 0x02 230 #define GLOBAL_STU_DATA_PORT_STATE_FORWARDING 0x03 231 #define GLOBAL_ATU_CONTROL 0x0a 232 #define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3) 233 #define GLOBAL_ATU_OP 0x0b 234 #define GLOBAL_ATU_OP_BUSY BIT(15) 235 #define GLOBAL_ATU_OP_NOP (0 << 12) 236 #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY) 237 #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY) 238 #define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY) 239 #define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY) 240 #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY) 241 #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY) 242 #define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY) 243 #define GLOBAL_ATU_DATA 0x0c 244 #define GLOBAL_ATU_DATA_TRUNK BIT(15) 245 #define GLOBAL_ATU_DATA_TRUNK_ID_MASK 0x00f0 246 #define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT 4 247 #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0 248 #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4 249 #define GLOBAL_ATU_DATA_STATE_MASK 0x0f 250 #define GLOBAL_ATU_DATA_STATE_UNUSED 0x00 251 #define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d 252 #define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e 253 #define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f 254 #define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05 255 #define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07 256 #define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e 257 #define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f 258 #define GLOBAL_ATU_MAC_01 0x0d 259 #define GLOBAL_ATU_MAC_23 0x0e 260 #define GLOBAL_ATU_MAC_45 0x0f 261 #define GLOBAL_IP_PRI_0 0x10 262 #define GLOBAL_IP_PRI_1 0x11 263 #define GLOBAL_IP_PRI_2 0x12 264 #define GLOBAL_IP_PRI_3 0x13 265 #define GLOBAL_IP_PRI_4 0x14 266 #define GLOBAL_IP_PRI_5 0x15 267 #define GLOBAL_IP_PRI_6 0x16 268 #define GLOBAL_IP_PRI_7 0x17 269 #define GLOBAL_IEEE_PRI 0x18 270 #define GLOBAL_CORE_TAG_TYPE 0x19 271 #define GLOBAL_MONITOR_CONTROL 0x1a 272 #define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12 273 #define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8 274 #define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4 275 #define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0 276 #define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0) 277 #define GLOBAL_CONTROL_2 0x1c 278 #define GLOBAL_CONTROL_2_NO_CASCADE 0xe000 279 #define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000 280 281 #define GLOBAL_STATS_OP 0x1d 282 #define GLOBAL_STATS_OP_BUSY BIT(15) 283 #define GLOBAL_STATS_OP_NOP (0 << 12) 284 #define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY) 285 #define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY) 286 #define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY) 287 #define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY) 288 #define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY) 289 #define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY) 290 #define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY) 291 #define GLOBAL_STATS_COUNTER_32 0x1e 292 #define GLOBAL_STATS_COUNTER_01 0x1f 293 294 #define REG_GLOBAL2 0x1c 295 #define GLOBAL2_INT_SOURCE 0x00 296 #define GLOBAL2_INT_MASK 0x01 297 #define GLOBAL2_MGMT_EN_2X 0x02 298 #define GLOBAL2_MGMT_EN_0X 0x03 299 #define GLOBAL2_FLOW_CONTROL 0x04 300 #define GLOBAL2_SWITCH_MGMT 0x05 301 #define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15) 302 #define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14) 303 #define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13) 304 #define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7) 305 #define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3) 306 #define GLOBAL2_DEVICE_MAPPING 0x06 307 #define GLOBAL2_DEVICE_MAPPING_UPDATE BIT(15) 308 #define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT 8 309 #define GLOBAL2_DEVICE_MAPPING_PORT_MASK 0x0f 310 #define GLOBAL2_TRUNK_MASK 0x07 311 #define GLOBAL2_TRUNK_MASK_UPDATE BIT(15) 312 #define GLOBAL2_TRUNK_MASK_NUM_SHIFT 12 313 #define GLOBAL2_TRUNK_MAPPING 0x08 314 #define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15) 315 #define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11 316 #define GLOBAL2_INGRESS_OP 0x09 317 #define GLOBAL2_INGRESS_DATA 0x0a 318 #define GLOBAL2_PVT_ADDR 0x0b 319 #define GLOBAL2_PVT_DATA 0x0c 320 #define GLOBAL2_SWITCH_MAC 0x0d 321 #define GLOBAL2_SWITCH_MAC_BUSY BIT(15) 322 #define GLOBAL2_ATU_STATS 0x0e 323 #define GLOBAL2_PRIO_OVERRIDE 0x0f 324 #define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7) 325 #define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4 326 #define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3) 327 #define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0 328 #define GLOBAL2_EEPROM_OP 0x14 329 #define GLOBAL2_EEPROM_OP_BUSY BIT(15) 330 #define GLOBAL2_EEPROM_OP_WRITE ((3 << 12) | GLOBAL2_EEPROM_OP_BUSY) 331 #define GLOBAL2_EEPROM_OP_READ ((4 << 12) | GLOBAL2_EEPROM_OP_BUSY) 332 #define GLOBAL2_EEPROM_OP_LOAD BIT(11) 333 #define GLOBAL2_EEPROM_OP_WRITE_EN BIT(10) 334 #define GLOBAL2_EEPROM_OP_ADDR_MASK 0xff 335 #define GLOBAL2_EEPROM_DATA 0x15 336 #define GLOBAL2_PTP_AVB_OP 0x16 337 #define GLOBAL2_PTP_AVB_DATA 0x17 338 #define GLOBAL2_SMI_OP 0x18 339 #define GLOBAL2_SMI_OP_BUSY BIT(15) 340 #define GLOBAL2_SMI_OP_CLAUSE_22 BIT(12) 341 #define GLOBAL2_SMI_OP_22_WRITE ((1 << 10) | GLOBAL2_SMI_OP_BUSY | \ 342 GLOBAL2_SMI_OP_CLAUSE_22) 343 #define GLOBAL2_SMI_OP_22_READ ((2 << 10) | GLOBAL2_SMI_OP_BUSY | \ 344 GLOBAL2_SMI_OP_CLAUSE_22) 345 #define GLOBAL2_SMI_OP_45_WRITE_ADDR ((0 << 10) | GLOBAL2_SMI_OP_BUSY) 346 #define GLOBAL2_SMI_OP_45_WRITE_DATA ((1 << 10) | GLOBAL2_SMI_OP_BUSY) 347 #define GLOBAL2_SMI_OP_45_READ_DATA ((2 << 10) | GLOBAL2_SMI_OP_BUSY) 348 #define GLOBAL2_SMI_DATA 0x19 349 #define GLOBAL2_SCRATCH_MISC 0x1a 350 #define GLOBAL2_SCRATCH_BUSY BIT(15) 351 #define GLOBAL2_SCRATCH_REGISTER_SHIFT 8 352 #define GLOBAL2_SCRATCH_VALUE_MASK 0xff 353 #define GLOBAL2_WDOG_CONTROL 0x1b 354 #define GLOBAL2_QOS_WEIGHT 0x1c 355 #define GLOBAL2_MISC 0x1d 356 357 struct mv88e6xxx_switch_id { 358 u16 id; 359 char *name; 360 }; 361 362 struct mv88e6xxx_atu_entry { 363 u16 fid; 364 u8 state; 365 bool trunk; 366 u16 portv_trunkid; 367 u8 mac[ETH_ALEN]; 368 }; 369 370 struct mv88e6xxx_vtu_stu_entry { 371 /* VTU only */ 372 u16 vid; 373 u16 fid; 374 375 /* VTU and STU */ 376 u8 sid; 377 bool valid; 378 u8 data[DSA_MAX_PORTS]; 379 }; 380 381 struct mv88e6xxx_priv_state { 382 /* When using multi-chip addressing, this mutex protects 383 * access to the indirect access registers. (In single-chip 384 * mode, this mutex is effectively useless.) 385 */ 386 struct mutex smi_mutex; 387 388 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU 389 /* Handles automatic disabling and re-enabling of the PHY 390 * polling unit. 391 */ 392 struct mutex ppu_mutex; 393 int ppu_disabled; 394 struct work_struct ppu_work; 395 struct timer_list ppu_timer; 396 #endif 397 398 /* This mutex serialises access to the statistics unit. 399 * Hold this mutex over snapshot + dump sequences. 400 */ 401 struct mutex stats_mutex; 402 403 /* This mutex serializes phy access for chips with 404 * indirect phy addressing. It is unused for chips 405 * with direct phy access. 406 */ 407 struct mutex phy_mutex; 408 409 /* This mutex serializes eeprom access for chips with 410 * eeprom support. 411 */ 412 struct mutex eeprom_mutex; 413 414 int id; /* switch product id */ 415 int num_ports; /* number of switch ports */ 416 417 unsigned long port_state_update_mask; 418 u8 port_state[DSA_MAX_PORTS]; 419 420 struct work_struct bridge_work; 421 }; 422 423 struct mv88e6xxx_hw_stat { 424 char string[ETH_GSTRING_LEN]; 425 int sizeof_stat; 426 int reg; 427 }; 428 429 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active); 430 char *mv88e6xxx_lookup_name(struct device *host_dev, int sw_addr, 431 const struct mv88e6xxx_switch_id *table, 432 unsigned int num); 433 int mv88e6xxx_setup_ports(struct dsa_switch *ds); 434 int mv88e6xxx_setup_common(struct dsa_switch *ds); 435 int mv88e6xxx_setup_global(struct dsa_switch *ds); 436 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg); 437 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val); 438 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr); 439 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr); 440 int mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum); 441 int mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val); 442 int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum); 443 int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum, 444 u16 val); 445 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds); 446 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum); 447 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr, 448 int regnum, u16 val); 449 void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data); 450 void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 451 uint64_t *data); 452 int mv88e6xxx_get_sset_count(struct dsa_switch *ds); 453 int mv88e6xxx_get_sset_count_basic(struct dsa_switch *ds); 454 void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 455 struct phy_device *phydev); 456 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port); 457 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 458 struct ethtool_regs *regs, void *_p); 459 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp); 460 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp); 461 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp); 462 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm); 463 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds); 464 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds); 465 int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum); 466 int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum, 467 u16 val); 468 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e); 469 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, 470 struct phy_device *phydev, struct ethtool_eee *e); 471 int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, u32 members); 472 int mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, u32 members); 473 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state); 474 int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 475 const struct switchdev_obj_port_vlan *vlan, 476 struct switchdev_trans *trans); 477 int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 478 const struct switchdev_obj_port_vlan *vlan, 479 struct switchdev_trans *trans); 480 int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 481 const struct switchdev_obj_port_vlan *vlan); 482 int mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *vid); 483 int mv88e6xxx_vlan_getnext(struct dsa_switch *ds, u16 *vid, 484 unsigned long *ports, unsigned long *untagged); 485 int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, 486 const struct switchdev_obj_port_fdb *fdb, 487 struct switchdev_trans *trans); 488 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 489 const struct switchdev_obj_port_fdb *fdb, 490 struct switchdev_trans *trans); 491 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 492 const struct switchdev_obj_port_fdb *fdb); 493 int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 494 struct switchdev_obj_port_fdb *fdb, 495 int (*cb)(struct switchdev_obj *obj)); 496 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg); 497 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page, 498 int reg, int val); 499 500 extern struct dsa_switch_driver mv88e6131_switch_driver; 501 extern struct dsa_switch_driver mv88e6123_61_65_switch_driver; 502 extern struct dsa_switch_driver mv88e6352_switch_driver; 503 extern struct dsa_switch_driver mv88e6171_switch_driver; 504 505 #define REG_READ(addr, reg) \ 506 ({ \ 507 int __ret; \ 508 \ 509 __ret = mv88e6xxx_reg_read(ds, addr, reg); \ 510 if (__ret < 0) \ 511 return __ret; \ 512 __ret; \ 513 }) 514 515 #define REG_WRITE(addr, reg, val) \ 516 ({ \ 517 int __ret; \ 518 \ 519 __ret = mv88e6xxx_reg_write(ds, addr, reg, val); \ 520 if (__ret < 0) \ 521 return __ret; \ 522 }) 523 524 525 526 #endif 527