1/* 2 * Device Tree Source for OMAP5 clock data 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10&cm_core_aon_clocks { 11 pad_clks_src_ck: pad_clks_src_ck { 12 #clock-cells = <0>; 13 compatible = "fixed-clock"; 14 clock-frequency = <12000000>; 15 }; 16 17 pad_clks_ck: pad_clks_ck { 18 #clock-cells = <0>; 19 compatible = "ti,gate-clock"; 20 clocks = <&pad_clks_src_ck>; 21 ti,bit-shift = <8>; 22 reg = <0x0108>; 23 }; 24 25 secure_32k_clk_src_ck: secure_32k_clk_src_ck { 26 #clock-cells = <0>; 27 compatible = "fixed-clock"; 28 clock-frequency = <32768>; 29 }; 30 31 slimbus_src_clk: slimbus_src_clk { 32 #clock-cells = <0>; 33 compatible = "fixed-clock"; 34 clock-frequency = <12000000>; 35 }; 36 37 slimbus_clk: slimbus_clk { 38 #clock-cells = <0>; 39 compatible = "ti,gate-clock"; 40 clocks = <&slimbus_src_clk>; 41 ti,bit-shift = <10>; 42 reg = <0x0108>; 43 }; 44 45 sys_32k_ck: sys_32k_ck { 46 #clock-cells = <0>; 47 compatible = "fixed-clock"; 48 clock-frequency = <32768>; 49 }; 50 51 virt_12000000_ck: virt_12000000_ck { 52 #clock-cells = <0>; 53 compatible = "fixed-clock"; 54 clock-frequency = <12000000>; 55 }; 56 57 virt_13000000_ck: virt_13000000_ck { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <13000000>; 61 }; 62 63 virt_16800000_ck: virt_16800000_ck { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <16800000>; 67 }; 68 69 virt_19200000_ck: virt_19200000_ck { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <19200000>; 73 }; 74 75 virt_26000000_ck: virt_26000000_ck { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <26000000>; 79 }; 80 81 virt_27000000_ck: virt_27000000_ck { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <27000000>; 85 }; 86 87 virt_38400000_ck: virt_38400000_ck { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <38400000>; 91 }; 92 93 xclk60mhsp1_ck: xclk60mhsp1_ck { 94 #clock-cells = <0>; 95 compatible = "fixed-clock"; 96 clock-frequency = <60000000>; 97 }; 98 99 xclk60mhsp2_ck: xclk60mhsp2_ck { 100 #clock-cells = <0>; 101 compatible = "fixed-clock"; 102 clock-frequency = <60000000>; 103 }; 104 105 dpll_abe_ck: dpll_abe_ck { 106 #clock-cells = <0>; 107 compatible = "ti,omap4-dpll-m4xen-clock"; 108 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; 109 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; 110 }; 111 112 dpll_abe_x2_ck: dpll_abe_x2_ck { 113 #clock-cells = <0>; 114 compatible = "ti,omap4-dpll-x2-clock"; 115 clocks = <&dpll_abe_ck>; 116 }; 117 118 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck { 119 #clock-cells = <0>; 120 compatible = "ti,divider-clock"; 121 clocks = <&dpll_abe_x2_ck>; 122 ti,max-div = <31>; 123 reg = <0x01f0>; 124 ti,index-starts-at-one; 125 }; 126 127 abe_24m_fclk: abe_24m_fclk { 128 #clock-cells = <0>; 129 compatible = "fixed-factor-clock"; 130 clocks = <&dpll_abe_m2x2_ck>; 131 clock-mult = <1>; 132 clock-div = <8>; 133 }; 134 135 abe_clk: abe_clk { 136 #clock-cells = <0>; 137 compatible = "ti,divider-clock"; 138 clocks = <&dpll_abe_m2x2_ck>; 139 ti,max-div = <4>; 140 reg = <0x0108>; 141 ti,index-power-of-two; 142 }; 143 144 abe_iclk: abe_iclk { 145 #clock-cells = <0>; 146 compatible = "ti,divider-clock"; 147 clocks = <&aess_fclk>; 148 ti,bit-shift = <24>; 149 reg = <0x0528>; 150 ti,dividers = <2>, <1>; 151 }; 152 153 abe_lp_clk_div: abe_lp_clk_div { 154 #clock-cells = <0>; 155 compatible = "fixed-factor-clock"; 156 clocks = <&dpll_abe_m2x2_ck>; 157 clock-mult = <1>; 158 clock-div = <16>; 159 }; 160 161 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck { 162 #clock-cells = <0>; 163 compatible = "ti,divider-clock"; 164 clocks = <&dpll_abe_x2_ck>; 165 ti,max-div = <31>; 166 reg = <0x01f4>; 167 ti,index-starts-at-one; 168 }; 169 170 dpll_core_byp_mux: dpll_core_byp_mux { 171 #clock-cells = <0>; 172 compatible = "ti,mux-clock"; 173 clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; 174 ti,bit-shift = <23>; 175 reg = <0x012c>; 176 }; 177 178 dpll_core_ck: dpll_core_ck { 179 #clock-cells = <0>; 180 compatible = "ti,omap4-dpll-core-clock"; 181 clocks = <&sys_clkin>, <&dpll_core_byp_mux>; 182 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; 183 }; 184 185 dpll_core_x2_ck: dpll_core_x2_ck { 186 #clock-cells = <0>; 187 compatible = "ti,omap4-dpll-x2-clock"; 188 clocks = <&dpll_core_ck>; 189 }; 190 191 dpll_core_h21x2_ck: dpll_core_h21x2_ck { 192 #clock-cells = <0>; 193 compatible = "ti,divider-clock"; 194 clocks = <&dpll_core_x2_ck>; 195 ti,max-div = <63>; 196 reg = <0x0150>; 197 ti,index-starts-at-one; 198 }; 199 200 c2c_fclk: c2c_fclk { 201 #clock-cells = <0>; 202 compatible = "fixed-factor-clock"; 203 clocks = <&dpll_core_h21x2_ck>; 204 clock-mult = <1>; 205 clock-div = <1>; 206 }; 207 208 c2c_iclk: c2c_iclk { 209 #clock-cells = <0>; 210 compatible = "fixed-factor-clock"; 211 clocks = <&c2c_fclk>; 212 clock-mult = <1>; 213 clock-div = <2>; 214 }; 215 216 dpll_core_h11x2_ck: dpll_core_h11x2_ck { 217 #clock-cells = <0>; 218 compatible = "ti,divider-clock"; 219 clocks = <&dpll_core_x2_ck>; 220 ti,max-div = <63>; 221 reg = <0x0138>; 222 ti,index-starts-at-one; 223 }; 224 225 dpll_core_h12x2_ck: dpll_core_h12x2_ck { 226 #clock-cells = <0>; 227 compatible = "ti,divider-clock"; 228 clocks = <&dpll_core_x2_ck>; 229 ti,max-div = <63>; 230 reg = <0x013c>; 231 ti,index-starts-at-one; 232 }; 233 234 dpll_core_h13x2_ck: dpll_core_h13x2_ck { 235 #clock-cells = <0>; 236 compatible = "ti,divider-clock"; 237 clocks = <&dpll_core_x2_ck>; 238 ti,max-div = <63>; 239 reg = <0x0140>; 240 ti,index-starts-at-one; 241 }; 242 243 dpll_core_h14x2_ck: dpll_core_h14x2_ck { 244 #clock-cells = <0>; 245 compatible = "ti,divider-clock"; 246 clocks = <&dpll_core_x2_ck>; 247 ti,max-div = <63>; 248 reg = <0x0144>; 249 ti,index-starts-at-one; 250 }; 251 252 dpll_core_h22x2_ck: dpll_core_h22x2_ck { 253 #clock-cells = <0>; 254 compatible = "ti,divider-clock"; 255 clocks = <&dpll_core_x2_ck>; 256 ti,max-div = <63>; 257 reg = <0x0154>; 258 ti,index-starts-at-one; 259 }; 260 261 dpll_core_h23x2_ck: dpll_core_h23x2_ck { 262 #clock-cells = <0>; 263 compatible = "ti,divider-clock"; 264 clocks = <&dpll_core_x2_ck>; 265 ti,max-div = <63>; 266 reg = <0x0158>; 267 ti,index-starts-at-one; 268 }; 269 270 dpll_core_h24x2_ck: dpll_core_h24x2_ck { 271 #clock-cells = <0>; 272 compatible = "ti,divider-clock"; 273 clocks = <&dpll_core_x2_ck>; 274 ti,max-div = <63>; 275 reg = <0x015c>; 276 ti,index-starts-at-one; 277 }; 278 279 dpll_core_m2_ck: dpll_core_m2_ck { 280 #clock-cells = <0>; 281 compatible = "ti,divider-clock"; 282 clocks = <&dpll_core_ck>; 283 ti,max-div = <31>; 284 reg = <0x0130>; 285 ti,index-starts-at-one; 286 }; 287 288 dpll_core_m3x2_ck: dpll_core_m3x2_ck { 289 #clock-cells = <0>; 290 compatible = "ti,divider-clock"; 291 clocks = <&dpll_core_x2_ck>; 292 ti,max-div = <31>; 293 reg = <0x0134>; 294 ti,index-starts-at-one; 295 }; 296 297 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { 298 #clock-cells = <0>; 299 compatible = "fixed-factor-clock"; 300 clocks = <&dpll_core_h12x2_ck>; 301 clock-mult = <1>; 302 clock-div = <1>; 303 }; 304 305 dpll_iva_byp_mux: dpll_iva_byp_mux { 306 #clock-cells = <0>; 307 compatible = "ti,mux-clock"; 308 clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; 309 ti,bit-shift = <23>; 310 reg = <0x01ac>; 311 }; 312 313 dpll_iva_ck: dpll_iva_ck { 314 #clock-cells = <0>; 315 compatible = "ti,omap4-dpll-clock"; 316 clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; 317 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; 318 }; 319 320 dpll_iva_x2_ck: dpll_iva_x2_ck { 321 #clock-cells = <0>; 322 compatible = "ti,omap4-dpll-x2-clock"; 323 clocks = <&dpll_iva_ck>; 324 }; 325 326 dpll_iva_h11x2_ck: dpll_iva_h11x2_ck { 327 #clock-cells = <0>; 328 compatible = "ti,divider-clock"; 329 clocks = <&dpll_iva_x2_ck>; 330 ti,max-div = <63>; 331 reg = <0x01b8>; 332 ti,index-starts-at-one; 333 }; 334 335 dpll_iva_h12x2_ck: dpll_iva_h12x2_ck { 336 #clock-cells = <0>; 337 compatible = "ti,divider-clock"; 338 clocks = <&dpll_iva_x2_ck>; 339 ti,max-div = <63>; 340 reg = <0x01bc>; 341 ti,index-starts-at-one; 342 }; 343 344 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { 345 #clock-cells = <0>; 346 compatible = "fixed-factor-clock"; 347 clocks = <&dpll_core_h12x2_ck>; 348 clock-mult = <1>; 349 clock-div = <1>; 350 }; 351 352 dpll_mpu_ck: dpll_mpu_ck { 353 #clock-cells = <0>; 354 compatible = "ti,omap5-mpu-dpll-clock"; 355 clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; 356 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; 357 }; 358 359 dpll_mpu_m2_ck: dpll_mpu_m2_ck { 360 #clock-cells = <0>; 361 compatible = "ti,divider-clock"; 362 clocks = <&dpll_mpu_ck>; 363 ti,max-div = <31>; 364 reg = <0x0170>; 365 ti,index-starts-at-one; 366 }; 367 368 per_dpll_hs_clk_div: per_dpll_hs_clk_div { 369 #clock-cells = <0>; 370 compatible = "fixed-factor-clock"; 371 clocks = <&dpll_abe_m3x2_ck>; 372 clock-mult = <1>; 373 clock-div = <2>; 374 }; 375 376 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { 377 #clock-cells = <0>; 378 compatible = "fixed-factor-clock"; 379 clocks = <&dpll_abe_m3x2_ck>; 380 clock-mult = <1>; 381 clock-div = <3>; 382 }; 383 384 l3_iclk_div: l3_iclk_div { 385 #clock-cells = <0>; 386 compatible = "ti,divider-clock"; 387 ti,max-div = <2>; 388 ti,bit-shift = <4>; 389 reg = <0x100>; 390 clocks = <&dpll_core_h12x2_ck>; 391 ti,index-power-of-two; 392 }; 393 394 gpu_l3_iclk: gpu_l3_iclk { 395 #clock-cells = <0>; 396 compatible = "fixed-factor-clock"; 397 clocks = <&l3_iclk_div>; 398 clock-mult = <1>; 399 clock-div = <1>; 400 }; 401 402 l4_root_clk_div: l4_root_clk_div { 403 #clock-cells = <0>; 404 compatible = "ti,divider-clock"; 405 ti,max-div = <2>; 406 ti,bit-shift = <8>; 407 reg = <0x100>; 408 clocks = <&l3_iclk_div>; 409 ti,index-power-of-two; 410 }; 411 412 slimbus1_slimbus_clk: slimbus1_slimbus_clk { 413 #clock-cells = <0>; 414 compatible = "ti,gate-clock"; 415 clocks = <&slimbus_clk>; 416 ti,bit-shift = <11>; 417 reg = <0x0560>; 418 }; 419 420 aess_fclk: aess_fclk { 421 #clock-cells = <0>; 422 compatible = "ti,divider-clock"; 423 clocks = <&abe_clk>; 424 ti,bit-shift = <24>; 425 ti,max-div = <2>; 426 reg = <0x0528>; 427 }; 428 429 dmic_sync_mux_ck: dmic_sync_mux_ck { 430 #clock-cells = <0>; 431 compatible = "ti,mux-clock"; 432 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; 433 ti,bit-shift = <26>; 434 reg = <0x0538>; 435 }; 436 437 dmic_gfclk: dmic_gfclk { 438 #clock-cells = <0>; 439 compatible = "ti,mux-clock"; 440 clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; 441 ti,bit-shift = <24>; 442 reg = <0x0538>; 443 }; 444 445 mcasp_sync_mux_ck: mcasp_sync_mux_ck { 446 #clock-cells = <0>; 447 compatible = "ti,mux-clock"; 448 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; 449 ti,bit-shift = <26>; 450 reg = <0x0540>; 451 }; 452 453 mcasp_gfclk: mcasp_gfclk { 454 #clock-cells = <0>; 455 compatible = "ti,mux-clock"; 456 clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; 457 ti,bit-shift = <24>; 458 reg = <0x0540>; 459 }; 460 461 mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck { 462 #clock-cells = <0>; 463 compatible = "ti,mux-clock"; 464 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; 465 ti,bit-shift = <26>; 466 reg = <0x0548>; 467 }; 468 469 mcbsp1_gfclk: mcbsp1_gfclk { 470 #clock-cells = <0>; 471 compatible = "ti,mux-clock"; 472 clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; 473 ti,bit-shift = <24>; 474 reg = <0x0548>; 475 }; 476 477 mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck { 478 #clock-cells = <0>; 479 compatible = "ti,mux-clock"; 480 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; 481 ti,bit-shift = <26>; 482 reg = <0x0550>; 483 }; 484 485 mcbsp2_gfclk: mcbsp2_gfclk { 486 #clock-cells = <0>; 487 compatible = "ti,mux-clock"; 488 clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; 489 ti,bit-shift = <24>; 490 reg = <0x0550>; 491 }; 492 493 mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck { 494 #clock-cells = <0>; 495 compatible = "ti,mux-clock"; 496 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; 497 ti,bit-shift = <26>; 498 reg = <0x0558>; 499 }; 500 501 mcbsp3_gfclk: mcbsp3_gfclk { 502 #clock-cells = <0>; 503 compatible = "ti,mux-clock"; 504 clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; 505 ti,bit-shift = <24>; 506 reg = <0x0558>; 507 }; 508 509 timer5_gfclk_mux: timer5_gfclk_mux { 510 #clock-cells = <0>; 511 compatible = "ti,mux-clock"; 512 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; 513 ti,bit-shift = <24>; 514 reg = <0x0568>; 515 }; 516 517 timer6_gfclk_mux: timer6_gfclk_mux { 518 #clock-cells = <0>; 519 compatible = "ti,mux-clock"; 520 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; 521 ti,bit-shift = <24>; 522 reg = <0x0570>; 523 }; 524 525 timer7_gfclk_mux: timer7_gfclk_mux { 526 #clock-cells = <0>; 527 compatible = "ti,mux-clock"; 528 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; 529 ti,bit-shift = <24>; 530 reg = <0x0578>; 531 }; 532 533 timer8_gfclk_mux: timer8_gfclk_mux { 534 #clock-cells = <0>; 535 compatible = "ti,mux-clock"; 536 clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; 537 ti,bit-shift = <24>; 538 reg = <0x0580>; 539 }; 540 541 dummy_ck: dummy_ck { 542 #clock-cells = <0>; 543 compatible = "fixed-clock"; 544 clock-frequency = <0>; 545 }; 546}; 547&prm_clocks { 548 sys_clkin: sys_clkin { 549 #clock-cells = <0>; 550 compatible = "ti,mux-clock"; 551 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; 552 reg = <0x0110>; 553 ti,index-starts-at-one; 554 }; 555 556 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux { 557 #clock-cells = <0>; 558 compatible = "ti,mux-clock"; 559 clocks = <&sys_clkin>, <&sys_32k_ck>; 560 reg = <0x0108>; 561 }; 562 563 abe_dpll_clk_mux: abe_dpll_clk_mux { 564 #clock-cells = <0>; 565 compatible = "ti,mux-clock"; 566 clocks = <&sys_clkin>, <&sys_32k_ck>; 567 reg = <0x010c>; 568 }; 569 570 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { 571 #clock-cells = <0>; 572 compatible = "fixed-factor-clock"; 573 clocks = <&sys_clkin>; 574 clock-mult = <1>; 575 clock-div = <2>; 576 }; 577 578 dss_syc_gfclk_div: dss_syc_gfclk_div { 579 #clock-cells = <0>; 580 compatible = "fixed-factor-clock"; 581 clocks = <&sys_clkin>; 582 clock-mult = <1>; 583 clock-div = <1>; 584 }; 585 586 wkupaon_iclk_mux: wkupaon_iclk_mux { 587 #clock-cells = <0>; 588 compatible = "ti,mux-clock"; 589 clocks = <&sys_clkin>, <&abe_lp_clk_div>; 590 reg = <0x0108>; 591 }; 592 593 l3instr_ts_gclk_div: l3instr_ts_gclk_div { 594 #clock-cells = <0>; 595 compatible = "fixed-factor-clock"; 596 clocks = <&wkupaon_iclk_mux>; 597 clock-mult = <1>; 598 clock-div = <1>; 599 }; 600 601 gpio1_dbclk: gpio1_dbclk { 602 #clock-cells = <0>; 603 compatible = "ti,gate-clock"; 604 clocks = <&sys_32k_ck>; 605 ti,bit-shift = <8>; 606 reg = <0x1938>; 607 }; 608 609 timer1_gfclk_mux: timer1_gfclk_mux { 610 #clock-cells = <0>; 611 compatible = "ti,mux-clock"; 612 clocks = <&sys_clkin>, <&sys_32k_ck>; 613 ti,bit-shift = <24>; 614 reg = <0x1940>; 615 }; 616}; 617&cm_core_clocks { 618 619 dpll_per_byp_mux: dpll_per_byp_mux { 620 #clock-cells = <0>; 621 compatible = "ti,mux-clock"; 622 clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; 623 ti,bit-shift = <23>; 624 reg = <0x014c>; 625 }; 626 627 dpll_per_ck: dpll_per_ck { 628 #clock-cells = <0>; 629 compatible = "ti,omap4-dpll-clock"; 630 clocks = <&sys_clkin>, <&dpll_per_byp_mux>; 631 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; 632 }; 633 634 dpll_per_x2_ck: dpll_per_x2_ck { 635 #clock-cells = <0>; 636 compatible = "ti,omap4-dpll-x2-clock"; 637 clocks = <&dpll_per_ck>; 638 }; 639 640 dpll_per_h11x2_ck: dpll_per_h11x2_ck { 641 #clock-cells = <0>; 642 compatible = "ti,divider-clock"; 643 clocks = <&dpll_per_x2_ck>; 644 ti,max-div = <63>; 645 reg = <0x0158>; 646 ti,index-starts-at-one; 647 }; 648 649 dpll_per_h12x2_ck: dpll_per_h12x2_ck { 650 #clock-cells = <0>; 651 compatible = "ti,divider-clock"; 652 clocks = <&dpll_per_x2_ck>; 653 ti,max-div = <63>; 654 reg = <0x015c>; 655 ti,index-starts-at-one; 656 }; 657 658 dpll_per_h14x2_ck: dpll_per_h14x2_ck { 659 #clock-cells = <0>; 660 compatible = "ti,divider-clock"; 661 clocks = <&dpll_per_x2_ck>; 662 ti,max-div = <63>; 663 reg = <0x0164>; 664 ti,index-starts-at-one; 665 }; 666 667 dpll_per_m2_ck: dpll_per_m2_ck { 668 #clock-cells = <0>; 669 compatible = "ti,divider-clock"; 670 clocks = <&dpll_per_ck>; 671 ti,max-div = <31>; 672 reg = <0x0150>; 673 ti,index-starts-at-one; 674 }; 675 676 dpll_per_m2x2_ck: dpll_per_m2x2_ck { 677 #clock-cells = <0>; 678 compatible = "ti,divider-clock"; 679 clocks = <&dpll_per_x2_ck>; 680 ti,max-div = <31>; 681 reg = <0x0150>; 682 ti,index-starts-at-one; 683 }; 684 685 dpll_per_m3x2_ck: dpll_per_m3x2_ck { 686 #clock-cells = <0>; 687 compatible = "ti,divider-clock"; 688 clocks = <&dpll_per_x2_ck>; 689 ti,max-div = <31>; 690 reg = <0x0154>; 691 ti,index-starts-at-one; 692 }; 693 694 dpll_unipro1_ck: dpll_unipro1_ck { 695 #clock-cells = <0>; 696 compatible = "ti,omap4-dpll-clock"; 697 clocks = <&sys_clkin>, <&sys_clkin>; 698 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; 699 }; 700 701 dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { 702 #clock-cells = <0>; 703 compatible = "fixed-factor-clock"; 704 clocks = <&dpll_unipro1_ck>; 705 clock-mult = <1>; 706 clock-div = <1>; 707 }; 708 709 dpll_unipro1_m2_ck: dpll_unipro1_m2_ck { 710 #clock-cells = <0>; 711 compatible = "ti,divider-clock"; 712 clocks = <&dpll_unipro1_ck>; 713 ti,max-div = <127>; 714 reg = <0x0210>; 715 ti,index-starts-at-one; 716 }; 717 718 dpll_unipro2_ck: dpll_unipro2_ck { 719 #clock-cells = <0>; 720 compatible = "ti,omap4-dpll-clock"; 721 clocks = <&sys_clkin>, <&sys_clkin>; 722 reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; 723 }; 724 725 dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { 726 #clock-cells = <0>; 727 compatible = "fixed-factor-clock"; 728 clocks = <&dpll_unipro2_ck>; 729 clock-mult = <1>; 730 clock-div = <1>; 731 }; 732 733 dpll_unipro2_m2_ck: dpll_unipro2_m2_ck { 734 #clock-cells = <0>; 735 compatible = "ti,divider-clock"; 736 clocks = <&dpll_unipro2_ck>; 737 ti,max-div = <127>; 738 reg = <0x01d0>; 739 ti,index-starts-at-one; 740 }; 741 742 dpll_usb_byp_mux: dpll_usb_byp_mux { 743 #clock-cells = <0>; 744 compatible = "ti,mux-clock"; 745 clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; 746 ti,bit-shift = <23>; 747 reg = <0x018c>; 748 }; 749 750 dpll_usb_ck: dpll_usb_ck { 751 #clock-cells = <0>; 752 compatible = "ti,omap4-dpll-j-type-clock"; 753 clocks = <&sys_clkin>, <&dpll_usb_byp_mux>; 754 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; 755 }; 756 757 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { 758 #clock-cells = <0>; 759 compatible = "fixed-factor-clock"; 760 clocks = <&dpll_usb_ck>; 761 clock-mult = <1>; 762 clock-div = <1>; 763 }; 764 765 dpll_usb_m2_ck: dpll_usb_m2_ck { 766 #clock-cells = <0>; 767 compatible = "ti,divider-clock"; 768 clocks = <&dpll_usb_ck>; 769 ti,max-div = <127>; 770 reg = <0x0190>; 771 ti,index-starts-at-one; 772 }; 773 774 func_128m_clk: func_128m_clk { 775 #clock-cells = <0>; 776 compatible = "fixed-factor-clock"; 777 clocks = <&dpll_per_h11x2_ck>; 778 clock-mult = <1>; 779 clock-div = <2>; 780 }; 781 782 func_12m_fclk: func_12m_fclk { 783 #clock-cells = <0>; 784 compatible = "fixed-factor-clock"; 785 clocks = <&dpll_per_m2x2_ck>; 786 clock-mult = <1>; 787 clock-div = <16>; 788 }; 789 790 func_24m_clk: func_24m_clk { 791 #clock-cells = <0>; 792 compatible = "fixed-factor-clock"; 793 clocks = <&dpll_per_m2_ck>; 794 clock-mult = <1>; 795 clock-div = <4>; 796 }; 797 798 func_48m_fclk: func_48m_fclk { 799 #clock-cells = <0>; 800 compatible = "fixed-factor-clock"; 801 clocks = <&dpll_per_m2x2_ck>; 802 clock-mult = <1>; 803 clock-div = <4>; 804 }; 805 806 func_96m_fclk: func_96m_fclk { 807 #clock-cells = <0>; 808 compatible = "fixed-factor-clock"; 809 clocks = <&dpll_per_m2x2_ck>; 810 clock-mult = <1>; 811 clock-div = <2>; 812 }; 813 814 l3init_60m_fclk: l3init_60m_fclk { 815 #clock-cells = <0>; 816 compatible = "ti,divider-clock"; 817 clocks = <&dpll_usb_m2_ck>; 818 reg = <0x0104>; 819 ti,dividers = <1>, <8>; 820 }; 821 822 dss_32khz_clk: dss_32khz_clk { 823 #clock-cells = <0>; 824 compatible = "ti,gate-clock"; 825 clocks = <&sys_32k_ck>; 826 ti,bit-shift = <11>; 827 reg = <0x1420>; 828 }; 829 830 dss_48mhz_clk: dss_48mhz_clk { 831 #clock-cells = <0>; 832 compatible = "ti,gate-clock"; 833 clocks = <&func_48m_fclk>; 834 ti,bit-shift = <9>; 835 reg = <0x1420>; 836 }; 837 838 dss_dss_clk: dss_dss_clk { 839 #clock-cells = <0>; 840 compatible = "ti,gate-clock"; 841 clocks = <&dpll_per_h12x2_ck>; 842 ti,bit-shift = <8>; 843 reg = <0x1420>; 844 ti,set-rate-parent; 845 }; 846 847 dss_sys_clk: dss_sys_clk { 848 #clock-cells = <0>; 849 compatible = "ti,gate-clock"; 850 clocks = <&dss_syc_gfclk_div>; 851 ti,bit-shift = <10>; 852 reg = <0x1420>; 853 }; 854 855 gpio2_dbclk: gpio2_dbclk { 856 #clock-cells = <0>; 857 compatible = "ti,gate-clock"; 858 clocks = <&sys_32k_ck>; 859 ti,bit-shift = <8>; 860 reg = <0x1060>; 861 }; 862 863 gpio3_dbclk: gpio3_dbclk { 864 #clock-cells = <0>; 865 compatible = "ti,gate-clock"; 866 clocks = <&sys_32k_ck>; 867 ti,bit-shift = <8>; 868 reg = <0x1068>; 869 }; 870 871 gpio4_dbclk: gpio4_dbclk { 872 #clock-cells = <0>; 873 compatible = "ti,gate-clock"; 874 clocks = <&sys_32k_ck>; 875 ti,bit-shift = <8>; 876 reg = <0x1070>; 877 }; 878 879 gpio5_dbclk: gpio5_dbclk { 880 #clock-cells = <0>; 881 compatible = "ti,gate-clock"; 882 clocks = <&sys_32k_ck>; 883 ti,bit-shift = <8>; 884 reg = <0x1078>; 885 }; 886 887 gpio6_dbclk: gpio6_dbclk { 888 #clock-cells = <0>; 889 compatible = "ti,gate-clock"; 890 clocks = <&sys_32k_ck>; 891 ti,bit-shift = <8>; 892 reg = <0x1080>; 893 }; 894 895 gpio7_dbclk: gpio7_dbclk { 896 #clock-cells = <0>; 897 compatible = "ti,gate-clock"; 898 clocks = <&sys_32k_ck>; 899 ti,bit-shift = <8>; 900 reg = <0x1110>; 901 }; 902 903 gpio8_dbclk: gpio8_dbclk { 904 #clock-cells = <0>; 905 compatible = "ti,gate-clock"; 906 clocks = <&sys_32k_ck>; 907 ti,bit-shift = <8>; 908 reg = <0x1118>; 909 }; 910 911 iss_ctrlclk: iss_ctrlclk { 912 #clock-cells = <0>; 913 compatible = "ti,gate-clock"; 914 clocks = <&func_96m_fclk>; 915 ti,bit-shift = <8>; 916 reg = <0x1320>; 917 }; 918 919 lli_txphy_clk: lli_txphy_clk { 920 #clock-cells = <0>; 921 compatible = "ti,gate-clock"; 922 clocks = <&dpll_unipro1_clkdcoldo>; 923 ti,bit-shift = <8>; 924 reg = <0x0f20>; 925 }; 926 927 lli_txphy_ls_clk: lli_txphy_ls_clk { 928 #clock-cells = <0>; 929 compatible = "ti,gate-clock"; 930 clocks = <&dpll_unipro1_m2_ck>; 931 ti,bit-shift = <9>; 932 reg = <0x0f20>; 933 }; 934 935 mmc1_32khz_clk: mmc1_32khz_clk { 936 #clock-cells = <0>; 937 compatible = "ti,gate-clock"; 938 clocks = <&sys_32k_ck>; 939 ti,bit-shift = <8>; 940 reg = <0x1628>; 941 }; 942 943 sata_ref_clk: sata_ref_clk { 944 #clock-cells = <0>; 945 compatible = "ti,gate-clock"; 946 clocks = <&sys_clkin>; 947 ti,bit-shift = <8>; 948 reg = <0x1688>; 949 }; 950 951 usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk { 952 #clock-cells = <0>; 953 compatible = "ti,gate-clock"; 954 clocks = <&dpll_usb_m2_ck>; 955 ti,bit-shift = <13>; 956 reg = <0x1658>; 957 }; 958 959 usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk { 960 #clock-cells = <0>; 961 compatible = "ti,gate-clock"; 962 clocks = <&dpll_usb_m2_ck>; 963 ti,bit-shift = <14>; 964 reg = <0x1658>; 965 }; 966 967 usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk { 968 #clock-cells = <0>; 969 compatible = "ti,gate-clock"; 970 clocks = <&dpll_usb_m2_ck>; 971 ti,bit-shift = <7>; 972 reg = <0x1658>; 973 }; 974 975 usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk { 976 #clock-cells = <0>; 977 compatible = "ti,gate-clock"; 978 clocks = <&l3init_60m_fclk>; 979 ti,bit-shift = <11>; 980 reg = <0x1658>; 981 }; 982 983 usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk { 984 #clock-cells = <0>; 985 compatible = "ti,gate-clock"; 986 clocks = <&l3init_60m_fclk>; 987 ti,bit-shift = <12>; 988 reg = <0x1658>; 989 }; 990 991 usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk { 992 #clock-cells = <0>; 993 compatible = "ti,gate-clock"; 994 clocks = <&l3init_60m_fclk>; 995 ti,bit-shift = <6>; 996 reg = <0x1658>; 997 }; 998 999 utmi_p1_gfclk: utmi_p1_gfclk { 1000 #clock-cells = <0>; 1001 compatible = "ti,mux-clock"; 1002 clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>; 1003 ti,bit-shift = <24>; 1004 reg = <0x1658>; 1005 }; 1006 1007 usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk { 1008 #clock-cells = <0>; 1009 compatible = "ti,gate-clock"; 1010 clocks = <&utmi_p1_gfclk>; 1011 ti,bit-shift = <8>; 1012 reg = <0x1658>; 1013 }; 1014 1015 utmi_p2_gfclk: utmi_p2_gfclk { 1016 #clock-cells = <0>; 1017 compatible = "ti,mux-clock"; 1018 clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>; 1019 ti,bit-shift = <25>; 1020 reg = <0x1658>; 1021 }; 1022 1023 usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk { 1024 #clock-cells = <0>; 1025 compatible = "ti,gate-clock"; 1026 clocks = <&utmi_p2_gfclk>; 1027 ti,bit-shift = <9>; 1028 reg = <0x1658>; 1029 }; 1030 1031 usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk { 1032 #clock-cells = <0>; 1033 compatible = "ti,gate-clock"; 1034 clocks = <&l3init_60m_fclk>; 1035 ti,bit-shift = <10>; 1036 reg = <0x1658>; 1037 }; 1038 1039 usb_otg_ss_refclk960m: usb_otg_ss_refclk960m { 1040 #clock-cells = <0>; 1041 compatible = "ti,gate-clock"; 1042 clocks = <&dpll_usb_clkdcoldo>; 1043 ti,bit-shift = <8>; 1044 reg = <0x16f0>; 1045 }; 1046 1047 usb_phy_cm_clk32k: usb_phy_cm_clk32k { 1048 #clock-cells = <0>; 1049 compatible = "ti,gate-clock"; 1050 clocks = <&sys_32k_ck>; 1051 ti,bit-shift = <8>; 1052 reg = <0x0640>; 1053 }; 1054 1055 usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk { 1056 #clock-cells = <0>; 1057 compatible = "ti,gate-clock"; 1058 clocks = <&l3init_60m_fclk>; 1059 ti,bit-shift = <8>; 1060 reg = <0x1668>; 1061 }; 1062 1063 usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk { 1064 #clock-cells = <0>; 1065 compatible = "ti,gate-clock"; 1066 clocks = <&l3init_60m_fclk>; 1067 ti,bit-shift = <9>; 1068 reg = <0x1668>; 1069 }; 1070 1071 usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk { 1072 #clock-cells = <0>; 1073 compatible = "ti,gate-clock"; 1074 clocks = <&l3init_60m_fclk>; 1075 ti,bit-shift = <10>; 1076 reg = <0x1668>; 1077 }; 1078 1079 fdif_fclk: fdif_fclk { 1080 #clock-cells = <0>; 1081 compatible = "ti,divider-clock"; 1082 clocks = <&dpll_per_h11x2_ck>; 1083 ti,bit-shift = <24>; 1084 ti,max-div = <2>; 1085 reg = <0x1328>; 1086 }; 1087 1088 gpu_core_gclk_mux: gpu_core_gclk_mux { 1089 #clock-cells = <0>; 1090 compatible = "ti,mux-clock"; 1091 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; 1092 ti,bit-shift = <24>; 1093 reg = <0x1520>; 1094 }; 1095 1096 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux { 1097 #clock-cells = <0>; 1098 compatible = "ti,mux-clock"; 1099 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; 1100 ti,bit-shift = <25>; 1101 reg = <0x1520>; 1102 }; 1103 1104 hsi_fclk: hsi_fclk { 1105 #clock-cells = <0>; 1106 compatible = "ti,divider-clock"; 1107 clocks = <&dpll_per_m2x2_ck>; 1108 ti,bit-shift = <24>; 1109 ti,max-div = <2>; 1110 reg = <0x1638>; 1111 }; 1112 1113 mmc1_fclk_mux: mmc1_fclk_mux { 1114 #clock-cells = <0>; 1115 compatible = "ti,mux-clock"; 1116 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; 1117 ti,bit-shift = <24>; 1118 reg = <0x1628>; 1119 }; 1120 1121 mmc1_fclk: mmc1_fclk { 1122 #clock-cells = <0>; 1123 compatible = "ti,divider-clock"; 1124 clocks = <&mmc1_fclk_mux>; 1125 ti,bit-shift = <25>; 1126 ti,max-div = <2>; 1127 reg = <0x1628>; 1128 }; 1129 1130 mmc2_fclk_mux: mmc2_fclk_mux { 1131 #clock-cells = <0>; 1132 compatible = "ti,mux-clock"; 1133 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; 1134 ti,bit-shift = <24>; 1135 reg = <0x1630>; 1136 }; 1137 1138 mmc2_fclk: mmc2_fclk { 1139 #clock-cells = <0>; 1140 compatible = "ti,divider-clock"; 1141 clocks = <&mmc2_fclk_mux>; 1142 ti,bit-shift = <25>; 1143 ti,max-div = <2>; 1144 reg = <0x1630>; 1145 }; 1146 1147 timer10_gfclk_mux: timer10_gfclk_mux { 1148 #clock-cells = <0>; 1149 compatible = "ti,mux-clock"; 1150 clocks = <&sys_clkin>, <&sys_32k_ck>; 1151 ti,bit-shift = <24>; 1152 reg = <0x1028>; 1153 }; 1154 1155 timer11_gfclk_mux: timer11_gfclk_mux { 1156 #clock-cells = <0>; 1157 compatible = "ti,mux-clock"; 1158 clocks = <&sys_clkin>, <&sys_32k_ck>; 1159 ti,bit-shift = <24>; 1160 reg = <0x1030>; 1161 }; 1162 1163 timer2_gfclk_mux: timer2_gfclk_mux { 1164 #clock-cells = <0>; 1165 compatible = "ti,mux-clock"; 1166 clocks = <&sys_clkin>, <&sys_32k_ck>; 1167 ti,bit-shift = <24>; 1168 reg = <0x1038>; 1169 }; 1170 1171 timer3_gfclk_mux: timer3_gfclk_mux { 1172 #clock-cells = <0>; 1173 compatible = "ti,mux-clock"; 1174 clocks = <&sys_clkin>, <&sys_32k_ck>; 1175 ti,bit-shift = <24>; 1176 reg = <0x1040>; 1177 }; 1178 1179 timer4_gfclk_mux: timer4_gfclk_mux { 1180 #clock-cells = <0>; 1181 compatible = "ti,mux-clock"; 1182 clocks = <&sys_clkin>, <&sys_32k_ck>; 1183 ti,bit-shift = <24>; 1184 reg = <0x1048>; 1185 }; 1186 1187 timer9_gfclk_mux: timer9_gfclk_mux { 1188 #clock-cells = <0>; 1189 compatible = "ti,mux-clock"; 1190 clocks = <&sys_clkin>, <&sys_32k_ck>; 1191 ti,bit-shift = <24>; 1192 reg = <0x1050>; 1193 }; 1194}; 1195 1196&cm_core_clockdomains { 1197 l3init_clkdm: l3init_clkdm { 1198 compatible = "ti,clockdomain"; 1199 clocks = <&dpll_usb_ck>; 1200 }; 1201}; 1202 1203&scrm_clocks { 1204 auxclk0_src_gate_ck: auxclk0_src_gate_ck { 1205 #clock-cells = <0>; 1206 compatible = "ti,composite-no-wait-gate-clock"; 1207 clocks = <&dpll_core_m3x2_ck>; 1208 ti,bit-shift = <8>; 1209 reg = <0x0310>; 1210 }; 1211 1212 auxclk0_src_mux_ck: auxclk0_src_mux_ck { 1213 #clock-cells = <0>; 1214 compatible = "ti,composite-mux-clock"; 1215 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 1216 ti,bit-shift = <1>; 1217 reg = <0x0310>; 1218 }; 1219 1220 auxclk0_src_ck: auxclk0_src_ck { 1221 #clock-cells = <0>; 1222 compatible = "ti,composite-clock"; 1223 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; 1224 }; 1225 1226 auxclk0_ck: auxclk0_ck { 1227 #clock-cells = <0>; 1228 compatible = "ti,divider-clock"; 1229 clocks = <&auxclk0_src_ck>; 1230 ti,bit-shift = <16>; 1231 ti,max-div = <16>; 1232 reg = <0x0310>; 1233 }; 1234 1235 auxclk1_src_gate_ck: auxclk1_src_gate_ck { 1236 #clock-cells = <0>; 1237 compatible = "ti,composite-no-wait-gate-clock"; 1238 clocks = <&dpll_core_m3x2_ck>; 1239 ti,bit-shift = <8>; 1240 reg = <0x0314>; 1241 }; 1242 1243 auxclk1_src_mux_ck: auxclk1_src_mux_ck { 1244 #clock-cells = <0>; 1245 compatible = "ti,composite-mux-clock"; 1246 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 1247 ti,bit-shift = <1>; 1248 reg = <0x0314>; 1249 }; 1250 1251 auxclk1_src_ck: auxclk1_src_ck { 1252 #clock-cells = <0>; 1253 compatible = "ti,composite-clock"; 1254 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; 1255 }; 1256 1257 auxclk1_ck: auxclk1_ck { 1258 #clock-cells = <0>; 1259 compatible = "ti,divider-clock"; 1260 clocks = <&auxclk1_src_ck>; 1261 ti,bit-shift = <16>; 1262 ti,max-div = <16>; 1263 reg = <0x0314>; 1264 }; 1265 1266 auxclk2_src_gate_ck: auxclk2_src_gate_ck { 1267 #clock-cells = <0>; 1268 compatible = "ti,composite-no-wait-gate-clock"; 1269 clocks = <&dpll_core_m3x2_ck>; 1270 ti,bit-shift = <8>; 1271 reg = <0x0318>; 1272 }; 1273 1274 auxclk2_src_mux_ck: auxclk2_src_mux_ck { 1275 #clock-cells = <0>; 1276 compatible = "ti,composite-mux-clock"; 1277 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 1278 ti,bit-shift = <1>; 1279 reg = <0x0318>; 1280 }; 1281 1282 auxclk2_src_ck: auxclk2_src_ck { 1283 #clock-cells = <0>; 1284 compatible = "ti,composite-clock"; 1285 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; 1286 }; 1287 1288 auxclk2_ck: auxclk2_ck { 1289 #clock-cells = <0>; 1290 compatible = "ti,divider-clock"; 1291 clocks = <&auxclk2_src_ck>; 1292 ti,bit-shift = <16>; 1293 ti,max-div = <16>; 1294 reg = <0x0318>; 1295 }; 1296 1297 auxclk3_src_gate_ck: auxclk3_src_gate_ck { 1298 #clock-cells = <0>; 1299 compatible = "ti,composite-no-wait-gate-clock"; 1300 clocks = <&dpll_core_m3x2_ck>; 1301 ti,bit-shift = <8>; 1302 reg = <0x031c>; 1303 }; 1304 1305 auxclk3_src_mux_ck: auxclk3_src_mux_ck { 1306 #clock-cells = <0>; 1307 compatible = "ti,composite-mux-clock"; 1308 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 1309 ti,bit-shift = <1>; 1310 reg = <0x031c>; 1311 }; 1312 1313 auxclk3_src_ck: auxclk3_src_ck { 1314 #clock-cells = <0>; 1315 compatible = "ti,composite-clock"; 1316 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; 1317 }; 1318 1319 auxclk3_ck: auxclk3_ck { 1320 #clock-cells = <0>; 1321 compatible = "ti,divider-clock"; 1322 clocks = <&auxclk3_src_ck>; 1323 ti,bit-shift = <16>; 1324 ti,max-div = <16>; 1325 reg = <0x031c>; 1326 }; 1327 1328 auxclk4_src_gate_ck: auxclk4_src_gate_ck { 1329 #clock-cells = <0>; 1330 compatible = "ti,composite-no-wait-gate-clock"; 1331 clocks = <&dpll_core_m3x2_ck>; 1332 ti,bit-shift = <8>; 1333 reg = <0x0320>; 1334 }; 1335 1336 auxclk4_src_mux_ck: auxclk4_src_mux_ck { 1337 #clock-cells = <0>; 1338 compatible = "ti,composite-mux-clock"; 1339 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 1340 ti,bit-shift = <1>; 1341 reg = <0x0320>; 1342 }; 1343 1344 auxclk4_src_ck: auxclk4_src_ck { 1345 #clock-cells = <0>; 1346 compatible = "ti,composite-clock"; 1347 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; 1348 }; 1349 1350 auxclk4_ck: auxclk4_ck { 1351 #clock-cells = <0>; 1352 compatible = "ti,divider-clock"; 1353 clocks = <&auxclk4_src_ck>; 1354 ti,bit-shift = <16>; 1355 ti,max-div = <16>; 1356 reg = <0x0320>; 1357 }; 1358 1359 auxclkreq0_ck: auxclkreq0_ck { 1360 #clock-cells = <0>; 1361 compatible = "ti,mux-clock"; 1362 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; 1363 ti,bit-shift = <2>; 1364 reg = <0x0210>; 1365 }; 1366 1367 auxclkreq1_ck: auxclkreq1_ck { 1368 #clock-cells = <0>; 1369 compatible = "ti,mux-clock"; 1370 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; 1371 ti,bit-shift = <2>; 1372 reg = <0x0214>; 1373 }; 1374 1375 auxclkreq2_ck: auxclkreq2_ck { 1376 #clock-cells = <0>; 1377 compatible = "ti,mux-clock"; 1378 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; 1379 ti,bit-shift = <2>; 1380 reg = <0x0218>; 1381 }; 1382 1383 auxclkreq3_ck: auxclkreq3_ck { 1384 #clock-cells = <0>; 1385 compatible = "ti,mux-clock"; 1386 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; 1387 ti,bit-shift = <2>; 1388 reg = <0x021c>; 1389 }; 1390}; 1391