1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 #ifndef __RTL8188E_HAL_H__ 21 #define __RTL8188E_HAL_H__ 22 23 24 /* include HAL Related header after HAL Related compiling flags */ 25 #include "rtl8188e_spec.h" 26 #include "Hal8188EPhyReg.h" 27 #include "Hal8188EPhyCfg.h" 28 #include "rtl8188e_dm.h" 29 #include "rtl8188e_recv.h" 30 #include "rtl8188e_xmit.h" 31 #include "rtl8188e_cmd.h" 32 #include "pwrseq.h" 33 #include "rtw_efuse.h" 34 #include "rtw_sreset.h" 35 #include "odm_precomp.h" 36 37 /* Fw Array */ 38 #define Rtl8188E_FwImageArray Rtl8188EFwImgArray 39 #define Rtl8188E_FWImgArrayLength Rtl8188EFWImgArrayLength 40 41 #define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin" 42 #define RTL8188E_PHY_REG "rtl8188E\\PHY_REG_1T.txt" 43 #define RTL8188E_PHY_RADIO_A "rtl8188E\\radio_a_1T.txt" 44 #define RTL8188E_PHY_RADIO_B "rtl8188E\\radio_b_1T.txt" 45 #define RTL8188E_AGC_TAB "rtl8188E\\AGC_TAB_1T.txt" 46 #define RTL8188E_PHY_MACREG "rtl8188E\\MAC_REG.txt" 47 #define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt" 48 #define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt" 49 50 /* RTL8188E Power Configuration CMDs for USB/SDIO interfaces */ 51 #define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow 52 #define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow 53 #define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow 54 #define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow 55 #define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow 56 #define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow 57 #define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow 58 #define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow 59 #define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow 60 61 #define DRVINFO_SZ 4 /* unit is 8bytes */ 62 #define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0)) 63 64 /* download firmware related data structure */ 65 #define FW_8188E_SIZE 0x4000 /* 16384,16k */ 66 #define FW_8188E_START_ADDRESS 0x1000 67 #define FW_8188E_END_ADDRESS 0x1FFF /* 0x5FFF */ 68 69 #define MAX_PAGE_SIZE 4096 /* @ page : 4k bytes */ 70 71 #define IS_FW_HEADER_EXIST(_pFwHdr) \ 72 ((le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x92C0 || \ 73 (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88C0 || \ 74 (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x2300 || \ 75 (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88E0) 76 77 #define DRIVER_EARLY_INT_TIME 0x05 78 #define BCN_DMA_ATIME_INT_TIME 0x02 79 80 enum usb_rx_agg_mode { 81 USB_RX_AGG_DISABLE, 82 USB_RX_AGG_DMA, 83 USB_RX_AGG_USB, 84 USB_RX_AGG_MIX 85 }; 86 87 #define MAX_RX_DMA_BUFFER_SIZE_88E \ 88 0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8), 89 * WOLPattern(16*24)) */ 90 91 #define MAX_TX_REPORT_BUFFER_SIZE 0x0400 /* 1k */ 92 93 94 /* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */ 95 #define MAX_TX_QUEUE 9 96 97 #define TX_SELE_HQ BIT(0) /* High Queue */ 98 #define TX_SELE_LQ BIT(1) /* Low Queue */ 99 #define TX_SELE_NQ BIT(2) /* Normal Queue */ 100 101 /* Note: We will divide number of page equally for each queue other 102 * than public queue! */ 103 /* 22k = 22528 bytes = 176 pages (@page = 128 bytes) */ 104 /* must reserved about 7 pages for LPS => 176-7 = 169 (0xA9) */ 105 /* 2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS 106 * null-data */ 107 108 #define TX_TOTAL_PAGE_NUMBER_88E 0xA9/* 169 (21632=> 21k) */ 109 110 #define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1) 111 112 /* Note: For Normal Chip Setting ,modify later */ 113 #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER \ 114 TX_TOTAL_PAGE_NUMBER_88E /* 0xA9 , 0xb0=>176=>22k */ 115 #define WMM_NORMAL_TX_PAGE_BOUNDARY_88E \ 116 (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */ 117 118 /* Chip specific */ 119 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) 120 #define CHIP_BONDING_92C_1T2R 0x1 121 #define CHIP_BONDING_88C_USB_MCARD 0x2 122 #define CHIP_BONDING_88C_USB_HP 0x1 123 #include "HalVerDef.h" 124 #include "hal_com.h" 125 126 /* Channel Plan */ 127 enum ChannelPlan { 128 CHPL_FCC = 0, 129 CHPL_IC = 1, 130 CHPL_ETSI = 2, 131 CHPL_SPA = 3, 132 CHPL_FRANCE = 4, 133 CHPL_MKK = 5, 134 CHPL_MKK1 = 6, 135 CHPL_ISRAEL = 7, 136 CHPL_TELEC = 8, 137 CHPL_GLOBAL = 9, 138 CHPL_WORLD = 10, 139 }; 140 141 struct txpowerinfo24g { 142 u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 143 u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; 144 /* If only one tx, only BW20 and OFDM are used. */ 145 s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 146 s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 147 s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 148 s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 149 }; 150 151 #define EFUSE_REAL_CONTENT_LEN 512 152 #define EFUSE_MAX_SECTION 16 153 #define EFUSE_IC_ID_OFFSET 506 /* For some inferior IC purpose*/ 154 #define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN) 155 /* To prevent out of boundary programming case, */ 156 /* leave 1byte and program full section */ 157 /* 9bytes + 1byt + 5bytes and pre 1byte. */ 158 /* For worst case: */ 159 /* | 1byte|----8bytes----|1byte|--5bytes--| */ 160 /* | | Reserved(14bytes) | */ 161 162 /* PG data exclude header, dummy 6 bytes from CP test and reserved 1byte. */ 163 #define EFUSE_OOB_PROTECT_BYTES 15 164 165 #define HWSET_MAX_SIZE_88E 512 166 167 #define EFUSE_REAL_CONTENT_LEN_88E 256 168 #define EFUSE_MAP_LEN_88E 512 169 #define EFUSE_MAP_LEN EFUSE_MAP_LEN_88E 170 #define EFUSE_MAX_SECTION_88E 64 171 #define EFUSE_MAX_WORD_UNIT_88E 4 172 #define EFUSE_IC_ID_OFFSET_88E 506 173 #define AVAILABLE_EFUSE_ADDR_88E(addr) \ 174 (addr < EFUSE_REAL_CONTENT_LEN_88E) 175 /* To prevent out of boundary programming case, leave 1byte and program 176 * full section */ 177 /* 9bytes + 1byt + 5bytes and pre 1byte. */ 178 /* For worst case: */ 179 /* | 2byte|----8bytes----|1byte|--7bytes--| 92D */ 180 /* PG data exclude header, dummy 7 bytes from CP test and reserved 1byte. */ 181 #define EFUSE_OOB_PROTECT_BYTES_88E 18 182 #define EFUSE_PROTECT_BYTES_BANK_88E 16 183 184 /* EFUSE for BT definition */ 185 #define EFUSE_BT_REAL_CONTENT_LEN 1536 /* 512*3 */ 186 #define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */ 187 #define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */ 188 189 #define EFUSE_PROTECT_BYTES_BANK 16 190 191 struct hal_data_8188e { 192 struct HAL_VERSION VersionID; 193 u16 CustomerID; 194 u8 *pfirmware; 195 u32 fwsize; 196 u16 FirmwareVersion; 197 u16 FirmwareVersionRev; 198 u16 FirmwareSubVersion; 199 u16 FirmwareSignature; 200 u8 PGMaxGroup; 201 /* current WIFI_PHY values */ 202 u32 ReceiveConfig; 203 enum wireless_mode CurrentWirelessMode; 204 enum ht_channel_width CurrentChannelBW; 205 u8 CurrentChannel; 206 u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */ 207 208 u16 BasicRateSet; 209 210 /* rf_ctrl */ 211 u8 rf_chip; 212 u8 rf_type; 213 u8 NumTotalRFPath; 214 215 u8 BoardType; 216 217 /* EEPROM setting. */ 218 u16 EEPROMVID; 219 u16 EEPROMPID; 220 u16 EEPROMSVID; 221 u16 EEPROMSDID; 222 u8 EEPROMCustomerID; 223 u8 EEPROMSubCustomerID; 224 u8 EEPROMVersion; 225 u8 EEPROMRegulatory; 226 227 u8 bTXPowerDataReadFromEEPORM; 228 u8 EEPROMThermalMeter; 229 u8 bAPKThermalMeterIgnore; 230 231 bool EepromOrEfuse; 232 /* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */ 233 u8 EfuseMap[2][HWSET_MAX_SIZE_512]; 234 u8 EfuseUsedPercentage; 235 struct efuse_hal EfuseHal; 236 237 u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 238 u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 239 /* If only one tx, only BW20 and OFDM are used. */ 240 s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 241 s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 242 s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 243 s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 244 245 u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; 246 /* For HT 40MHZ pwr */ 247 u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; 248 /* For HT 40MHZ pwr */ 249 u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; 250 /* HT 20<->40 Pwr diff */ 251 u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; 252 /* For HT<->legacy pwr diff */ 253 u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; 254 /* For power group */ 255 u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; 256 u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; 257 258 u8 LegacyHTTxPowerDiff;/* Legacy to HT rate power diff */ 259 /* The current Tx Power Level */ 260 u8 CurrentCckTxPwrIdx; 261 u8 CurrentOfdm24GTxPwrIdx; 262 u8 CurrentBW2024GTxPwrIdx; 263 u8 CurrentBW4024GTxPwrIdx; 264 265 266 /* Read/write are allow for following hardware information variables */ 267 u8 framesync; 268 u32 framesyncC34; 269 u8 framesyncMonitor; 270 u8 DefaultInitialGain[4]; 271 u8 pwrGroupCnt; 272 u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; 273 u32 CCKTxPowerLevelOriginalOffset; 274 275 u8 CrystalCap; 276 u32 AntennaTxPath; /* Antenna path Tx */ 277 u32 AntennaRxPath; /* Antenna path Rx */ 278 u8 BluetoothCoexist; 279 u8 ExternalPA; 280 281 u8 bLedOpenDrain; /* Open-drain support for controlling the LED.*/ 282 283 u8 b1x1RecvCombine; /* for 1T1R receive combining */ 284 285 u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */ 286 287 struct bb_reg_def PHYRegDef[4]; /* Radio A/B/C/D */ 288 289 u32 RfRegChnlVal[2]; 290 291 /* RDG enable */ 292 bool bRDGEnable; 293 294 /* for host message to fw */ 295 u8 LastHMEBoxNum; 296 297 u8 RegTxPause; 298 /* Beacon function related global variable. */ 299 u32 RegBcnCtrlVal; 300 u8 RegFwHwTxQCtrl; 301 u8 RegReg542; 302 u8 RegCR_1; 303 304 struct dm_priv dmpriv; 305 struct odm_dm_struct odmpriv; 306 struct sreset_priv srestpriv; 307 308 u8 CurAntenna; 309 u8 AntDivCfg; 310 u8 TRxAntDivType; 311 312 313 u8 bDumpRxPkt;/* for debug */ 314 u8 bDumpTxPkt;/* for debug */ 315 u8 FwRsvdPageStartOffset; /* Reserve page start offset except 316 * beacon in TxQ. */ 317 318 /* 2010/08/09 MH Add CU power down mode. */ 319 bool pwrdown; 320 321 /* Add for dual MAC 0--Mac0 1--Mac1 */ 322 u32 interfaceIndex; 323 324 u8 OutEpQueueSel; 325 u8 OutEpNumber; 326 327 /* Add for USB aggreation mode dynamic shceme. */ 328 bool UsbRxHighSpeedMode; 329 330 /* 2010/11/22 MH Add for slim combo debug mode selective. */ 331 /* This is used for fix the drawback of CU TSMC-A/UMC-A cut. 332 * HW auto suspend ability. Close BT clock. */ 333 bool SlimComboDbg; 334 335 u16 EfuseUsedBytes; 336 337 /* Auto FSM to Turn On, include clock, isolation, power control 338 * for MAC only */ 339 u8 bMacPwrCtrlOn; 340 341 u32 UsbBulkOutSize; 342 343 /* Interrupt relatd register information. */ 344 u32 IntArray[3];/* HISR0,HISR1,HSISR */ 345 u32 IntrMask[3]; 346 u8 C2hArray[16]; 347 u8 UsbTxAggMode; 348 u8 UsbTxAggDescNum; 349 u16 HwRxPageSize; /* Hardware setting */ 350 u32 MaxUsbRxAggBlock; 351 352 enum usb_rx_agg_mode UsbRxAggMode; 353 u8 UsbRxAggBlockCount; /* USB Block count. Block size is 354 * 512-byte in high speed and 64-byte 355 * in full speed */ 356 u8 UsbRxAggBlockTimeout; 357 u8 UsbRxAggPageCount; /* 8192C DMA page count */ 358 u8 UsbRxAggPageTimeout; 359 }; 360 361 #define GET_HAL_DATA(__pAdapter) \ 362 ((struct hal_data_8188e *)((__pAdapter)->HalData)) 363 #define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type) 364 365 /* rtl8188e_hal_init.c */ 366 void _8051Reset88E(struct adapter *padapter); 367 void rtl8188e_InitializeFirmwareVars(struct adapter *padapter); 368 369 370 s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy); 371 372 /* EFuse */ 373 void Hal_InitPGData88E(struct adapter *padapter); 374 void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo); 375 void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo, 376 bool AutoLoadFail); 377 378 void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo, 379 bool AutoLoadFail); 380 void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo, 381 bool AutoLoadFail); 382 void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo, 383 bool AutoLoadFail); 384 void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent, 385 bool AutoLoadFail); 386 void Hal_ReadThermalMeter_88E(struct adapter *dapter, u8 *PROMContent, 387 bool AutoloadFail); 388 void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo, 389 bool AutoLoadFail); 390 void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo, 391 bool AutoLoadFail); 392 void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo, 393 bool AutoLoadFail); 394 395 void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc); 396 397 /* register */ 398 399 void rtl8188e_start_thread(struct adapter *padapter); 400 void rtl8188e_stop_thread(struct adapter *padapter); 401 402 s32 iol_execute(struct adapter *padapter, u8 control); 403 void iol_mode_enable(struct adapter *padapter, u8 enable); 404 s32 rtl8188e_iol_efuse_patch(struct adapter *padapter); 405 void rtw_cancel_all_timer(struct adapter *padapter); 406 407 #endif /* __RTL8188E_HAL_H__ */ 408