1/* 2 * sama5d3_uart.dtsi - Device Tree Include file for SAMA5D3 SoC with 3 * UART support 4 * 5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 6 * 7 * Licensed under GPLv2. 8 */ 9 10#include <dt-bindings/pinctrl/at91.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/clock/at91.h> 13 14/ { 15 aliases { 16 serial5 = &uart0; 17 serial6 = &uart1; 18 }; 19 20 ahb { 21 apb { 22 pinctrl@fffff200 { 23 uart0 { 24 pinctrl_uart0: uart0-0 { 25 atmel,pins = 26 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ 27 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ 28 }; 29 }; 30 31 uart1 { 32 pinctrl_uart1: uart1-0 { 33 atmel,pins = 34 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ 35 AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ 36 }; 37 }; 38 }; 39 40 pmc: pmc@fffffc00 { 41 periphck { 42 uart0_clk: uart0_clk { 43 #clock-cells = <0>; 44 reg = <16>; 45 atmel,clk-output-range = <0 83000000>; 46 }; 47 48 uart1_clk: uart1_clk { 49 #clock-cells = <0>; 50 reg = <17>; 51 atmel,clk-output-range = <0 83000000>; 52 }; 53 }; 54 }; 55 56 uart0: serial@f0024000 { 57 compatible = "atmel,at91sam9260-usart"; 58 reg = <0xf0024000 0x200>; 59 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_uart0>; 62 clocks = <&uart0_clk>; 63 clock-names = "usart"; 64 status = "disabled"; 65 }; 66 67 uart1: serial@f8028000 { 68 compatible = "atmel,at91sam9260-usart"; 69 reg = <0xf8028000 0x200>; 70 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_uart1>; 73 clocks = <&uart1_clk>; 74 clock-names = "usart"; 75 status = "disabled"; 76 }; 77 }; 78 }; 79}; 80