1/* 2 * Copyright (C) 2012 Altera <www.altera.com> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18#include "skeleton.dtsi" 19#include <dt-bindings/reset/altr,rst-mgr.h> 20 21/ { 22 #address-cells = <1>; 23 #size-cells = <1>; 24 25 aliases { 26 ethernet0 = &gmac0; 27 ethernet1 = &gmac1; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 timer0 = &timer0; 31 timer1 = &timer1; 32 timer2 = &timer2; 33 timer3 = &timer3; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 enable-method = "altr,socfpga-smp"; 40 41 cpu@0 { 42 compatible = "arm,cortex-a9"; 43 device_type = "cpu"; 44 reg = <0>; 45 next-level-cache = <&L2>; 46 }; 47 cpu@1 { 48 compatible = "arm,cortex-a9"; 49 device_type = "cpu"; 50 reg = <1>; 51 next-level-cache = <&L2>; 52 }; 53 }; 54 55 intc: intc@fffed000 { 56 compatible = "arm,cortex-a9-gic"; 57 #interrupt-cells = <3>; 58 interrupt-controller; 59 reg = <0xfffed000 0x1000>, 60 <0xfffec100 0x100>; 61 }; 62 63 soc { 64 #address-cells = <1>; 65 #size-cells = <1>; 66 compatible = "simple-bus"; 67 device_type = "soc"; 68 interrupt-parent = <&intc>; 69 ranges; 70 71 amba { 72 compatible = "arm,amba-bus"; 73 #address-cells = <1>; 74 #size-cells = <1>; 75 ranges; 76 77 pdma: pdma@ffe01000 { 78 compatible = "arm,pl330", "arm,primecell"; 79 reg = <0xffe01000 0x1000>; 80 interrupts = <0 104 4>, 81 <0 105 4>, 82 <0 106 4>, 83 <0 107 4>, 84 <0 108 4>, 85 <0 109 4>, 86 <0 110 4>, 87 <0 111 4>; 88 #dma-cells = <1>; 89 #dma-channels = <8>; 90 #dma-requests = <32>; 91 clocks = <&l4_main_clk>; 92 clock-names = "apb_pclk"; 93 }; 94 }; 95 96 can0: can@ffc00000 { 97 compatible = "bosch,d_can"; 98 reg = <0xffc00000 0x1000>; 99 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; 100 clocks = <&can0_clk>; 101 status = "disabled"; 102 }; 103 104 can1: can@ffc01000 { 105 compatible = "bosch,d_can"; 106 reg = <0xffc01000 0x1000>; 107 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; 108 clocks = <&can1_clk>; 109 status = "disabled"; 110 }; 111 112 clkmgr@ffd04000 { 113 compatible = "altr,clk-mgr"; 114 reg = <0xffd04000 0x1000>; 115 116 clocks { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 120 osc1: osc1 { 121 #clock-cells = <0>; 122 compatible = "fixed-clock"; 123 }; 124 125 osc2: osc2 { 126 #clock-cells = <0>; 127 compatible = "fixed-clock"; 128 }; 129 130 f2s_periph_ref_clk: f2s_periph_ref_clk { 131 #clock-cells = <0>; 132 compatible = "fixed-clock"; 133 }; 134 135 f2s_sdram_ref_clk: f2s_sdram_ref_clk { 136 #clock-cells = <0>; 137 compatible = "fixed-clock"; 138 }; 139 140 main_pll: main_pll { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 #clock-cells = <0>; 144 compatible = "altr,socfpga-pll-clock"; 145 clocks = <&osc1>; 146 reg = <0x40>; 147 148 mpuclk: mpuclk { 149 #clock-cells = <0>; 150 compatible = "altr,socfpga-perip-clk"; 151 clocks = <&main_pll>; 152 div-reg = <0xe0 0 9>; 153 reg = <0x48>; 154 }; 155 156 mainclk: mainclk { 157 #clock-cells = <0>; 158 compatible = "altr,socfpga-perip-clk"; 159 clocks = <&main_pll>; 160 div-reg = <0xe4 0 9>; 161 reg = <0x4C>; 162 }; 163 164 dbg_base_clk: dbg_base_clk { 165 #clock-cells = <0>; 166 compatible = "altr,socfpga-perip-clk"; 167 clocks = <&main_pll>, <&osc1>; 168 div-reg = <0xe8 0 9>; 169 reg = <0x50>; 170 }; 171 172 main_qspi_clk: main_qspi_clk { 173 #clock-cells = <0>; 174 compatible = "altr,socfpga-perip-clk"; 175 clocks = <&main_pll>; 176 reg = <0x54>; 177 }; 178 179 main_nand_sdmmc_clk: main_nand_sdmmc_clk { 180 #clock-cells = <0>; 181 compatible = "altr,socfpga-perip-clk"; 182 clocks = <&main_pll>; 183 reg = <0x58>; 184 }; 185 186 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { 187 #clock-cells = <0>; 188 compatible = "altr,socfpga-perip-clk"; 189 clocks = <&main_pll>; 190 reg = <0x5C>; 191 }; 192 }; 193 194 periph_pll: periph_pll { 195 #address-cells = <1>; 196 #size-cells = <0>; 197 #clock-cells = <0>; 198 compatible = "altr,socfpga-pll-clock"; 199 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; 200 reg = <0x80>; 201 202 emac0_clk: emac0_clk { 203 #clock-cells = <0>; 204 compatible = "altr,socfpga-perip-clk"; 205 clocks = <&periph_pll>; 206 reg = <0x88>; 207 }; 208 209 emac1_clk: emac1_clk { 210 #clock-cells = <0>; 211 compatible = "altr,socfpga-perip-clk"; 212 clocks = <&periph_pll>; 213 reg = <0x8C>; 214 }; 215 216 per_qspi_clk: per_qsi_clk { 217 #clock-cells = <0>; 218 compatible = "altr,socfpga-perip-clk"; 219 clocks = <&periph_pll>; 220 reg = <0x90>; 221 }; 222 223 per_nand_mmc_clk: per_nand_mmc_clk { 224 #clock-cells = <0>; 225 compatible = "altr,socfpga-perip-clk"; 226 clocks = <&periph_pll>; 227 reg = <0x94>; 228 }; 229 230 per_base_clk: per_base_clk { 231 #clock-cells = <0>; 232 compatible = "altr,socfpga-perip-clk"; 233 clocks = <&periph_pll>; 234 reg = <0x98>; 235 }; 236 237 h2f_usr1_clk: h2f_usr1_clk { 238 #clock-cells = <0>; 239 compatible = "altr,socfpga-perip-clk"; 240 clocks = <&periph_pll>; 241 reg = <0x9C>; 242 }; 243 }; 244 245 sdram_pll: sdram_pll { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 #clock-cells = <0>; 249 compatible = "altr,socfpga-pll-clock"; 250 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; 251 reg = <0xC0>; 252 253 ddr_dqs_clk: ddr_dqs_clk { 254 #clock-cells = <0>; 255 compatible = "altr,socfpga-perip-clk"; 256 clocks = <&sdram_pll>; 257 reg = <0xC8>; 258 }; 259 260 ddr_2x_dqs_clk: ddr_2x_dqs_clk { 261 #clock-cells = <0>; 262 compatible = "altr,socfpga-perip-clk"; 263 clocks = <&sdram_pll>; 264 reg = <0xCC>; 265 }; 266 267 ddr_dq_clk: ddr_dq_clk { 268 #clock-cells = <0>; 269 compatible = "altr,socfpga-perip-clk"; 270 clocks = <&sdram_pll>; 271 reg = <0xD0>; 272 }; 273 274 h2f_usr2_clk: h2f_usr2_clk { 275 #clock-cells = <0>; 276 compatible = "altr,socfpga-perip-clk"; 277 clocks = <&sdram_pll>; 278 reg = <0xD4>; 279 }; 280 }; 281 282 mpu_periph_clk: mpu_periph_clk { 283 #clock-cells = <0>; 284 compatible = "altr,socfpga-perip-clk"; 285 clocks = <&mpuclk>; 286 fixed-divider = <4>; 287 }; 288 289 mpu_l2_ram_clk: mpu_l2_ram_clk { 290 #clock-cells = <0>; 291 compatible = "altr,socfpga-perip-clk"; 292 clocks = <&mpuclk>; 293 fixed-divider = <2>; 294 }; 295 296 l4_main_clk: l4_main_clk { 297 #clock-cells = <0>; 298 compatible = "altr,socfpga-gate-clk"; 299 clocks = <&mainclk>; 300 clk-gate = <0x60 0>; 301 }; 302 303 l3_main_clk: l3_main_clk { 304 #clock-cells = <0>; 305 compatible = "altr,socfpga-perip-clk"; 306 clocks = <&mainclk>; 307 fixed-divider = <1>; 308 }; 309 310 l3_mp_clk: l3_mp_clk { 311 #clock-cells = <0>; 312 compatible = "altr,socfpga-gate-clk"; 313 clocks = <&mainclk>; 314 div-reg = <0x64 0 2>; 315 clk-gate = <0x60 1>; 316 }; 317 318 l3_sp_clk: l3_sp_clk { 319 #clock-cells = <0>; 320 compatible = "altr,socfpga-gate-clk"; 321 clocks = <&l3_mp_clk>; 322 div-reg = <0x64 2 2>; 323 }; 324 325 l4_mp_clk: l4_mp_clk { 326 #clock-cells = <0>; 327 compatible = "altr,socfpga-gate-clk"; 328 clocks = <&mainclk>, <&per_base_clk>; 329 div-reg = <0x64 4 3>; 330 clk-gate = <0x60 2>; 331 }; 332 333 l4_sp_clk: l4_sp_clk { 334 #clock-cells = <0>; 335 compatible = "altr,socfpga-gate-clk"; 336 clocks = <&mainclk>, <&per_base_clk>; 337 div-reg = <0x64 7 3>; 338 clk-gate = <0x60 3>; 339 }; 340 341 dbg_at_clk: dbg_at_clk { 342 #clock-cells = <0>; 343 compatible = "altr,socfpga-gate-clk"; 344 clocks = <&dbg_base_clk>; 345 div-reg = <0x68 0 2>; 346 clk-gate = <0x60 4>; 347 }; 348 349 dbg_clk: dbg_clk { 350 #clock-cells = <0>; 351 compatible = "altr,socfpga-gate-clk"; 352 clocks = <&dbg_at_clk>; 353 div-reg = <0x68 2 2>; 354 clk-gate = <0x60 5>; 355 }; 356 357 dbg_trace_clk: dbg_trace_clk { 358 #clock-cells = <0>; 359 compatible = "altr,socfpga-gate-clk"; 360 clocks = <&dbg_base_clk>; 361 div-reg = <0x6C 0 3>; 362 clk-gate = <0x60 6>; 363 }; 364 365 dbg_timer_clk: dbg_timer_clk { 366 #clock-cells = <0>; 367 compatible = "altr,socfpga-gate-clk"; 368 clocks = <&dbg_base_clk>; 369 clk-gate = <0x60 7>; 370 }; 371 372 cfg_clk: cfg_clk { 373 #clock-cells = <0>; 374 compatible = "altr,socfpga-gate-clk"; 375 clocks = <&cfg_h2f_usr0_clk>; 376 clk-gate = <0x60 8>; 377 }; 378 379 h2f_user0_clk: h2f_user0_clk { 380 #clock-cells = <0>; 381 compatible = "altr,socfpga-gate-clk"; 382 clocks = <&cfg_h2f_usr0_clk>; 383 clk-gate = <0x60 9>; 384 }; 385 386 emac_0_clk: emac_0_clk { 387 #clock-cells = <0>; 388 compatible = "altr,socfpga-gate-clk"; 389 clocks = <&emac0_clk>; 390 clk-gate = <0xa0 0>; 391 }; 392 393 emac_1_clk: emac_1_clk { 394 #clock-cells = <0>; 395 compatible = "altr,socfpga-gate-clk"; 396 clocks = <&emac1_clk>; 397 clk-gate = <0xa0 1>; 398 }; 399 400 usb_mp_clk: usb_mp_clk { 401 #clock-cells = <0>; 402 compatible = "altr,socfpga-gate-clk"; 403 clocks = <&per_base_clk>; 404 clk-gate = <0xa0 2>; 405 div-reg = <0xa4 0 3>; 406 }; 407 408 spi_m_clk: spi_m_clk { 409 #clock-cells = <0>; 410 compatible = "altr,socfpga-gate-clk"; 411 clocks = <&per_base_clk>; 412 clk-gate = <0xa0 3>; 413 div-reg = <0xa4 3 3>; 414 }; 415 416 can0_clk: can0_clk { 417 #clock-cells = <0>; 418 compatible = "altr,socfpga-gate-clk"; 419 clocks = <&per_base_clk>; 420 clk-gate = <0xa0 4>; 421 div-reg = <0xa4 6 3>; 422 }; 423 424 can1_clk: can1_clk { 425 #clock-cells = <0>; 426 compatible = "altr,socfpga-gate-clk"; 427 clocks = <&per_base_clk>; 428 clk-gate = <0xa0 5>; 429 div-reg = <0xa4 9 3>; 430 }; 431 432 gpio_db_clk: gpio_db_clk { 433 #clock-cells = <0>; 434 compatible = "altr,socfpga-gate-clk"; 435 clocks = <&per_base_clk>; 436 clk-gate = <0xa0 6>; 437 div-reg = <0xa8 0 24>; 438 }; 439 440 h2f_user1_clk: h2f_user1_clk { 441 #clock-cells = <0>; 442 compatible = "altr,socfpga-gate-clk"; 443 clocks = <&h2f_usr1_clk>; 444 clk-gate = <0xa0 7>; 445 }; 446 447 sdmmc_clk: sdmmc_clk { 448 #clock-cells = <0>; 449 compatible = "altr,socfpga-gate-clk"; 450 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 451 clk-gate = <0xa0 8>; 452 clk-phase = <0 135>; 453 }; 454 455 sdmmc_clk_divided: sdmmc_clk_divided { 456 #clock-cells = <0>; 457 compatible = "altr,socfpga-gate-clk"; 458 clocks = <&sdmmc_clk>; 459 clk-gate = <0xa0 8>; 460 fixed-divider = <4>; 461 }; 462 463 nand_x_clk: nand_x_clk { 464 #clock-cells = <0>; 465 compatible = "altr,socfpga-gate-clk"; 466 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 467 clk-gate = <0xa0 9>; 468 }; 469 470 nand_clk: nand_clk { 471 #clock-cells = <0>; 472 compatible = "altr,socfpga-gate-clk"; 473 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 474 clk-gate = <0xa0 10>; 475 fixed-divider = <4>; 476 }; 477 478 qspi_clk: qspi_clk { 479 #clock-cells = <0>; 480 compatible = "altr,socfpga-gate-clk"; 481 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; 482 clk-gate = <0xa0 11>; 483 }; 484 485 ddr_dqs_clk_gate: ddr_dqs_clk_gate { 486 #clock-cells = <0>; 487 compatible = "altr,socfpga-gate-clk"; 488 clocks = <&ddr_dqs_clk>; 489 clk-gate = <0xd8 0>; 490 }; 491 492 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { 493 #clock-cells = <0>; 494 compatible = "altr,socfpga-gate-clk"; 495 clocks = <&ddr_2x_dqs_clk>; 496 clk-gate = <0xd8 1>; 497 }; 498 499 ddr_dq_clk_gate: ddr_dq_clk_gate { 500 #clock-cells = <0>; 501 compatible = "altr,socfpga-gate-clk"; 502 clocks = <&ddr_dq_clk>; 503 clk-gate = <0xd8 2>; 504 }; 505 506 h2f_user2_clk: h2f_user2_clk { 507 #clock-cells = <0>; 508 compatible = "altr,socfpga-gate-clk"; 509 clocks = <&h2f_usr2_clk>; 510 clk-gate = <0xd8 3>; 511 }; 512 513 }; 514 }; 515 516 fpgamgr0: fpgamgr@ff706000 { 517 compatible = "altr,socfpga-fpga-mgr"; 518 reg = <0xff706000 0x1000 519 0xffb90000 0x1000>; 520 interrupts = <0 175 4>; 521 }; 522 523 gmac0: ethernet@ff700000 { 524 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 525 altr,sysmgr-syscon = <&sysmgr 0x60 0>; 526 reg = <0xff700000 0x2000>; 527 interrupts = <0 115 4>; 528 interrupt-names = "macirq"; 529 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 530 clocks = <&emac0_clk>; 531 clock-names = "stmmaceth"; 532 resets = <&rst EMAC0_RESET>; 533 reset-names = "stmmaceth"; 534 snps,multicast-filter-bins = <256>; 535 snps,perfect-filter-entries = <128>; 536 tx-fifo-depth = <4096>; 537 rx-fifo-depth = <4096>; 538 status = "disabled"; 539 }; 540 541 gmac1: ethernet@ff702000 { 542 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 543 altr,sysmgr-syscon = <&sysmgr 0x60 2>; 544 reg = <0xff702000 0x2000>; 545 interrupts = <0 120 4>; 546 interrupt-names = "macirq"; 547 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 548 clocks = <&emac1_clk>; 549 clock-names = "stmmaceth"; 550 resets = <&rst EMAC1_RESET>; 551 reset-names = "stmmaceth"; 552 snps,multicast-filter-bins = <256>; 553 snps,perfect-filter-entries = <128>; 554 tx-fifo-depth = <4096>; 555 rx-fifo-depth = <4096>; 556 status = "disabled"; 557 }; 558 559 gpio0: gpio@ff708000 { 560 #address-cells = <1>; 561 #size-cells = <0>; 562 compatible = "snps,dw-apb-gpio"; 563 reg = <0xff708000 0x1000>; 564 clocks = <&l4_mp_clk>; 565 status = "disabled"; 566 567 porta: gpio-controller@0 { 568 compatible = "snps,dw-apb-gpio-port"; 569 gpio-controller; 570 #gpio-cells = <2>; 571 snps,nr-gpios = <29>; 572 reg = <0>; 573 interrupt-controller; 574 #interrupt-cells = <2>; 575 interrupts = <0 164 4>; 576 }; 577 }; 578 579 gpio1: gpio@ff709000 { 580 #address-cells = <1>; 581 #size-cells = <0>; 582 compatible = "snps,dw-apb-gpio"; 583 reg = <0xff709000 0x1000>; 584 clocks = <&l4_mp_clk>; 585 status = "disabled"; 586 587 portb: gpio-controller@0 { 588 compatible = "snps,dw-apb-gpio-port"; 589 gpio-controller; 590 #gpio-cells = <2>; 591 snps,nr-gpios = <29>; 592 reg = <0>; 593 interrupt-controller; 594 #interrupt-cells = <2>; 595 interrupts = <0 165 4>; 596 }; 597 }; 598 599 gpio2: gpio@ff70a000 { 600 #address-cells = <1>; 601 #size-cells = <0>; 602 compatible = "snps,dw-apb-gpio"; 603 reg = <0xff70a000 0x1000>; 604 clocks = <&l4_mp_clk>; 605 status = "disabled"; 606 607 portc: gpio-controller@0 { 608 compatible = "snps,dw-apb-gpio-port"; 609 gpio-controller; 610 #gpio-cells = <2>; 611 snps,nr-gpios = <27>; 612 reg = <0>; 613 interrupt-controller; 614 #interrupt-cells = <2>; 615 interrupts = <0 166 4>; 616 }; 617 }; 618 619 i2c0: i2c@ffc04000 { 620 #address-cells = <1>; 621 #size-cells = <0>; 622 compatible = "snps,designware-i2c"; 623 reg = <0xffc04000 0x1000>; 624 clocks = <&l4_sp_clk>; 625 interrupts = <0 158 0x4>; 626 status = "disabled"; 627 }; 628 629 i2c1: i2c@ffc05000 { 630 #address-cells = <1>; 631 #size-cells = <0>; 632 compatible = "snps,designware-i2c"; 633 reg = <0xffc05000 0x1000>; 634 clocks = <&l4_sp_clk>; 635 interrupts = <0 159 0x4>; 636 status = "disabled"; 637 }; 638 639 i2c2: i2c@ffc06000 { 640 #address-cells = <1>; 641 #size-cells = <0>; 642 compatible = "snps,designware-i2c"; 643 reg = <0xffc06000 0x1000>; 644 clocks = <&l4_sp_clk>; 645 interrupts = <0 160 0x4>; 646 status = "disabled"; 647 }; 648 649 i2c3: i2c@ffc07000 { 650 #address-cells = <1>; 651 #size-cells = <0>; 652 compatible = "snps,designware-i2c"; 653 reg = <0xffc07000 0x1000>; 654 clocks = <&l4_sp_clk>; 655 interrupts = <0 161 0x4>; 656 status = "disabled"; 657 }; 658 659 L2: l2-cache@fffef000 { 660 compatible = "arm,pl310-cache"; 661 reg = <0xfffef000 0x1000>; 662 interrupts = <0 38 0x04>; 663 cache-unified; 664 cache-level = <2>; 665 arm,tag-latency = <1 1 1>; 666 arm,data-latency = <2 1 1>; 667 prefetch-data = <1>; 668 prefetch-instr = <1>; 669 }; 670 671 mmc: dwmmc0@ff704000 { 672 compatible = "altr,socfpga-dw-mshc"; 673 reg = <0xff704000 0x1000>; 674 interrupts = <0 139 4>; 675 fifo-depth = <0x400>; 676 #address-cells = <1>; 677 #size-cells = <0>; 678 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; 679 clock-names = "biu", "ciu"; 680 }; 681 682 ocram: sram@ffff0000 { 683 compatible = "mmio-sram"; 684 reg = <0xffff0000 0x10000>; 685 }; 686 687 rst: rstmgr@ffd05000 { 688 #reset-cells = <1>; 689 compatible = "altr,rst-mgr"; 690 reg = <0xffd05000 0x1000>; 691 altr,modrst-offset = <0x10>; 692 }; 693 694 scu: snoop-control-unit@fffec000 { 695 compatible = "arm,cortex-a9-scu"; 696 reg = <0xfffec000 0x100>; 697 }; 698 699 sdr: sdr@ffc25000 { 700 compatible = "syscon"; 701 reg = <0xffc25000 0x1000>; 702 }; 703 704 sdramedac { 705 compatible = "altr,sdram-edac"; 706 altr,sdr-syscon = <&sdr>; 707 interrupts = <0 39 4>; 708 }; 709 710 spi0: spi@fff00000 { 711 compatible = "snps,dw-apb-ssi"; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 reg = <0xfff00000 0x1000>; 715 interrupts = <0 154 4>; 716 num-cs = <4>; 717 clocks = <&spi_m_clk>; 718 status = "disabled"; 719 }; 720 721 spi1: spi@fff01000 { 722 compatible = "snps,dw-apb-ssi"; 723 #address-cells = <1>; 724 #size-cells = <0>; 725 reg = <0xfff01000 0x1000>; 726 interrupts = <0 155 4>; 727 num-cs = <4>; 728 clocks = <&spi_m_clk>; 729 status = "disabled"; 730 }; 731 732 sysmgr: sysmgr@ffd08000 { 733 compatible = "altr,sys-mgr", "syscon"; 734 reg = <0xffd08000 0x4000>; 735 }; 736 737 /* Local timer */ 738 timer@fffec600 { 739 compatible = "arm,cortex-a9-twd-timer"; 740 reg = <0xfffec600 0x100>; 741 interrupts = <1 13 0xf01>; 742 clocks = <&mpu_periph_clk>; 743 }; 744 745 timer0: timer0@ffc08000 { 746 compatible = "snps,dw-apb-timer"; 747 interrupts = <0 167 4>; 748 reg = <0xffc08000 0x1000>; 749 clocks = <&l4_sp_clk>; 750 clock-names = "timer"; 751 }; 752 753 timer1: timer1@ffc09000 { 754 compatible = "snps,dw-apb-timer"; 755 interrupts = <0 168 4>; 756 reg = <0xffc09000 0x1000>; 757 clocks = <&l4_sp_clk>; 758 clock-names = "timer"; 759 }; 760 761 timer2: timer2@ffd00000 { 762 compatible = "snps,dw-apb-timer"; 763 interrupts = <0 169 4>; 764 reg = <0xffd00000 0x1000>; 765 clocks = <&osc1>; 766 clock-names = "timer"; 767 }; 768 769 timer3: timer3@ffd01000 { 770 compatible = "snps,dw-apb-timer"; 771 interrupts = <0 170 4>; 772 reg = <0xffd01000 0x1000>; 773 clocks = <&osc1>; 774 clock-names = "timer"; 775 }; 776 777 uart0: serial0@ffc02000 { 778 compatible = "snps,dw-apb-uart"; 779 reg = <0xffc02000 0x1000>; 780 interrupts = <0 162 4>; 781 reg-shift = <2>; 782 reg-io-width = <4>; 783 clocks = <&l4_sp_clk>; 784 dmas = <&pdma 28>, 785 <&pdma 29>; 786 dma-names = "tx", "rx"; 787 }; 788 789 uart1: serial1@ffc03000 { 790 compatible = "snps,dw-apb-uart"; 791 reg = <0xffc03000 0x1000>; 792 interrupts = <0 163 4>; 793 reg-shift = <2>; 794 reg-io-width = <4>; 795 clocks = <&l4_sp_clk>; 796 dmas = <&pdma 30>, 797 <&pdma 31>; 798 dma-names = "tx", "rx"; 799 }; 800 801 usbphy0: usbphy@0 { 802 #phy-cells = <0>; 803 compatible = "usb-nop-xceiv"; 804 status = "okay"; 805 }; 806 807 usb0: usb@ffb00000 { 808 compatible = "snps,dwc2"; 809 reg = <0xffb00000 0xffff>; 810 interrupts = <0 125 4>; 811 clocks = <&usb_mp_clk>; 812 clock-names = "otg"; 813 phys = <&usbphy0>; 814 phy-names = "usb2-phy"; 815 status = "disabled"; 816 }; 817 818 usb1: usb@ffb40000 { 819 compatible = "snps,dwc2"; 820 reg = <0xffb40000 0xffff>; 821 interrupts = <0 128 4>; 822 clocks = <&usb_mp_clk>; 823 clock-names = "otg"; 824 phys = <&usbphy0>; 825 phy-names = "usb2-phy"; 826 status = "disabled"; 827 }; 828 829 watchdog0: watchdog@ffd02000 { 830 compatible = "snps,dw-wdt"; 831 reg = <0xffd02000 0x1000>; 832 interrupts = <0 171 4>; 833 clocks = <&osc1>; 834 status = "disabled"; 835 }; 836 837 watchdog1: watchdog@ffd03000 { 838 compatible = "snps,dw-wdt"; 839 reg = <0xffd03000 0x1000>; 840 interrupts = <0 172 4>; 841 clocks = <&osc1>; 842 status = "disabled"; 843 }; 844 }; 845}; 846