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Searched refs:A0StP (Results 1 – 14 of 14) sorted by relevance

/arch/metag/kernel/
Dhead.S34 MOVT A0StP,#HI(_init_thread_union)
35 ADD A0StP,A0StP,#LO(_init_thread_union)
36 ADD A0StP,A0StP,#THREAD_INFO_SIZE
59 MOVT A0StP,#HI(_secondary_data_stack)
60 ADD A0StP,A0StP,#LO(_secondary_data_stack)
61 GETD A0StP,[A0StP]
62 ADD A0StP,A0StP,#THREAD_INFO_SIZE
Dftrace_stub.S19 MSETL [A0StP], D0Ar6, D0Ar4, D0Ar2, D0.4
28 GETL D0.4, D1RtP, [A0StP++#(-8)]
29 GETL D0Ar2, D1Ar1, [A0StP++#(-8)]
30 GETL D0Ar4, D1Ar3, [A0StP++#(-8)]
31 GETL D0Ar6, D1Ar5, [A0StP++#(-8)]
38 MSETL [A0StP], D0Ar6, D0Ar4, D0Ar2, D0.4
52 GETL D0.4, D1RtP, [A0StP++#(-8)]
53 GETL D0Ar2, D1Ar1, [A0StP++#(-8)]
54 GETL D0Ar4, D1Ar3, [A0StP++#(-8)]
55 GETL D0Ar6, D1Ar5, [A0StP++#(-8)]
Dtbiunexp.S15 MSETL [A0StP],D0Ar6,D0Ar4,D0Ar2 ! Save args on stack
16 SETL [A0StP++],D0Ar2,D1Ar1 ! Init area for returned values
19 GETL D0Re0,D1Re0,[--A0StP] ! Get result
20 SUB A0StP,A0StP,#(8*3) ! Recover stack frame
Dirq.c59 sp = __core_reg_get(A0StP); in do_IRQ()
/arch/metag/tbx/
Dtbilogf.S24 MSETL [A0StP],D0Ar6,D0Ar4,D0Ar2
27 SUB A0StP,A0StP,#24
40 MSETL [A0StP],D0Ar6,D0Ar4,D0Ar2
42 SUB A0StP,A0StP,#(8*3)
Dtbisoft.S75 ADD A0FrP,A0StP,#0
76 SETL [A0StP+#8++],D0FrT,D1RtP
84 SETD [D1Ar3],A0StP /* Record pCtx of this thread */
86 SETL [A0StP++],D0Re0,D1Re0 /* Push header fields */
87 ADD D0FrT,A0StP,#TBICTX_AX-TBICTX_DX /* Address AX save area */
90 MSETL [A0StP],D0Re0,D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
91 SETL [A0StP++],D0Re0,D1Re0 /* Zero CurrRPT, CurrBPOBITS, */
92 SETL [A0StP++],D0Re0,D1Re0 /* Zero CurrMODE, CurrDIVTIME */
93 ADD A0StP,A0StP,#(TBICTX_AX_REGS*8) /* Reserve AX save space */
94 MSETL [D0FrT],A0StP,A0FrP,A0.2,A0.3 A0_4 /* Save AX regs */
[all …]
Dtbidspram.S31 SETL [A0StP++], D0.5, D1.5
52 GETL D0.5, D1.5, [--A0StP]
65 SETL [A0StP++], D0.5, D1.5
86 GETL D0.5, D1.5, [--A0StP]
99 SETL [A0StP++], D0.5, D1.5
120 GETL D0.5, D1.5, [--A0StP]
133 SETL [A0StP++], D0.5, D1.5
154 GETL D0.5, D1.5, [--A0StP]
Dtbipcx.S69 ADD A0FrP,A0StP,#0
70 SETL [A0StP++],D0FrT,D1RtP
77 MOV A0.2,A0StP /* else push context here */
98 MSETL [D0FrT],A0StP,A0FrP,A0.2,A0.3 A0_4 /* Save AX regs */
117 MGETL A0StP,A0FrP,A0.2,A0.3 A0_4,[D1Re0] /* Restore AX regs */
126 SETL [A0StP+#TBICTX_DX],D0Re0,D1Re0 /* Save key registers */
127 ADD D1Re0,A0StP,#TBICTX_AX /* Address AX save area */
130 MSETL [D1Re0],A0StP,A0FrP,A0.2,A0.3 A0_4 /* Save AX critical regs */
140 ADD A1.2,A0StP,#TBICTX_DX+(8*1) /* Address DX.1 save area */
141 MOV A0FrP,A0StP /* Setup frame pointer */
[all …]
Dtbidefr.S28 MSETL [A0StP++], D0FrT, D0.5
103 GETL D0.5, D1.5, [--A0StP]
104 GETL D0FrT, D1RtP, [--A0StP]
Dtbicore.S92 SETL [A0StP++],D0FrT,D1RtP /* Save our return address */
97 GETL D0FrT,D1RtP,[--A0StP] /* Restore return address */
Dtbictx.S60 ADD A0FrP,A0StP,#0 /* can make sub-calls */
61 MSETL [A0StP],D0FrT,D0.5,D0.6 /* and preserve our result */
72 SUB A0StP,A0FrP,#(8*3)
/arch/metag/lib/
Ddiv64.S78 MSETL [A0StP],D0FrT,D0.5
104 GETL D0FrT,D1RtP,[A0StP+#(-16)]
105 GETL D0.5,D1.5,[A0StP+#(-8)]
106 SUB A0StP,A0StP,#16
Dmemmove.S14 MSETL [A0StP], D0.5, D0.6, D0.7
61 SUB A0.2, A0StP, #24
63 SUB A0StP, A0StP, #24
/arch/metag/include/asm/
Dmetag_regs.h131 #define A0StP A0.0 macro