Home
last modified time | relevance | path

Searched refs:A1 (Results 1 – 25 of 51) sorted by relevance

123

/arch/blackfin/lib/
Dmuldi3.S51 A0 = R2.H * R1.L, A1 = R2.L * R1.H (FU) || R3 = [SP + 12]; /* E1 */
52 A0 += R3.H * R0.L, A1 += R3.L * R0.H (FU) || [SP] = R4; /* E1 */
53 A0 += A1; /* E1 */
58 A1 = R2.L * R0.L (FU); /* E4 */ define
59 R3 = A1.w;
60 A1 = A1 >> 16; /* E3c */ define
61 A0 += R2.H * R0.H, A1 += R2.L * R0.H (FU); /* E2, E3c */
62 A1 += R0.L * R2.H (FU); /* E3c */
63 R0 = A1.w;
64 A1 = A1 >> 16; /* E2c */ define
[all …]
/arch/metag/lib/
Dmemmove.S28 MOV A1.2, D0Ar2
46 GETL D0Re0, D1Re0, [--A1.2]
54 GETB D1Re0, [--A1.2]
68 GETB D0Re0, [--A1.2]
77 ! adjust A1.2
78 MOV D0Ar4, A1.2
80 MOV D0Ar6, A1.2
85 MOV A1.2, D0Ar4
96 GETL D0Re0, D1Re0, [--A1.2]
111 GETL D0.7, D1.7, [--A1.2]
[all …]
Dmemcpy.S12 MOV A1.2, D0Ar2 ! source pointer
23 GETB D1Re0, [A1.2++]
41 GETB D0Re0, [A1.2++]
52 MOV D0Ar4, A1.2
64 GETL D0Re0, D1Re0, [A1.2++]
65 GETL D0Ar6, D1Ar5, [A1.2++]
68 GETL D0Re0, D1Re0, [A1.2++]
69 GETL D0Ar6, D1Ar5, [A1.2++]
82 ! Adjust the source pointer (A1.2) to the 8 byte boundary before its
84 MOV D0Ar4, A1.2
[all …]
Dmemset.S33 MOV A1.2,A0.2
38 SETL [D1Ar1++],A0.2,A1.2
39 SETL [D1Ar1++],A0.2,A1.2
40 SETL [D1Ar1++],A0.2,A1.2
41 SETL [D1Ar1++],A0.2,A1.2
55 SETL [D1Ar1++],A0.2,A1.2
70 MOV A1.2,D1Ar5
71 SUB PC,CPC1,A1.2 ! Jump into table below
/arch/c6x/lib/
Dcsum_64plus.S36 AND .S1 3,A4,A1
38 OR .L2X B0,A1,B0 ; non aligned condition
41 || MV .D1X B5,A1 ; words condition
42 [!A1] B .S1 L8
59 ZERO .D1 A1
63 [!A1] BNOP .S1 L8,5
300 || ZERO .D1 A1
304 || [A0] LDBU .D1T1 *A4++,A1
309 || SHL .S1 A0,8,A1
321 || ADD .L1 A0,A1,A1
[all …]
Ddivi.S22 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
23 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
24 ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
25 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
41 || cmpgt .l1 0, A4, A1
44 [A1] neg .l1 A4, A4
46 || xor .s1x A1, B1, A1
47 [A1] addkpc .s2 _divu_ret, B3, 4
Dmemcpy_64plus.S17 || AND .S1 0x2,A6,A1
23 [A1] LDB .D2T1 *B4++,A7
24 [A1] LDB .D2T1 *B4++,A8
31 [A1] STB .D1T1 A7,*A3++
32 [A1] STB .D1T1 A8,*A3++
Dllshr.S24 mv .l1x B4,A1
25 [!A1] b .s2 B3 ; return if zero shift count
27 sub .d1 A0,A1,A0
32 || [A2] shru .s1 A4,A1,A4
36 [A2] shr .s1 A5,A1,A5
Dllshru.S24 mv .l1x B4,A1
25 [!A1] b .s2 B3 ; return if zero shift count
27 sub .d1 A0,A1,A0
32 || [A2] shru .s1 A4,A1,A4
36 [A2] shru .s1 A5,A1,A5
Dllshl.S24 mv .l1x B4,A1
25 [!A1] b .s2 B3 ; just return if zero shift
27 sub .d1 A0,A1,A0
31 || [A2] shl .s1 A5,A1,A5
35 [A2] shl .s1 A4,A1,A4
Dremi.S22 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
23 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
24 ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
25 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
41 || cmpgt .l1 0, A4, A1
46 [A1] neg .l1 A4, A4
48 || xor .s2x B2, A1, B0
Dremu.S22 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
23 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
24 ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
25 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
51 cmpltu .l1x A4, B4, A1
52 [!A1] sub .l1x A4, B4, A4
Ddivremi.S23 || cmpgt .l1 0, A4, A1
28 [A1] neg .l1 A4, A4
30 || xor .s2x B2, A1, B0
Ddivu.S22 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
23 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
24 ;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
25 ;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
90 || mvk .s1 32, A1
91 sub .l1 A1, A6, A6
Dstrasgi.S27 ldw .d2t1 *B4++, A1
41 || mv .s2x A1, B5
48 [B0] ldw .d2t1 *B4++, A1
78 [B0] stw .d1t1 A1, *A4++
Dmpyll.S40 mpy32u .m1x A4,B4,A1:A0 ; X0*Y0
48 add .s1 A1,A5,A5
/arch/mips/mm/
Dpage.c44 #define A1 5 macro
362 uasm_i_ld(buf, reg, off, A1); in build_copy_load()
364 uasm_i_lw(buf, reg, off, A1); in build_copy_load()
383 _uasm_i_pref(buf, pref_src_mode, pref_bias_copy_load + off, A1); in build_copy_load_pref()
484 pg_addiu(&buf, A1, A1, 2 * off); in build_copy_page()
529 pg_addiu(&buf, A1, A1, 2 * off); in build_copy_page()
567 pg_addiu(&buf, A1, A1, 2 * off); in build_copy_page()
/arch/metag/tbx/
Dtbitimer.S181 MOV A1.3,A1LbP /* Get ___TBITimes address */
186 GETD A0.3,[A1.3+#0] /* A0.3 == &___TBITimeB */
194 GETD A0.3,[A1.3+#4] /* A0.3 == &___TBITimeI */
Dtbipcx.S53 #define A1GblIGbP A1.15 /* Interrupt A1GbP value in PRIV system */
140 ADD A1.2,A0StP,#TBICTX_DX+(8*1) /* Address DX.1 save area */
142 MSETL [A1.2],D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
153 MSETL [A1.2],D0Ar4,D0Ar2 /* Save CT regs state */
260 MOV D1Ar3,A1.3 /* Copy old TXDIVTIME */
284 MOV TXDIVTIME,A1.3 /* Set RPDIRTY again */
297 MOV TXBPOBITS,A1.2
Dtbictx.S104 MOV A1.2,D1RtP /* Free off D0FrT:D1RtP pair */
210 MOVZ PC,A1.2 /* No: Early return */
212 MOVZ PC,A1.2 /* No: Early return */
233 MOV PC,A1.2 /* Return */
276 MOV A1.2,D1RtP /* Free off D1RtP register */
304 MOVZ PC,A1.2 /* No: Early return */
361 MOV PC,A1.2 /* Return */
/arch/m68k/fpsp040/
Dsatan.S317 |--U + A1*U*V*(A2 + V*(A3 + V)), V = U*U
319 |--THE NATURAL FORM IS U + U*V*(A1 + V*(A2 + V*A3))
320 |--WHAT WE HAVE HERE IS MERELY A1 = A3, A2 = A1/A3, A3 = A2/A3.
322 |--PARTS A1*U*V AND (A2 + ... STUFF) MORE LOAD-BALANCED
332 fmuld ATANA1,%fp1 | ...A1*U*V
333 fmulx %fp2,%fp1 | ...A1*U*V*(A2+V*(A3+V))
/arch/c6x/kernel/
Dswitch_to.S53 || LDDW .D1T1 *+A5(THREAD_RICL_ICL),A1:A0
71 || MV .L2X A1,B1
Dentry.S94 || STDW .D1T1 A1:A0,*A15--[1]
151 LDDW .D1T1 *++A15[1],A1:A0
258 MVKL .S1 schedule,A1
259 MVKH .S1 schedule,A1
260 B .S2X A1
313 MVK .S1 _TIF_WORK_MASK,A1
316 AND .D1 A1,A2,A0
/arch/h8300/lib/
Dudivsi3.S12 divxu.w A1,A2P
14 divxu.w A1,A0P
/arch/arm/boot/dts/
Dkirkwood-dns320.dts6 model = "D-Link DNS-320 NAS (Rev A1)";

123